# Reading C:/altera/13.0/modelsim_ase/tcl/vsim/pref.tcl 
# ERROR: No extended dataflow license exists
# do pwn_run_msim_rtl_verilog.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying C:\altera\13.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied C:\altera\13.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
# 
# vlog -vlog01compat -work work +incdir+D:/code/beep/rtl {D:/code/beep/rtl/pwn.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module pwn
# 
# Top level modules:
# 	pwn
# 
# vlog -vlog01compat -work work +incdir+D:/code/beep/prj/../testbench {D:/code/beep/prj/../testbench/pwn_tb.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module pwn_tb
# 
# Top level modules:
# 	pwn_tb
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  pwn_tb
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps pwn_tb 
# Loading work.pwn_tb
# Loading work.pwn
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
# Break key hit 
# Break in Module pwn at D:/code/beep/rtl/pwn.v line 20
