Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\data\ipcores\gw_jtag.v
D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\bin\Documents\UART_RAM\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 Education
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version B
Created Time Fri Jul 31 18:15:52 2026
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.287s, Peak memory usage = 38.527MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 38.527MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 38.527MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 38.527MB
    Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.086s, Peak memory usage = 38.527MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 38.527MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 38.527MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.527MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.527MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 38.527MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 38.527MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 38.527MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 62.703MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 62.703MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 62.703MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 62.703MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 6
I/O Buf 6
    IBUF 5
    OBUF 1
Register 282
    DFFRE 1
    DFFPE 36
    DFFCE 245
LUT 426
    LUT2 59
    LUT3 117
    LUT4 250
MUX 1
    MUX16 1
ALU 15
    ALU 15
INV 4
    INV 4
BSRAM 1
    SDPB 1
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 453(438 LUT, 15 ALU) / 23040 2%
Register 282 / 23685 2%
  --Register as Latch 0 / 23685 0%
  --Register as FF 282 / 23685 2%
BSRAM 1 / 56 2%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 250.564(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.009
Data Arrival Time 4.240
Data Required Time 10.249
From u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
To u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 74 clk_ibuf/O
0.300 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
0.606 0.306 tC2Q RR 6 u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/Q
0.906 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n132_s1/I0
1.327 0.421 tINS RR 4 u_la0_top/u_ao_mem_ctrl/n132_s1/F
1.627 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n129_s2/I3
1.837 0.210 tINS RR 3 u_la0_top/u_ao_mem_ctrl/n129_s2/F
2.137 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n128_s1/I1
2.550 0.413 tINS RR 3 u_la0_top/u_ao_mem_ctrl/n128_s1/F
2.850 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n126_s1/I2
3.219 0.369 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n126_s1/F
3.519 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n126_s2/I0
3.940 0.421 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n126_s2/F
4.240 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 74 clk_ibuf/O
10.300 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
10.249 -0.051 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.834, 46.549%; route: 1.800, 45.685%; tC2Q: 0.306, 7.766%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 2

Path Summary:
Slack 6.009
Data Arrival Time 4.240
Data Required Time 10.249
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 74 clk_ibuf/O
0.300 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
0.606 0.306 tC2Q RR 5 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/Q
0.906 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n245_s3/I0
1.327 0.421 tINS RR 4 u_la0_top/u_ao_mem_ctrl/n245_s3/F
1.627 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n242_s2/I3
1.837 0.210 tINS RR 3 u_la0_top/u_ao_mem_ctrl/n242_s2/F
2.137 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n240_s2/I2
2.506 0.369 tINS RR 3 u_la0_top/u_ao_mem_ctrl/n240_s2/F
2.806 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n239_s2/I1
3.219 0.413 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n239_s2/F
3.519 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n239_s1/I0
3.940 0.421 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n239_s1/F
4.240 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 74 clk_ibuf/O
10.300 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
10.249 -0.051 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.834, 46.549%; route: 1.800, 45.685%; tC2Q: 0.306, 7.766%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 3

Path Summary:
Slack 6.053
Data Arrival Time 4.196
Data Required Time 10.249
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 74 clk_ibuf/O
0.300 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
0.606 0.306 tC2Q RR 5 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/Q
0.906 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n245_s3/I0
1.327 0.421 tINS RR 4 u_la0_top/u_ao_mem_ctrl/n245_s3/F
1.627 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n242_s2/I3
1.837 0.210 tINS RR 3 u_la0_top/u_ao_mem_ctrl/n242_s2/F
2.137 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n240_s2/I2
2.506 0.369 tINS RR 3 u_la0_top/u_ao_mem_ctrl/n240_s2/F
2.806 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n238_s3/I2
3.175 0.369 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n238_s3/F
3.475 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n238_s2/I0
3.896 0.421 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n238_s2/F
4.196 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 74 clk_ibuf/O
10.300 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLK
10.249 -0.051 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.790, 45.945%; route: 1.800, 46.201%; tC2Q: 0.306, 7.854%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 4

Path Summary:
Slack 6.220
Data Arrival Time 4.029
Data Required Time 10.249
From u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
To u_la0_top/u_ao_mem_ctrl/capture_length_11_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 74 clk_ibuf/O
0.300 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
0.606 0.306 tC2Q RR 6 u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/Q
0.906 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n132_s1/I0
1.327 0.421 tINS RR 4 u_la0_top/u_ao_mem_ctrl/n132_s1/F
1.627 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n129_s2/I3
1.837 0.210 tINS RR 3 u_la0_top/u_ao_mem_ctrl/n129_s2/F
2.137 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n128_s1/I1
2.550 0.413 tINS RR 3 u_la0_top/u_ao_mem_ctrl/n128_s1/F
2.850 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n125_s1/I3
3.060 0.210 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n125_s1/F
3.360 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n125_s0/I2
3.729 0.369 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n125_s0/F
4.029 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 74 clk_ibuf/O
10.300 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLK
10.249 -0.051 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_length_11_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.623, 43.524%; route: 1.800, 48.270%; tC2Q: 0.306, 8.206%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 5

Path Summary:
Slack 6.261
Data Arrival Time 3.790
Data Required Time 10.051
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 74 clk_ibuf/O
0.300 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.606 0.306 tC2Q RR 4 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
0.906 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n238_s7/I0
1.327 0.421 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n238_s7/F
1.627 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n238_s5/I0
2.048 0.421 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n238_s5/F
2.348 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n238_s4/I0
2.769 0.421 tINS RR 12 u_la0_top/u_ao_mem_ctrl/n238_s4/F
3.069 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
3.490 0.421 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
3.790 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 74 clk_ibuf/O
10.300 0.300 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.051 -0.249 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.684, 48.252%; route: 1.500, 42.980%; tC2Q: 0.306, 8.768%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%