Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\bin\Documents\UART_RAM\src\UART_RAM.v
D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\bin\Documents\UART_RAM\src\gowin_ram16sdp\gowin_ram16sdp.v
D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\bin\Documents\UART_RAM\src\key_filter.v
D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\bin\Documents\UART_RAM\src\uart_rx.v
D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\bin\Documents\UART_RAM\src\uart_tx.v
D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\bin\Documents\UART_RAM\src\user_ctrl.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 Education
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version B
Created Time Fri Jul 31 18:10:05 2026
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module UART_RAM
Synthesis Process Running parser:
    CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.182s, Peak memory usage = 590.383MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 590.383MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 590.383MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 590.383MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 590.383MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 590.383MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 590.383MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 590.383MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 590.383MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 590.383MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 590.383MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.312s, Peak memory usage = 590.383MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 590.383MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 590.383MB
Total Time and Memory Usage CPU time = 0h 0m 0.497s, Elapsed time = 0h 0m 0.579s, Peak memory usage = 590.383MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 6
I/O Buf 5
    IBUF 3
    OBUF 2
Register 40
    DFFPE 5
    DFFCE 35
LUT 64
    LUT2 10
    LUT3 16
    LUT4 38
INV 2
    INV 2

Resource Utilization Summary

Resource Usage Utilization
Logic 66(66 LUT, 0 ALU) / 23040 <1%
Register 40 / 23685 <1%
  --Register as Latch 0 / 23685 0%
  --Register as FF 40 / 23685 <1%
BSRAM 0 / 56 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 283.046(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.467
Data Arrival Time 3.782
Data Required Time 10.249
From key_filter_inst/cnt_15_s0
To key_filter_inst/cnt_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 40 clk_ibuf/O
0.300 0.300 tNET RR 1 key_filter_inst/cnt_15_s0/CLK
0.606 0.306 tC2Q RR 4 key_filter_inst/cnt_15_s0/Q
0.906 0.300 tNET RR 1 key_filter_inst/n114_s5/I0
1.327 0.421 tINS RR 1 key_filter_inst/n114_s5/F
1.627 0.300 tNET RR 1 key_filter_inst/n114_s2/I0
2.048 0.421 tINS RR 2 key_filter_inst/n114_s2/F
2.348 0.300 tNET RR 1 key_filter_inst/n113_s4/I0
2.769 0.421 tINS RR 22 key_filter_inst/n113_s4/F
3.069 0.300 tNET RR 1 key_filter_inst/n113_s3/I1
3.482 0.413 tINS RR 1 key_filter_inst/n113_s3/F
3.782 0.300 tNET RR 1 key_filter_inst/cnt_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 40 clk_ibuf/O
10.300 0.300 tNET RR 1 key_filter_inst/cnt_0_s0/CLK
10.249 -0.051 tSu 1 key_filter_inst/cnt_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.676, 48.133%; route: 1.500, 43.079%; tC2Q: 0.306, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 2

Path Summary:
Slack 6.467
Data Arrival Time 3.782
Data Required Time 10.249
From key_filter_inst/cnt_15_s0
To key_filter_inst/cnt_19_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 40 clk_ibuf/O
0.300 0.300 tNET RR 1 key_filter_inst/cnt_15_s0/CLK
0.606 0.306 tC2Q RR 4 key_filter_inst/cnt_15_s0/Q
0.906 0.300 tNET RR 1 key_filter_inst/n114_s5/I0
1.327 0.421 tINS RR 1 key_filter_inst/n114_s5/F
1.627 0.300 tNET RR 1 key_filter_inst/n114_s2/I0
2.048 0.421 tINS RR 2 key_filter_inst/n114_s2/F
2.348 0.300 tNET RR 1 key_filter_inst/n113_s4/I0
2.769 0.421 tINS RR 22 key_filter_inst/n113_s4/F
3.069 0.300 tNET RR 1 key_filter_inst/n94_s2/I1
3.482 0.413 tINS RR 1 key_filter_inst/n94_s2/F
3.782 0.300 tNET RR 1 key_filter_inst/cnt_19_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 40 clk_ibuf/O
10.300 0.300 tNET RR 1 key_filter_inst/cnt_19_s0/CLK
10.249 -0.051 tSu 1 key_filter_inst/cnt_19_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.676, 48.133%; route: 1.500, 43.079%; tC2Q: 0.306, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 3

Path Summary:
Slack 6.467
Data Arrival Time 3.782
Data Required Time 10.249
From key_filter_inst/cnt_15_s0
To key_filter_inst/cnt_20_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 40 clk_ibuf/O
0.300 0.300 tNET RR 1 key_filter_inst/cnt_15_s0/CLK
0.606 0.306 tC2Q RR 4 key_filter_inst/cnt_15_s0/Q
0.906 0.300 tNET RR 1 key_filter_inst/n114_s5/I0
1.327 0.421 tINS RR 1 key_filter_inst/n114_s5/F
1.627 0.300 tNET RR 1 key_filter_inst/n114_s2/I0
2.048 0.421 tINS RR 2 key_filter_inst/n114_s2/F
2.348 0.300 tNET RR 1 key_filter_inst/n113_s4/I0
2.769 0.421 tINS RR 22 key_filter_inst/n113_s4/F
3.069 0.300 tNET RR 1 key_filter_inst/n93_s2/I1
3.482 0.413 tINS RR 1 key_filter_inst/n93_s2/F
3.782 0.300 tNET RR 1 key_filter_inst/cnt_20_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 40 clk_ibuf/O
10.300 0.300 tNET RR 1 key_filter_inst/cnt_20_s0/CLK
10.249 -0.051 tSu 1 key_filter_inst/cnt_20_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.676, 48.133%; route: 1.500, 43.079%; tC2Q: 0.306, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 4

Path Summary:
Slack 6.467
Data Arrival Time 3.782
Data Required Time 10.249
From key_filter_inst/cnt_15_s0
To key_filter_inst/cnt_22_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 40 clk_ibuf/O
0.300 0.300 tNET RR 1 key_filter_inst/cnt_15_s0/CLK
0.606 0.306 tC2Q RR 4 key_filter_inst/cnt_15_s0/Q
0.906 0.300 tNET RR 1 key_filter_inst/n114_s5/I0
1.327 0.421 tINS RR 1 key_filter_inst/n114_s5/F
1.627 0.300 tNET RR 1 key_filter_inst/n114_s2/I0
2.048 0.421 tINS RR 2 key_filter_inst/n114_s2/F
2.348 0.300 tNET RR 1 key_filter_inst/n113_s4/I0
2.769 0.421 tINS RR 22 key_filter_inst/n113_s4/F
3.069 0.300 tNET RR 1 key_filter_inst/n91_s2/I1
3.482 0.413 tINS RR 1 key_filter_inst/n91_s2/F
3.782 0.300 tNET RR 1 key_filter_inst/cnt_22_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 40 clk_ibuf/O
10.300 0.300 tNET RR 1 key_filter_inst/cnt_22_s0/CLK
10.249 -0.051 tSu 1 key_filter_inst/cnt_22_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.676, 48.133%; route: 1.500, 43.079%; tC2Q: 0.306, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 5

Path Summary:
Slack 6.475
Data Arrival Time 3.774
Data Required Time 10.249
From key_filter_inst/cnt_0_s0
To key_filter_inst/cnt_25_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 40 clk_ibuf/O
0.300 0.300 tNET RR 1 key_filter_inst/cnt_0_s0/CLK
0.606 0.306 tC2Q RR 5 key_filter_inst/cnt_0_s0/Q
0.906 0.300 tNET RR 1 key_filter_inst/n109_s3/I0
1.327 0.421 tINS RR 8 key_filter_inst/n109_s3/F
1.627 0.300 tNET RR 1 key_filter_inst/n100_s3/I1
2.040 0.413 tINS RR 11 key_filter_inst/n100_s3/F
2.340 0.300 tNET RR 1 key_filter_inst/n88_s3/I0
2.761 0.421 tINS RR 1 key_filter_inst/n88_s3/F
3.061 0.300 tNET RR 1 key_filter_inst/n88_s2/I1
3.474 0.413 tINS RR 1 key_filter_inst/n88_s2/F
3.774 0.300 tNET RR 1 key_filter_inst/cnt_25_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 40 clk_ibuf/O
10.300 0.300 tNET RR 1 key_filter_inst/cnt_25_s0/CLK
10.249 -0.051 tSu 1 key_filter_inst/cnt_25_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.668, 48.014%; route: 1.500, 43.178%; tC2Q: 0.306, 8.808%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%