Timing Messages

Report Title	Timing Analysis Report
Design File	D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\bin\Documents\UART_RAM\impl\gwsynthesis\UART_RAM.vg
Physical Constraints File	D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\bin\Documents\UART_RAM\src\UART_RAM.cst
Timing Constraint File	D:\Gowin\Gowin_V1.9.11.03_Education_x64\IDE\bin\Documents\UART_RAM\src\UART_RAM.sdc
Tool Version	V1.9.11.03 Education
Part Number	GW5A-LV25UG324C2/I1
Device	GW5A-25
Device Version	B
Created Time	Fri Jul 31 18:16:01 2026
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C C2/I1
Hold Delay Model	Fast 0.945V 85C C2/I1
Numbers of Paths Analyzed	771
Numbers of Endpoints Analyzed	1006
Numbers of Falling Endpoints	10
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk	Base	10.000	100.000	0.000	5.000			clk_ibuf/I
2	tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.000(MHz)	239.923(MHz)	6	TOP
2	tck_pad_i	20.000(MHz)	79.344(MHz)	6	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	5.832	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q	u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/D	clk:[R]	clk:[R]	10.000	0.000	4.117
2	5.968	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/D	clk:[R]	clk:[R]	10.000	0.000	3.981
3	6.112	u_la0_top/triger_level_cnt_1_s1/Q	u_la0_top/trigger_seq_start_s1/CE	clk:[R]	clk:[R]	10.000	0.000	3.639
4	6.314	u_la0_top/triger_level_cnt_1_s1/Q	u_la0_top/triger_level_cnt_1_s1/CE	clk:[R]	clk:[R]	10.000	0.000	3.437
5	6.314	u_la0_top/triger_level_cnt_1_s1/Q	u_la0_top/triger_level_cnt_2_s1/CE	clk:[R]	clk:[R]	10.000	0.000	3.437
6	6.314	u_la0_top/triger_level_cnt_1_s1/Q	u_la0_top/triger_level_cnt_3_s1/CE	clk:[R]	clk:[R]	10.000	0.000	3.437
7	6.344	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D	clk:[R]	clk:[R]	10.000	-0.006	3.611
8	6.389	u_la0_top/capture_window_sel_3_s1/Q	u_la0_top/start_reg_s0/D	clk:[R]	clk:[R]	10.000	-0.004	3.564
9	6.569	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE	clk:[R]	clk:[R]	10.000	0.006	3.176
10	6.608	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/D	clk:[R]	clk:[R]	10.000	-0.006	3.347
11	6.654	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D	clk:[R]	clk:[R]	10.000	-0.004	3.299
12	6.663	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/Q	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE	clk:[R]	clk:[R]	10.000	0.002	3.086
13	6.677	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D	clk:[R]	clk:[R]	10.000	-0.004	3.276
14	6.677	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D	clk:[R]	clk:[R]	10.000	-0.004	3.276
15	6.776	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE	clk:[R]	clk:[R]	10.000	0.000	2.975
16	6.791	key_filter_inst/cnt_1_s0/Q	key_filter_inst/cnt_21_s0/D	clk:[R]	clk:[R]	10.000	-0.043	3.201
17	6.806	key_filter_inst/cnt_1_s0/Q	key_filter_inst/cnt_23_s0/D	clk:[R]	clk:[R]	10.000	-0.048	3.191
18	6.809	key_filter_inst/cnt_1_s0/Q	key_filter_inst/cnt_25_s0/D	clk:[R]	clk:[R]	10.000	-0.025	3.166
19	6.810	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/D	clk:[R]	clk:[R]	10.000	-0.006	3.145
20	6.854	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D	clk:[R]	clk:[R]	10.000	-0.006	3.101
21	6.885	key_filter_inst/cnt_1_s0/Q	key_filter_inst/cnt_19_s0/D	clk:[R]	clk:[R]	10.000	-0.048	3.112
22	6.888	u_la0_top/triger_level_cnt_1_s1/Q	u_la0_top/triger_level_cnt_0_s3/D	clk:[R]	clk:[R]	10.000	-0.002	3.063
23	6.888	u_la0_top/triger_level_cnt_1_s1/Q	u_la0_top/triger_s0/D	clk:[R]	clk:[R]	10.000	-0.002	3.063
24	6.928	key_filter_inst/cnt_1_s0/Q	key_filter_inst/cnt_20_s0/D	clk:[R]	clk:[R]	10.000	-0.050	3.071
25	6.931	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/D	clk:[R]	clk:[R]	10.000	0.003	3.015

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.227	u_la0_top/u_ao_match_0/trig_dly_in_0_s0/D	u_la0_top/u_ao_match_0/trig_dly_in_0_s0/D	clk:[R]	clk:[R]	0.000	-0.717	0.957
2	0.254	u_la0_top/address_counter_10_s0/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADB[11]	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.005	0.284
3	0.271	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[4]	clk:[R]	clk:[R]	0.000	0.016	0.292
4	0.275	u_la0_top/capture_end_tck_1_s0/Q	u_la0_top/capture_end_tck_2_s0/D	tck_pad_i:[F]	tck_pad_i:[F]	0.000	0.000	0.239
5	0.275	u_icon_top/enable_reg_1_s0/Q	u_icon_top/enable_reg_0_s0/D	tck_pad_i:[F]	tck_pad_i:[F]	0.000	0.000	0.239
6	0.275	u_icon_top/enable_reg_2_s0/Q	u_icon_top/enable_reg_1_s0/D	tck_pad_i:[F]	tck_pad_i:[F]	0.000	0.000	0.239
7	0.275	u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0/Q	u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
8	0.275	key_filter_inst/cnt_1_s0/Q	key_filter_inst/cnt_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.300
9	0.275	key_filter_inst/cnt_7_s0/Q	key_filter_inst/cnt_7_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.300
10	0.275	key_filter_inst/cnt_21_s0/Q	key_filter_inst/cnt_21_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.300
11	0.275	led_s3/Q	led_s3/D	clk:[R]	clk:[R]	0.000	0.000	0.300
12	0.278	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.303
13	0.278	key_filter_inst/state_0_s0/Q	key_filter_inst/state_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.303
14	0.278	key_filter_inst/cnt_16_s0/Q	key_filter_inst/cnt_16_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.303
15	0.278	key_filter_inst/cnt_24_s0/Q	key_filter_inst/cnt_24_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.303
16	0.278	u_icon_top/input_shift_reg_1_s0/Q	u_icon_top/input_shift_reg_0_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.225
17	0.278	u_icon_top/input_shift_reg_2_s0/Q	u_icon_top/input_shift_reg_1_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.225
18	0.278	u_icon_top/input_shift_reg_4_s0/Q	u_icon_top/input_shift_reg_3_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.225
19	0.278	u_icon_top/input_shift_reg_2_s0/Q	u_icon_top/module_id_reg_2_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.225
20	0.281	u_la0_top/internal_reg_start_dly_0_s0/Q	u_la0_top/internal_reg_start_dly_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.228
21	0.281	u_la0_top/triger_level_cnt_1_s1/Q	u_la0_top/triger_level_cnt_1_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.306
22	0.281	u_la0_top/word_count_14_s0/Q	u_la0_top/word_count_14_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.306
23	0.281	u_la0_top/data_register_17_s0/Q	u_la0_top/internal_register_select_1_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.228
24	0.281	u_la0_top/data_register_15_s0/Q	u_la0_top/data_register_14_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.228
25	0.281	u_la0_top/data_register_17_s0/Q	u_la0_top/data_register_16_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.228

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.696	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	5.000	0.012	3.014
2	1.696	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.012	3.014
3	1.696	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.012	3.014
4	1.696	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.012	3.014
5	1.696	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.012	3.014
6	1.696	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.012	3.014
7	1.703	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.005	3.014
8	1.703	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.005	3.014
9	1.703	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.005	3.014
10	1.703	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.005	3.014
11	1.718	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.007	2.997
12	1.718	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.007	2.997
13	1.718	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.007	2.997
14	1.718	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.007	2.997
15	1.718	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.007	2.997
16	1.718	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.007	2.997
17	1.718	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.007	2.997
18	1.725	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.014	2.983
19	1.725	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.014	2.983
20	1.725	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.014	2.983
21	1.725	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.014	2.983
22	1.725	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.018	2.979
23	1.725	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_5_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.005	2.992
24	1.725	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_6_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.005	2.992
25	1.725	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_7_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.005	2.992

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	6.627	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.007	1.567
2	6.627	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.007	1.567
3	6.627	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.007	1.567
4	6.630	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.003	1.574
5	6.631	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_0_s3/CLEAR	clk:[F]	clk:[R]	-5.000	0.003	1.575
6	6.631	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_0_s3/CLEAR	clk:[F]	clk:[R]	-5.000	0.003	1.575
7	6.631	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_end_dly_s0/PRESET	clk:[F]	clk:[R]	-5.000	0.003	1.575
8	6.631	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.003	1.575
9	6.631	u_la0_top/rst_ao_s0/Q	u_la0_top/start_reg_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.003	1.575
10	6.631	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.003	1.575
11	6.631	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_start_dly_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.003	1.575
12	6.631	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.010	1.567
13	6.631	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.010	1.567
14	6.631	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.010	1.567
15	6.631	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.010	1.567
16	6.631	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.010	1.567
17	6.631	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.010	1.567
18	6.631	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.010	1.567
19	6.632	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.006	1.573
20	6.632	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.006	1.573
21	6.632	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.006	1.573
22	6.632	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_4_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.006	1.573
23	6.634	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.005	1.577
24	6.634	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.005	1.577
25	6.634	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.005	1.577

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.279	4.141	0.862	Low Pulse Width	clk	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
2	3.289	4.151	0.862	High Pulse Width	clk	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
3	3.932	4.132	0.200	Low Pulse Width	clk	key_filter_inst/cnt_22_s0
4	3.932	4.132	0.200	Low Pulse Width	clk	key_filter_inst/cnt_20_s0
5	3.933	4.133	0.200	Low Pulse Width	clk	key_filter_inst/cnt_23_s0
6	3.933	4.133	0.200	Low Pulse Width	clk	key_filter_inst/cnt_19_s0
7	3.933	4.133	0.200	Low Pulse Width	clk	key_filter_inst/key_flag_s1
8	3.936	4.136	0.200	Low Pulse Width	clk	u_la0_top/internal_reg_start_dly_1_s0
9	3.936	4.136	0.200	Low Pulse Width	clk	u_la0_top/triger_level_cnt_0_s3
10	3.936	4.136	0.200	Low Pulse Width	clk	u_la0_top/capture_window_sel_0_s3

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	5.832
Data Arrival Time	6.269
Data Required Time	12.101
From	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
To	u_la0_top/u_ao_mem_ctrl/capture_length_11_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.152	1.565	tNET	RR	1	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
2.458	0.306	tC2Q	RR	5	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q
3.292	0.834	tNET	RR	1	R4C8[2][A]	u_la0_top/u_ao_mem_ctrl/n132_s1/I1
3.502	0.210	tINS	RR	4	R4C8[2][A]	u_la0_top/u_ao_mem_ctrl/n132_s1/F
4.091	0.589	tNET	RR	1	R6C7[3][B]	u_la0_top/u_ao_mem_ctrl/n129_s2/I3
4.508	0.417	tINS	RR	3	R6C7[3][B]	u_la0_top/u_ao_mem_ctrl/n129_s2/F
4.638	0.130	tNET	RR	1	R5C7[0][A]	u_la0_top/u_ao_mem_ctrl/n128_s1/I1
4.848	0.210	tINS	RR	3	R5C7[0][A]	u_la0_top/u_ao_mem_ctrl/n128_s1/F
4.978	0.130	tNET	RR	1	R6C7[1][B]	u_la0_top/u_ao_mem_ctrl/n125_s1/I3
5.347	0.369	tINS	RR	1	R6C7[1][B]	u_la0_top/u_ao_mem_ctrl/n125_s1/F
5.871	0.524	tNET	RR	1	R2C7[3][A]	u_la0_top/u_ao_mem_ctrl/n125_s0/I2
6.269	0.398	tINS	RR	1	R2C7[3][A]	u_la0_top/u_ao_mem_ctrl/n125_s0/F
6.269	0.000	tNET	RR	1	R2C7[3][A]	u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.152	1.565	tNET	RR	1	R2C7[3][A]	u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLK
12.101	-0.051	tSu		1	R2C7[3][A]	u_la0_top/u_ao_mem_ctrl/capture_length_11_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%
Arrival Data Path Delay	cell: 1.604, 38.960%; route: 2.207, 53.607%; tC2Q: 0.306, 7.433%
Required Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%

Path2

Path Summary:

Slack	5.968
Data Arrival Time	6.133
Data Required Time	12.101
From	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
To	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.152	1.565	tNET	RR	1	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
2.458	0.306	tC2Q	RR	5	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q
3.292	0.834	tNET	RR	1	R4C8[2][A]	u_la0_top/u_ao_mem_ctrl/n132_s1/I1
3.502	0.210	tINS	RR	4	R4C8[2][A]	u_la0_top/u_ao_mem_ctrl/n132_s1/F
4.091	0.589	tNET	RR	1	R6C7[3][B]	u_la0_top/u_ao_mem_ctrl/n129_s2/I3
4.508	0.417	tINS	RR	3	R6C7[3][B]	u_la0_top/u_ao_mem_ctrl/n129_s2/F
4.638	0.130	tNET	RR	1	R5C7[0][A]	u_la0_top/u_ao_mem_ctrl/n128_s1/I1
4.848	0.210	tINS	RR	3	R5C7[0][A]	u_la0_top/u_ao_mem_ctrl/n128_s1/F
4.854	0.006	tNET	RR	1	R5C7[0][B]	u_la0_top/u_ao_mem_ctrl/n126_s1/I2
5.064	0.210	tINS	RR	1	R5C7[0][B]	u_la0_top/u_ao_mem_ctrl/n126_s1/F
5.712	0.648	tNET	RR	1	R2C7[2][B]	u_la0_top/u_ao_mem_ctrl/n126_s2/I0
6.133	0.421	tINS	RR	1	R2C7[2][B]	u_la0_top/u_ao_mem_ctrl/n126_s2/F
6.133	0.000	tNET	RR	1	R2C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.152	1.565	tNET	RR	1	R2C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
12.101	-0.051	tSu		1	R2C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%
Arrival Data Path Delay	cell: 1.468, 36.875%; route: 2.207, 55.438%; tC2Q: 0.306, 7.687%
Required Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%

Path3

Path Summary:

Slack	6.112
Data Arrival Time	5.804
Data Required Time	11.916
From	u_la0_top/triger_level_cnt_1_s1
To	u_la0_top/trigger_seq_start_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.165	1.578	tNET	RR	1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/CLK
2.471	0.306	tC2Q	RR	5	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/Q
3.481	1.010	tNET	RR	1	R5C8[2][A]	u_la0_top/triger_level_cnt_3_s5/I0
3.850	0.369	tINS	RR	1	R5C8[2][A]	u_la0_top/triger_level_cnt_3_s5/F
3.852	0.002	tNET	RR	1	R5C8[1][B]	u_la0_top/triger_level_cnt_3_s4/I2
4.221	0.369	tINS	RR	4	R5C8[1][B]	u_la0_top/triger_level_cnt_3_s4/F
4.721	0.500	tNET	RR	1	R4C5[2][B]	u_la0_top/n1147_s1/I1
5.142	0.421	tINS	RR	1	R4C5[2][B]	u_la0_top/n1147_s1/F
5.144	0.002	tNET	RR	1	R4C5[3][A]	u_la0_top/trigger_seq_start_s3/I3
5.542	0.398	tINS	RR	1	R4C5[3][A]	u_la0_top/trigger_seq_start_s3/F
5.804	0.262	tNET	RR	1	R3C5[0][A]	u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.165	1.578	tNET	RR	1	R3C5[0][A]	u_la0_top/trigger_seq_start_s1/CLK
11.916	-0.249	tSu		1	R3C5[0][A]	u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.111%; route: 1.578, 72.889%
Arrival Data Path Delay	cell: 1.557, 42.786%; route: 1.776, 48.805%; tC2Q: 0.306, 8.409%
Required Clock Path Delay	cell: 0.587, 27.111%; route: 1.578, 72.889%

Path4

Path Summary:

Slack	6.314
Data Arrival Time	5.602
Data Required Time	11.916
From	u_la0_top/triger_level_cnt_1_s1
To	u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.165	1.578	tNET	RR	1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/CLK
2.471	0.306	tC2Q	RR	5	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/Q
3.481	1.010	tNET	RR	1	R5C8[2][A]	u_la0_top/triger_level_cnt_3_s5/I0
3.850	0.369	tINS	RR	1	R5C8[2][A]	u_la0_top/triger_level_cnt_3_s5/F
3.852	0.002	tNET	RR	1	R5C8[1][B]	u_la0_top/triger_level_cnt_3_s4/I2
4.221	0.369	tINS	RR	4	R5C8[1][B]	u_la0_top/triger_level_cnt_3_s4/F
4.721	0.500	tNET	RR	1	R3C5[2][B]	u_la0_top/triger_level_cnt_3_s6/I0
5.142	0.421	tINS	RR	3	R3C5[2][B]	u_la0_top/triger_level_cnt_3_s6/F
5.602	0.460	tNET	RR	1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.165	1.578	tNET	RR	1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/CLK
11.916	-0.249	tSu		1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.111%; route: 1.578, 72.889%
Arrival Data Path Delay	cell: 1.159, 33.721%; route: 1.972, 57.376%; tC2Q: 0.306, 8.903%
Required Clock Path Delay	cell: 0.587, 27.111%; route: 1.578, 72.889%

Path5

Path Summary:

Slack	6.314
Data Arrival Time	5.602
Data Required Time	11.916
From	u_la0_top/triger_level_cnt_1_s1
To	u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.165	1.578	tNET	RR	1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/CLK
2.471	0.306	tC2Q	RR	5	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/Q
3.481	1.010	tNET	RR	1	R5C8[2][A]	u_la0_top/triger_level_cnt_3_s5/I0
3.850	0.369	tINS	RR	1	R5C8[2][A]	u_la0_top/triger_level_cnt_3_s5/F
3.852	0.002	tNET	RR	1	R5C8[1][B]	u_la0_top/triger_level_cnt_3_s4/I2
4.221	0.369	tINS	RR	4	R5C8[1][B]	u_la0_top/triger_level_cnt_3_s4/F
4.721	0.500	tNET	RR	1	R3C5[2][B]	u_la0_top/triger_level_cnt_3_s6/I0
5.142	0.421	tINS	RR	3	R3C5[2][B]	u_la0_top/triger_level_cnt_3_s6/F
5.602	0.460	tNET	RR	1	R3C5[1][B]	u_la0_top/triger_level_cnt_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.165	1.578	tNET	RR	1	R3C5[1][B]	u_la0_top/triger_level_cnt_2_s1/CLK
11.916	-0.249	tSu		1	R3C5[1][B]	u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.111%; route: 1.578, 72.889%
Arrival Data Path Delay	cell: 1.159, 33.721%; route: 1.972, 57.376%; tC2Q: 0.306, 8.903%
Required Clock Path Delay	cell: 0.587, 27.111%; route: 1.578, 72.889%

Path6

Path Summary:

Slack	6.314
Data Arrival Time	5.602
Data Required Time	11.916
From	u_la0_top/triger_level_cnt_1_s1
To	u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.165	1.578	tNET	RR	1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/CLK
2.471	0.306	tC2Q	RR	5	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/Q
3.481	1.010	tNET	RR	1	R5C8[2][A]	u_la0_top/triger_level_cnt_3_s5/I0
3.850	0.369	tINS	RR	1	R5C8[2][A]	u_la0_top/triger_level_cnt_3_s5/F
3.852	0.002	tNET	RR	1	R5C8[1][B]	u_la0_top/triger_level_cnt_3_s4/I2
4.221	0.369	tINS	RR	4	R5C8[1][B]	u_la0_top/triger_level_cnt_3_s4/F
4.721	0.500	tNET	RR	1	R3C5[2][B]	u_la0_top/triger_level_cnt_3_s6/I0
5.142	0.421	tINS	RR	3	R3C5[2][B]	u_la0_top/triger_level_cnt_3_s6/F
5.602	0.460	tNET	RR	1	R3C5[2][A]	u_la0_top/triger_level_cnt_3_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.165	1.578	tNET	RR	1	R3C5[2][A]	u_la0_top/triger_level_cnt_3_s1/CLK
11.916	-0.249	tSu		1	R3C5[2][A]	u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.111%; route: 1.578, 72.889%
Arrival Data Path Delay	cell: 1.159, 33.721%; route: 1.972, 57.376%; tC2Q: 0.306, 8.903%
Required Clock Path Delay	cell: 0.587, 27.111%; route: 1.578, 72.889%

Path7

Path Summary:

Slack	6.344
Data Arrival Time	5.763
Data Required Time	12.106
From	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
To	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.152	1.565	tNET	RR	1	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
2.458	0.306	tC2Q	RR	5	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q
3.292	0.834	tNET	RR	1	R4C8[2][A]	u_la0_top/u_ao_mem_ctrl/n132_s1/I1
3.502	0.210	tINS	RR	4	R4C8[2][A]	u_la0_top/u_ao_mem_ctrl/n132_s1/F
4.091	0.589	tNET	RR	1	R6C7[3][B]	u_la0_top/u_ao_mem_ctrl/n129_s2/I3
4.508	0.417	tINS	RR	3	R6C7[3][B]	u_la0_top/u_ao_mem_ctrl/n129_s2/F
4.514	0.006	tNET	RR	1	R6C7[1][A]	u_la0_top/u_ao_mem_ctrl/n127_s2/I2
4.935	0.421	tINS	RR	1	R6C7[1][A]	u_la0_top/u_ao_mem_ctrl/n127_s2/F
5.365	0.430	tNET	RR	1	R3C6[3][A]	u_la0_top/u_ao_mem_ctrl/n127_s3/I0
5.763	0.398	tINS	RR	1	R3C6[3][A]	u_la0_top/u_ao_mem_ctrl/n127_s3/F
5.763	0.000	tNET	RR	1	R3C6[3][A]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.157	1.571	tNET	RR	1	R3C6[3][A]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
12.106	-0.051	tSu		1	R3C6[3][A]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	0.006
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%
Arrival Data Path Delay	cell: 1.446, 40.044%; route: 1.859, 51.482%; tC2Q: 0.306, 8.474%
Required Clock Path Delay	cell: 0.587, 27.206%; route: 1.571, 72.794%

Path8

Path Summary:

Slack	6.389
Data Arrival Time	5.727
Data Required Time	12.116
From	u_la0_top/capture_window_sel_3_s1
To	u_la0_top/start_reg_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.163	1.576	tNET	RR	1	R4C5[1][A]	u_la0_top/capture_window_sel_3_s1/CLK
2.457	0.294	tC2Q	RF	10	R4C5[1][A]	u_la0_top/capture_window_sel_3_s1/Q
3.273	0.816	tNET	FF	2	R2C9[1][B]	u_la0_top/n1076_s27/I1
3.667	0.394	tINS	FR	1	R2C9[1][B]	u_la0_top/n1076_s27/COUT
3.667	0.000	tNET	RR	2	R2C9[2][A]	u_la0_top/n1076_s28/CIN
3.707	0.040	tINS	RR	1	R2C9[2][A]	u_la0_top/n1076_s28/COUT
3.707	0.000	tNET	RR	2	R2C9[2][B]	u_la0_top/n1076_s29/CIN
3.747	0.040	tINS	RR	1	R2C9[2][B]	u_la0_top/n1076_s29/COUT
3.747	0.000	tNET	RR	2	R2C10[0][A]	u_la0_top/n1076_s30/CIN
3.787	0.040	tINS	RR	1	R2C10[0][A]	u_la0_top/n1076_s30/COUT
3.787	0.000	tNET	RR	2	R2C10[0][B]	u_la0_top/n1076_s31/CIN
3.827	0.040	tINS	RR	1	R2C10[0][B]	u_la0_top/n1076_s31/COUT
3.827	0.000	tNET	RR	2	R2C10[1][A]	u_la0_top/n1076_s32/CIN
3.867	0.040	tINS	RR	1	R2C10[1][A]	u_la0_top/n1076_s32/COUT
3.867	0.000	tNET	RR	2	R2C10[1][B]	u_la0_top/n1076_s33/CIN
3.907	0.040	tINS	RR	1	R2C10[1][B]	u_la0_top/n1076_s33/COUT
3.907	0.000	tNET	RR	2	R2C10[2][A]	u_la0_top/n1076_s34/CIN
3.947	0.040	tINS	RR	2	R2C10[2][A]	u_la0_top/n1076_s34/COUT
4.754	0.807	tNET	RR	1	R4C5[3][B]	u_la0_top/start_reg1_s1/I1
5.152	0.398	tINS	RR	1	R4C5[3][B]	u_la0_top/start_reg1_s1/F
5.306	0.154	tNET	RR	1	R2C5[1][B]	u_la0_top/start_reg1_s0/I1
5.727	0.421	tINS	RR	1	R2C5[1][B]	u_la0_top/start_reg1_s0/F
5.727	0.000	tNET	RR	1	R2C5[1][B]	u_la0_top/start_reg_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.167	1.580	tNET	RR	1	R2C5[1][B]	u_la0_top/start_reg_s0/CLK
12.116	-0.051	tSu		1	R2C5[1][B]	u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	0.004
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.587, 27.137%; route: 1.576, 72.863%
Arrival Data Path Delay	cell: 1.493, 41.891%; route: 1.777, 49.860%; tC2Q: 0.294, 8.249%
Required Clock Path Delay	cell: 0.587, 27.086%; route: 1.580, 72.914%

Path9

Path Summary:

Slack	6.569
Data Arrival Time	5.328
Data Required Time	11.897
From	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.152	1.565	tNET	RR	1	R2C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
2.458	0.306	tC2Q	RR	3	R2C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/Q
3.538	1.080	tNET	RR	1	R5C8[3][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s7/I2
3.955	0.417	tINS	RR	1	R5C8[3][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s7/F
3.957	0.002	tNET	RR	1	R5C8[3][B]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/I1
4.289	0.332	tINS	RR	2	R5C8[3][B]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/F
4.417	0.128	tNET	RR	1	R4C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I0
4.838	0.421	tINS	RR	1	R4C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
4.840	0.002	tNET	RR	1	R4C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I2
5.050	0.210	tINS	RR	1	R4C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
5.328	0.278	tNET	RR	1	R5C7[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.146	1.559	tNET	RR	1	R5C7[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
11.897	-0.249	tSu		1	R5C7[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.006
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%
Arrival Data Path Delay	cell: 1.380, 43.451%; route: 1.490, 46.914%; tC2Q: 0.306, 9.635%
Required Clock Path Delay	cell: 0.587, 27.352%; route: 1.559, 72.648%

Path10

Path Summary:

Slack	6.608
Data Arrival Time	5.499
Data Required Time	12.106
From	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
To	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.152	1.565	tNET	RR	1	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
2.458	0.306	tC2Q	RR	5	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q
3.292	0.834	tNET	RR	1	R4C8[2][A]	u_la0_top/u_ao_mem_ctrl/n132_s1/I1
3.502	0.210	tINS	RR	4	R4C8[2][A]	u_la0_top/u_ao_mem_ctrl/n132_s1/F
4.091	0.589	tNET	RR	1	R6C7[3][B]	u_la0_top/u_ao_mem_ctrl/n129_s2/I3
4.508	0.417	tINS	RR	3	R6C7[3][B]	u_la0_top/u_ao_mem_ctrl/n129_s2/F
4.638	0.130	tNET	RR	1	R5C7[0][A]	u_la0_top/u_ao_mem_ctrl/n128_s1/I1
4.848	0.210	tINS	RR	3	R5C7[0][A]	u_la0_top/u_ao_mem_ctrl/n128_s1/F
5.130	0.282	tNET	RR	1	R3C6[2][B]	u_la0_top/u_ao_mem_ctrl/n128_s0/I2
5.499	0.369	tINS	RR	1	R3C6[2][B]	u_la0_top/u_ao_mem_ctrl/n128_s0/F
5.499	0.000	tNET	RR	1	R3C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.157	1.571	tNET	RR	1	R3C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
12.106	-0.051	tSu		1	R3C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	0.006
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%
Arrival Data Path Delay	cell: 1.206, 36.032%; route: 1.835, 54.825%; tC2Q: 0.306, 9.143%
Required Clock Path Delay	cell: 0.587, 27.206%; route: 1.571, 72.794%

Path11

Path Summary:

Slack	6.654
Data Arrival Time	5.454
Data Required Time	12.108
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.155	1.568	tNET	RR	1	R4C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
2.461	0.306	tC2Q	RR	4	R4C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
3.268	0.807	tNET	RR	1	R5C7[2][B]	u_la0_top/u_ao_mem_ctrl/n238_s7/I0
3.689	0.421	tINS	RR	1	R5C7[2][B]	u_la0_top/u_ao_mem_ctrl/n238_s7/F
3.691	0.002	tNET	RR	1	R5C7[3][A]	u_la0_top/u_ao_mem_ctrl/n238_s5/I0
4.089	0.398	tINS	RR	2	R5C7[3][A]	u_la0_top/u_ao_mem_ctrl/n238_s5/F
4.093	0.004	tNET	RR	1	R5C7[3][B]	u_la0_top/u_ao_mem_ctrl/n238_s4/I0
4.399	0.306	tINS	RF	12	R5C7[3][B]	u_la0_top/u_ao_mem_ctrl/n238_s4/F
5.033	0.634	tNET	FF	1	R2C8[2][A]	u_la0_top/u_ao_mem_ctrl/n241_s1/I2
5.454	0.421	tINS	FR	1	R2C8[2][A]	u_la0_top/u_ao_mem_ctrl/n241_s1/F
5.454	0.000	tNET	RR	1	R2C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.159	1.572	tNET	RR	1	R2C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
12.108	-0.051	tSu		1	R2C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	0.004
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.231%; route: 1.568, 72.769%
Arrival Data Path Delay	cell: 1.546, 46.863%; route: 1.447, 43.862%; tC2Q: 0.306, 9.276%
Required Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%

Path12

Path Summary:

Slack	6.663
Data Arrival Time	5.238
Data Required Time	11.901
From	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
To	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.152	1.565	tNET	RR	1	R2C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
2.458	0.306	tC2Q	RR	3	R2C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/Q
3.538	1.080	tNET	RR	1	R5C8[3][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s7/I2
3.955	0.417	tINS	RR	1	R5C8[3][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s7/F
3.957	0.002	tNET	RR	1	R5C8[3][B]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/I1
4.289	0.332	tINS	RR	2	R5C8[3][B]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/F
4.293	0.004	tNET	RR	1	R5C8[0][B]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s9/I0
4.714	0.421	tINS	RR	1	R5C8[0][B]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s9/F
5.238	0.524	tNET	RR	1	R3C7[2][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.150	1.563	tNET	RR	1	R3C7[2][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
11.901	-0.249	tSu		1	R3C7[2][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%
Arrival Data Path Delay	cell: 1.170, 37.913%; route: 1.610, 52.171%; tC2Q: 0.306, 9.916%
Required Clock Path Delay	cell: 0.587, 27.301%; route: 1.563, 72.699%

Path13

Path Summary:

Slack	6.677
Data Arrival Time	5.431
Data Required Time	12.108
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.155	1.568	tNET	RR	1	R4C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
2.461	0.306	tC2Q	RR	4	R4C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
3.268	0.807	tNET	RR	1	R5C7[2][B]	u_la0_top/u_ao_mem_ctrl/n238_s7/I0
3.689	0.421	tINS	RR	1	R5C7[2][B]	u_la0_top/u_ao_mem_ctrl/n238_s7/F
3.691	0.002	tNET	RR	1	R5C7[3][A]	u_la0_top/u_ao_mem_ctrl/n238_s5/I0
4.089	0.398	tINS	RR	2	R5C7[3][A]	u_la0_top/u_ao_mem_ctrl/n238_s5/F
4.093	0.004	tNET	RR	1	R5C7[3][B]	u_la0_top/u_ao_mem_ctrl/n238_s4/I0
4.399	0.306	tINS	RF	12	R5C7[3][B]	u_la0_top/u_ao_mem_ctrl/n238_s4/F
5.033	0.634	tNET	FF	1	R2C8[3][A]	u_la0_top/u_ao_mem_ctrl/n240_s1/I3
5.431	0.398	tINS	FR	1	R2C8[3][A]	u_la0_top/u_ao_mem_ctrl/n240_s1/F
5.431	0.000	tNET	RR	1	R2C8[3][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.159	1.572	tNET	RR	1	R2C8[3][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
12.108	-0.051	tSu		1	R2C8[3][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	0.004
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.231%; route: 1.568, 72.769%
Arrival Data Path Delay	cell: 1.523, 46.490%; route: 1.447, 44.170%; tC2Q: 0.306, 9.341%
Required Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%

Path14

Path Summary:

Slack	6.677
Data Arrival Time	5.431
Data Required Time	12.108
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.155	1.568	tNET	RR	1	R4C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
2.461	0.306	tC2Q	RR	4	R4C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
3.268	0.807	tNET	RR	1	R5C7[2][B]	u_la0_top/u_ao_mem_ctrl/n238_s7/I0
3.689	0.421	tINS	RR	1	R5C7[2][B]	u_la0_top/u_ao_mem_ctrl/n238_s7/F
3.691	0.002	tNET	RR	1	R5C7[3][A]	u_la0_top/u_ao_mem_ctrl/n238_s5/I0
4.089	0.398	tINS	RR	2	R5C7[3][A]	u_la0_top/u_ao_mem_ctrl/n238_s5/F
4.093	0.004	tNET	RR	1	R5C7[3][B]	u_la0_top/u_ao_mem_ctrl/n238_s4/I0
4.399	0.306	tINS	RF	12	R5C7[3][B]	u_la0_top/u_ao_mem_ctrl/n238_s4/F
5.033	0.634	tNET	FF	1	R2C8[3][B]	u_la0_top/u_ao_mem_ctrl/n239_s1/I2
5.431	0.398	tINS	FR	1	R2C8[3][B]	u_la0_top/u_ao_mem_ctrl/n239_s1/F
5.431	0.000	tNET	RR	1	R2C8[3][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.159	1.572	tNET	RR	1	R2C8[3][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
12.108	-0.051	tSu		1	R2C8[3][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew	0.004
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.231%; route: 1.568, 72.769%
Arrival Data Path Delay	cell: 1.523, 46.490%; route: 1.447, 44.170%; tC2Q: 0.306, 9.341%
Required Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%

Path15

Path Summary:

Slack	6.776
Data Arrival Time	5.130
Data Required Time	11.906
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To	u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.155	1.568	tNET	RR	1	R4C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
2.461	0.306	tC2Q	RR	4	R4C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
3.268	0.807	tNET	RR	1	R5C7[2][B]	u_la0_top/u_ao_mem_ctrl/n238_s7/I0
3.689	0.421	tINS	RR	1	R5C7[2][B]	u_la0_top/u_ao_mem_ctrl/n238_s7/F
3.691	0.002	tNET	RR	1	R5C7[3][A]	u_la0_top/u_ao_mem_ctrl/n238_s5/I0
4.089	0.398	tINS	RR	2	R5C7[3][A]	u_la0_top/u_ao_mem_ctrl/n238_s5/F
4.093	0.004	tNET	RR	1	R5C7[3][B]	u_la0_top/u_ao_mem_ctrl/n238_s4/I0
4.425	0.332	tINS	RR	12	R5C7[3][B]	u_la0_top/u_ao_mem_ctrl/n238_s4/F
4.431	0.006	tNET	RR	1	R5C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
4.852	0.421	tINS	RR	1	R5C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
5.130	0.278	tNET	RR	1	R4C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.155	1.568	tNET	RR	1	R4C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
11.906	-0.249	tSu		1	R4C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.231%; route: 1.568, 72.769%
Arrival Data Path Delay	cell: 1.572, 52.840%; route: 1.097, 36.874%; tC2Q: 0.306, 10.286%
Required Clock Path Delay	cell: 0.587, 27.231%; route: 1.568, 72.769%

Path16

Path Summary:

Slack	6.791
Data Arrival Time	5.325
Data Required Time	12.116
From	key_filter_inst/cnt_1_s0
To	key_filter_inst/cnt_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.124	1.538	tNET	RR	1	R18C47[0][A]	key_filter_inst/cnt_1_s0/CLK
2.430	0.306	tC2Q	RR	4	R18C47[0][A]	key_filter_inst/cnt_1_s0/Q
2.684	0.254	tNET	RR	1	R18C45[1][B]	key_filter_inst/n109_s3/I1
3.097	0.413	tINS	RR	8	R18C45[1][B]	key_filter_inst/n109_s3/F
3.649	0.552	tNET	RR	1	R17C46[0][B]	key_filter_inst/n100_s3/I1
4.070	0.421	tINS	RR	11	R17C46[0][B]	key_filter_inst/n100_s3/F
4.365	0.295	tNET	RR	1	R20C46[2][A]	key_filter_inst/n92_s3/I2
4.778	0.413	tINS	RR	1	R20C46[2][A]	key_filter_inst/n92_s3/F
4.904	0.126	tNET	RR	1	R20C45[0][A]	key_filter_inst/n92_s2/I1
5.325	0.421	tINS	RR	1	R20C45[0][A]	key_filter_inst/n92_s2/F
5.325	0.000	tNET	RR	1	R20C45[0][A]	key_filter_inst/cnt_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.167	1.580	tNET	RR	1	R20C45[0][A]	key_filter_inst/cnt_21_s0/CLK
12.116	-0.051	tSu		1	R20C45[0][A]	key_filter_inst/cnt_21_s0

Path Statistics:

Clock Skew	0.043
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.628%; route: 1.538, 72.372%
Arrival Data Path Delay	cell: 1.668, 52.109%; route: 1.227, 38.332%; tC2Q: 0.306, 9.560%
Required Clock Path Delay	cell: 0.587, 27.086%; route: 1.580, 72.914%

Path17

Path Summary:

Slack	6.806
Data Arrival Time	5.315
Data Required Time	12.121
From	key_filter_inst/cnt_1_s0
To	key_filter_inst/cnt_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.124	1.538	tNET	RR	1	R18C47[0][A]	key_filter_inst/cnt_1_s0/CLK
2.430	0.306	tC2Q	RR	4	R18C47[0][A]	key_filter_inst/cnt_1_s0/Q
2.684	0.254	tNET	RR	1	R18C45[1][B]	key_filter_inst/n109_s3/I1
3.097	0.413	tINS	RR	8	R18C45[1][B]	key_filter_inst/n109_s3/F
3.649	0.552	tNET	RR	1	R17C46[0][B]	key_filter_inst/n100_s3/I1
4.070	0.421	tINS	RR	11	R17C46[0][B]	key_filter_inst/n100_s3/F
4.523	0.453	tNET	RR	1	R21C46[2][A]	key_filter_inst/n90_s3/I1
4.944	0.421	tINS	RR	1	R21C46[2][A]	key_filter_inst/n90_s3/F
4.946	0.002	tNET	RR	1	R21C46[2][B]	key_filter_inst/n90_s2/I1
5.315	0.369	tINS	RR	1	R21C46[2][B]	key_filter_inst/n90_s2/F
5.315	0.000	tNET	RR	1	R21C46[2][B]	key_filter_inst/cnt_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.172	1.585	tNET	RR	1	R21C46[2][B]	key_filter_inst/cnt_23_s0/CLK
12.121	-0.051	tSu		1	R21C46[2][B]	key_filter_inst/cnt_23_s0

Path Statistics:

Clock Skew	0.048
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.628%; route: 1.538, 72.372%
Arrival Data Path Delay	cell: 1.624, 50.893%; route: 1.261, 39.517%; tC2Q: 0.306, 9.589%
Required Clock Path Delay	cell: 0.587, 27.018%; route: 1.585, 72.982%

Path18

Path Summary:

Slack	6.809
Data Arrival Time	5.290
Data Required Time	12.099
From	key_filter_inst/cnt_1_s0
To	key_filter_inst/cnt_25_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.124	1.538	tNET	RR	1	R18C47[0][A]	key_filter_inst/cnt_1_s0/CLK
2.430	0.306	tC2Q	RR	4	R18C47[0][A]	key_filter_inst/cnt_1_s0/Q
2.684	0.254	tNET	RR	1	R18C45[1][B]	key_filter_inst/n109_s3/I1
3.097	0.413	tINS	RR	8	R18C45[1][B]	key_filter_inst/n109_s3/F
3.649	0.552	tNET	RR	1	R17C46[0][B]	key_filter_inst/n100_s3/I1
4.070	0.421	tINS	RR	11	R17C46[0][B]	key_filter_inst/n100_s3/F
4.523	0.453	tNET	RR	1	R21C46[3][B]	key_filter_inst/n88_s3/I0
4.921	0.398	tINS	RR	1	R21C46[3][B]	key_filter_inst/n88_s3/F
5.080	0.159	tNET	RR	1	R21C47[2][B]	key_filter_inst/n88_s2/I1
5.290	0.210	tINS	RR	1	R21C47[2][B]	key_filter_inst/n88_s2/F
5.290	0.000	tNET	RR	1	R21C47[2][B]	key_filter_inst/cnt_25_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.150	1.563	tNET	RR	1	R21C47[2][B]	key_filter_inst/cnt_25_s0/CLK
12.099	-0.051	tSu		1	R21C47[2][B]	key_filter_inst/cnt_25_s0

Path Statistics:

Clock Skew	0.025
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.628%; route: 1.538, 72.372%
Arrival Data Path Delay	cell: 1.442, 45.546%; route: 1.418, 44.788%; tC2Q: 0.306, 9.665%
Required Clock Path Delay	cell: 0.587, 27.301%; route: 1.563, 72.699%

Path19

Path Summary:

Slack	6.810
Data Arrival Time	5.297
Data Required Time	12.106
From	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
To	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.152	1.565	tNET	RR	1	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
2.458	0.306	tC2Q	RR	5	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q
3.292	0.834	tNET	RR	1	R4C8[2][A]	u_la0_top/u_ao_mem_ctrl/n132_s1/I1
3.502	0.210	tINS	RR	4	R4C8[2][A]	u_la0_top/u_ao_mem_ctrl/n132_s1/F
4.091	0.589	tNET	RR	1	R6C7[0][B]	u_la0_top/u_ao_mem_ctrl/n131_s1/I1
4.512	0.421	tINS	RR	1	R6C7[0][B]	u_la0_top/u_ao_mem_ctrl/n131_s1/F
4.884	0.372	tNET	RR	1	R3C6[1][A]	u_la0_top/u_ao_mem_ctrl/n131_s2/I0
5.297	0.413	tINS	RR	1	R3C6[1][A]	u_la0_top/u_ao_mem_ctrl/n131_s2/F
5.297	0.000	tNET	RR	1	R3C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.157	1.571	tNET	RR	1	R3C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
12.106	-0.051	tSu		1	R3C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	0.006
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%
Arrival Data Path Delay	cell: 1.044, 33.196%; route: 1.795, 57.075%; tC2Q: 0.306, 9.730%
Required Clock Path Delay	cell: 0.587, 27.206%; route: 1.571, 72.794%

Path20

Path Summary:

Slack	6.854
Data Arrival Time	5.253
Data Required Time	12.106
From	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
To	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.152	1.565	tNET	RR	1	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
2.458	0.306	tC2Q	RR	5	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q
3.292	0.834	tNET	RR	1	R4C8[2][A]	u_la0_top/u_ao_mem_ctrl/n132_s1/I1
3.502	0.210	tINS	RR	4	R4C8[2][A]	u_la0_top/u_ao_mem_ctrl/n132_s1/F
4.091	0.589	tNET	RR	1	R6C7[3][B]	u_la0_top/u_ao_mem_ctrl/n129_s2/I3
4.508	0.417	tINS	RR	3	R6C7[3][B]	u_la0_top/u_ao_mem_ctrl/n129_s2/F
4.884	0.376	tNET	RR	1	R3C6[2][A]	u_la0_top/u_ao_mem_ctrl/n129_s0/I2
5.253	0.369	tINS	RR	1	R3C6[2][A]	u_la0_top/u_ao_mem_ctrl/n129_s0/F
5.253	0.000	tNET	RR	1	R3C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.157	1.571	tNET	RR	1	R3C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
12.106	-0.051	tSu		1	R3C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	0.006
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%
Arrival Data Path Delay	cell: 0.996, 32.119%; route: 1.799, 58.014%; tC2Q: 0.306, 9.868%
Required Clock Path Delay	cell: 0.587, 27.206%; route: 1.571, 72.794%

Path21

Path Summary:

Slack	6.885
Data Arrival Time	5.236
Data Required Time	12.121
From	key_filter_inst/cnt_1_s0
To	key_filter_inst/cnt_19_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.124	1.538	tNET	RR	1	R18C47[0][A]	key_filter_inst/cnt_1_s0/CLK
2.430	0.306	tC2Q	RR	4	R18C47[0][A]	key_filter_inst/cnt_1_s0/Q
2.684	0.254	tNET	RR	1	R18C45[1][B]	key_filter_inst/n109_s3/I1
3.097	0.413	tINS	RR	8	R18C45[1][B]	key_filter_inst/n109_s3/F
3.649	0.552	tNET	RR	1	R17C46[0][B]	key_filter_inst/n100_s3/I1
4.070	0.421	tINS	RR	11	R17C46[0][B]	key_filter_inst/n100_s3/F
4.631	0.561	tNET	RR	1	R21C46[3][A]	key_filter_inst/n94_s3/I1
4.863	0.232	tINS	RF	1	R21C46[3][A]	key_filter_inst/n94_s3/F
4.867	0.004	tNET	FF	1	R21C46[1][B]	key_filter_inst/n94_s2/I0
5.236	0.369	tINS	FR	1	R21C46[1][B]	key_filter_inst/n94_s2/F
5.236	0.000	tNET	RR	1	R21C46[1][B]	key_filter_inst/cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.172	1.585	tNET	RR	1	R21C46[1][B]	key_filter_inst/cnt_19_s0/CLK
12.121	-0.051	tSu		1	R21C46[1][B]	key_filter_inst/cnt_19_s0

Path Statistics:

Clock Skew	0.048
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.628%; route: 1.538, 72.372%
Arrival Data Path Delay	cell: 1.435, 46.112%; route: 1.371, 44.055%; tC2Q: 0.306, 9.833%
Required Clock Path Delay	cell: 0.587, 27.018%; route: 1.585, 72.982%

Path22

Path Summary:

Slack	6.888
Data Arrival Time	5.228
Data Required Time	12.116
From	u_la0_top/triger_level_cnt_1_s1
To	u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.165	1.578	tNET	RR	1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/CLK
2.471	0.306	tC2Q	RR	5	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/Q
3.481	1.010	tNET	RR	1	R5C8[2][A]	u_la0_top/triger_level_cnt_3_s5/I0
3.850	0.369	tINS	RR	1	R5C8[2][A]	u_la0_top/triger_level_cnt_3_s5/F
3.852	0.002	tNET	RR	1	R5C8[1][B]	u_la0_top/triger_level_cnt_3_s4/I2
4.221	0.369	tINS	RR	4	R5C8[1][B]	u_la0_top/triger_level_cnt_3_s4/F
4.807	0.586	tNET	RR	1	R2C5[0][B]	u_la0_top/n1127_s3/I2
5.228	0.421	tINS	RR	1	R2C5[0][B]	u_la0_top/n1127_s3/F
5.228	0.000	tNET	RR	1	R2C5[0][B]	u_la0_top/triger_level_cnt_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.167	1.580	tNET	RR	1	R2C5[0][B]	u_la0_top/triger_level_cnt_0_s3/CLK
12.116	-0.051	tSu		1	R2C5[0][B]	u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	0.002
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.111%; route: 1.578, 72.889%
Arrival Data Path Delay	cell: 1.159, 37.839%; route: 1.598, 52.171%; tC2Q: 0.306, 9.990%
Required Clock Path Delay	cell: 0.587, 27.086%; route: 1.580, 72.914%

Path23

Path Summary:

Slack	6.888
Data Arrival Time	5.228
Data Required Time	12.116
From	u_la0_top/triger_level_cnt_1_s1
To	u_la0_top/triger_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.165	1.578	tNET	RR	1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/CLK
2.471	0.306	tC2Q	RR	5	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/Q
3.481	1.010	tNET	RR	1	R5C8[2][A]	u_la0_top/triger_level_cnt_3_s5/I0
3.850	0.369	tINS	RR	1	R5C8[2][A]	u_la0_top/triger_level_cnt_3_s5/F
3.852	0.002	tNET	RR	1	R5C8[1][B]	u_la0_top/triger_level_cnt_3_s4/I2
4.221	0.369	tINS	RR	4	R5C8[1][B]	u_la0_top/triger_level_cnt_3_s4/F
4.807	0.586	tNET	RR	1	R2C5[1][A]	u_la0_top/n1147_s2/I2
5.228	0.421	tINS	RR	1	R2C5[1][A]	u_la0_top/n1147_s2/F
5.228	0.000	tNET	RR	1	R2C5[1][A]	u_la0_top/triger_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.167	1.580	tNET	RR	1	R2C5[1][A]	u_la0_top/triger_s0/CLK
12.116	-0.051	tSu		1	R2C5[1][A]	u_la0_top/triger_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.111%; route: 1.578, 72.889%
Arrival Data Path Delay	cell: 1.159, 37.839%; route: 1.598, 52.171%; tC2Q: 0.306, 9.990%
Required Clock Path Delay	cell: 0.587, 27.086%; route: 1.580, 72.914%

Path24

Path Summary:

Slack	6.928
Data Arrival Time	5.195
Data Required Time	12.123
From	key_filter_inst/cnt_1_s0
To	key_filter_inst/cnt_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.124	1.538	tNET	RR	1	R18C47[0][A]	key_filter_inst/cnt_1_s0/CLK
2.430	0.306	tC2Q	RR	4	R18C47[0][A]	key_filter_inst/cnt_1_s0/Q
2.684	0.254	tNET	RR	1	R18C45[1][B]	key_filter_inst/n109_s3/I1
3.097	0.413	tINS	RR	8	R18C45[1][B]	key_filter_inst/n109_s3/F
3.649	0.552	tNET	RR	1	R17C46[0][B]	key_filter_inst/n100_s3/I1
4.070	0.421	tINS	RR	11	R17C46[0][B]	key_filter_inst/n100_s3/F
4.367	0.297	tNET	RR	1	R20C46[0][B]	key_filter_inst/n93_s3/I1
4.780	0.413	tINS	RR	1	R20C46[0][B]	key_filter_inst/n93_s3/F
4.782	0.002	tNET	RR	1	R20C46[1][B]	key_filter_inst/n93_s2/I0
5.195	0.413	tINS	RR	1	R20C46[1][B]	key_filter_inst/n93_s2/F
5.195	0.000	tNET	RR	1	R20C46[1][B]	key_filter_inst/cnt_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.174	1.587	tNET	RR	1	R20C46[1][B]	key_filter_inst/cnt_20_s0/CLK
12.123	-0.051	tSu		1	R20C46[1][B]	key_filter_inst/cnt_20_s0

Path Statistics:

Clock Skew	0.050
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.628%; route: 1.538, 72.372%
Arrival Data Path Delay	cell: 1.660, 54.054%; route: 1.105, 35.982%; tC2Q: 0.306, 9.964%
Required Clock Path Delay	cell: 0.587, 26.993%; route: 1.587, 73.007%

Path25

Path Summary:

Slack	6.931
Data Arrival Time	5.170
Data Required Time	12.101
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
2.155	1.568	tNET	RR	1	R4C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
2.461	0.306	tC2Q	RR	4	R4C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
3.268	0.807	tNET	RR	1	R5C7[2][B]	u_la0_top/u_ao_mem_ctrl/n238_s7/I0
3.689	0.421	tINS	RR	1	R5C7[2][B]	u_la0_top/u_ao_mem_ctrl/n238_s7/F
3.691	0.002	tNET	RR	1	R5C7[3][A]	u_la0_top/u_ao_mem_ctrl/n238_s5/I0
4.089	0.398	tINS	RR	2	R5C7[3][A]	u_la0_top/u_ao_mem_ctrl/n238_s5/F
4.093	0.004	tNET	RR	1	R5C7[3][B]	u_la0_top/u_ao_mem_ctrl/n238_s4/I0
4.425	0.332	tINS	RR	12	R5C7[3][B]	u_la0_top/u_ao_mem_ctrl/n238_s4/F
4.801	0.376	tNET	RR	1	R2C7[0][A]	u_la0_top/u_ao_mem_ctrl/n238_s2/I2
5.170	0.369	tINS	RR	1	R2C7[0][A]	u_la0_top/u_ao_mem_ctrl/n238_s2/F
5.170	0.000	tNET	RR	1	R2C7[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.152	1.565	tNET	RR	1	R2C7[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLK
12.101	-0.051	tSu		1	R2C7[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1

Path Statistics:

Clock Skew	-0.003
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.231%; route: 1.568, 72.769%
Arrival Data Path Delay	cell: 1.520, 50.415%; route: 1.189, 39.436%; tC2Q: 0.306, 10.149%
Required Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.227
Data Arrival Time	1.538
Data Required Time	1.311
From	u_la0_top/u_ao_match_0/trig_dly_in_0_s0
To	u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.538	0.957	tNET	RR	1	R3C7[1][B]	u_la0_top/u_ao_match_0/trig_dly_in_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.298	0.717	tNET	RR	1	R3C7[1][B]	u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
1.311	0.013	tHld		1	R3C7[1][B]	u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	0.717
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.957, 100.000%
Required Clock Path Delay	cell: 0.581, 44.758%; route: 0.717, 55.242%

Path2

Path Summary:

Slack	0.254
Data Arrival Time	2.509
Data Required Time	2.255
From	u_la0_top/address_counter_10_s0
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.225	1.063	tNET	RR	1		u_la0_top/address_counter_10_s0/CLK
2.369	0.144	tC2Q	RR	3		u_la0_top/address_counter_10_s0/Q
2.509	0.140	tNET	RR	1		u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADB[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.220	1.058	tNET	RR	1		u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKB
2.255	0.035	tHld		1		u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 52.222%; route: 1.063, 47.778%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.140, 49.296%; tC2Q: 0.144, 50.704%
Required Clock Path Delay	cell: 1.162, 52.339%; route: 1.058, 47.661%

Path3

Path Summary:

Slack	0.271
Data Arrival Time	1.592
Data Required Time	1.321
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R4C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.441	0.141	tC2Q	RF	4	R4C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q
1.592	0.151	tNET	FF	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.284	0.703	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.321	0.037	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.016
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.151, 51.712%; tC2Q: 0.141, 48.288%
Required Clock Path Delay	cell: 0.581, 45.246%; route: 0.703, 54.754%

Path4

Path Summary:

Slack	0.275
Data Arrival Time	27.569
Data Required Time	27.294
From	u_la0_top/capture_end_tck_1_s0
To	u_la0_top/capture_end_tck_2_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	tck_pad_i:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1		tck_ibuf/I
25.583	0.583	tINS	FF	1		tck_ibuf/O
25.583	0.000	tNET	FF	1		u_gw_jtag/tck_pad_i
26.165	0.583	tINS	FF	211		u_gw_jtag/tck_o
27.330	1.164	tNET	FF	1		u_la0_top/capture_end_tck_1_s0/CLK
27.488	0.158	tC2Q	FR	2		u_la0_top/capture_end_tck_1_s0/Q
27.569	0.081	tNET	RR	1		u_la0_top/capture_end_tck_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1		tck_ibuf/I
25.583	0.583	tINS	FF	1		tck_ibuf/O
25.583	0.000	tNET	FF	1		u_gw_jtag/tck_pad_i
26.165	0.583	tINS	FF	211		u_gw_jtag/tck_o
27.330	1.164	tNET	FF	1		u_la0_top/capture_end_tck_2_s0/CLK
27.294	-0.036	tHld		1		u_la0_top/capture_end_tck_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.165, 50.017%; route: 1.164, 49.983%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.081, 33.891%; tC2Q: 0.158, 66.109%
Required Clock Path Delay	cell: 1.165, 50.017%; route: 1.164, 49.983%

Path5

Path Summary:

Slack	0.275
Data Arrival Time	27.588
Data Required Time	27.313
From	u_icon_top/enable_reg_1_s0
To	u_icon_top/enable_reg_0_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	tck_pad_i:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1		tck_ibuf/I
25.583	0.583	tINS	FF	1		tck_ibuf/O
25.583	0.000	tNET	FF	1		u_gw_jtag/tck_pad_i
26.165	0.583	tINS	FF	211		u_gw_jtag/tck_o
27.349	1.184	tNET	FF	1		u_icon_top/enable_reg_1_s0/CLK
27.507	0.158	tC2Q	FR	3		u_icon_top/enable_reg_1_s0/Q
27.588	0.081	tNET	RR	1		u_icon_top/enable_reg_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1		tck_ibuf/I
25.583	0.583	tINS	FF	1		tck_ibuf/O
25.583	0.000	tNET	FF	1		u_gw_jtag/tck_pad_i
26.165	0.583	tINS	FF	211		u_gw_jtag/tck_o
27.349	1.184	tNET	FF	1		u_icon_top/enable_reg_0_s0/CLK
27.313	-0.036	tHld		1		u_icon_top/enable_reg_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.165, 49.602%; route: 1.184, 50.398%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.081, 33.891%; tC2Q: 0.158, 66.109%
Required Clock Path Delay	cell: 1.165, 49.602%; route: 1.184, 50.398%

Path6

Path Summary:

Slack	0.275
Data Arrival Time	27.588
Data Required Time	27.313
From	u_icon_top/enable_reg_2_s0
To	u_icon_top/enable_reg_1_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	tck_pad_i:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1		tck_ibuf/I
25.583	0.583	tINS	FF	1		tck_ibuf/O
25.583	0.000	tNET	FF	1		u_gw_jtag/tck_pad_i
26.165	0.583	tINS	FF	211		u_gw_jtag/tck_o
27.349	1.184	tNET	FF	1		u_icon_top/enable_reg_2_s0/CLK
27.507	0.158	tC2Q	FR	3		u_icon_top/enable_reg_2_s0/Q
27.588	0.081	tNET	RR	1		u_icon_top/enable_reg_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1		tck_ibuf/I
25.583	0.583	tINS	FF	1		tck_ibuf/O
25.583	0.000	tNET	FF	1		u_gw_jtag/tck_pad_i
26.165	0.583	tINS	FF	211		u_gw_jtag/tck_o
27.349	1.184	tNET	FF	1		u_icon_top/enable_reg_1_s0/CLK
27.313	-0.036	tHld		1		u_icon_top/enable_reg_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.165, 49.602%; route: 1.184, 50.398%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.081, 33.891%; tC2Q: 0.158, 66.109%
Required Clock Path Delay	cell: 1.165, 49.602%; route: 1.184, 50.398%

Path7

Path Summary:

Slack	0.275
Data Arrival Time	1.520
Data Required Time	1.245
From	u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0
To	u_la0_top/u_ao_mem_ctrl/data_reg_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.298	0.718	tNET	RR	1	R5C6[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0/CLK
1.442	0.144	tC2Q	RR	1	R5C6[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0/Q
1.520	0.078	tNET	RR	1	R5C6[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.298	0.718	tNET	RR	1	R5C6[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/CLK
1.245	-0.053	tHld		1	R5C6[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.741%; route: 0.718, 55.259%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.581, 44.741%; route: 0.718, 55.259%

Path8

Path Summary:

Slack	0.275
Data Arrival Time	1.578
Data Required Time	1.303
From	key_filter_inst/cnt_1_s0
To	key_filter_inst/cnt_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.278	0.697	tNET	RR	1	R18C47[0][A]	key_filter_inst/cnt_1_s0/CLK
1.419	0.141	tC2Q	RF	4	R18C47[0][A]	key_filter_inst/cnt_1_s0/Q
1.425	0.006	tNET	FF	1	R18C47[0][A]	key_filter_inst/n112_s2/I1
1.578	0.153	tINS	FF	1	R18C47[0][A]	key_filter_inst/n112_s2/F
1.578	0.000	tNET	FF	1	R18C47[0][A]	key_filter_inst/cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.278	0.697	tNET	RR	1	R18C47[0][A]	key_filter_inst/cnt_1_s0/CLK
1.303	0.025	tHld		1	R18C47[0][A]	key_filter_inst/cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 45.468%; route: 0.697, 54.532%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.581, 45.468%; route: 0.697, 54.532%

Path9

Path Summary:

Slack	0.275
Data Arrival Time	1.589
Data Required Time	1.314
From	key_filter_inst/cnt_7_s0
To	key_filter_inst/cnt_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.289	0.708	tNET	RR	1	R18C46[0][A]	key_filter_inst/cnt_7_s0/CLK
1.430	0.141	tC2Q	RF	3	R18C46[0][A]	key_filter_inst/cnt_7_s0/Q
1.436	0.006	tNET	FF	1	R18C46[0][A]	key_filter_inst/n106_s2/I2
1.589	0.153	tINS	FF	1	R18C46[0][A]	key_filter_inst/n106_s2/F
1.589	0.000	tNET	FF	1	R18C46[0][A]	key_filter_inst/cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.289	0.708	tNET	RR	1	R18C46[0][A]	key_filter_inst/cnt_7_s0/CLK
1.314	0.025	tHld		1	R18C46[0][A]	key_filter_inst/cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 45.062%; route: 0.708, 54.938%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.581, 45.062%; route: 0.708, 54.938%

Path10

Path Summary:

Slack	0.275
Data Arrival Time	1.608
Data Required Time	1.333
From	key_filter_inst/cnt_21_s0
To	key_filter_inst/cnt_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.308	0.727	tNET	RR	1	R20C45[0][A]	key_filter_inst/cnt_21_s0/CLK
1.449	0.141	tC2Q	RF	3	R20C45[0][A]	key_filter_inst/cnt_21_s0/Q
1.455	0.006	tNET	FF	1	R20C45[0][A]	key_filter_inst/n92_s2/I0
1.608	0.153	tINS	FF	1	R20C45[0][A]	key_filter_inst/n92_s2/F
1.608	0.000	tNET	FF	1	R20C45[0][A]	key_filter_inst/cnt_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.308	0.727	tNET	RR	1	R20C45[0][A]	key_filter_inst/cnt_21_s0/CLK
1.333	0.025	tHld		1	R20C45[0][A]	key_filter_inst/cnt_21_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 44.424%; route: 0.727, 55.576%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.581, 44.424%; route: 0.727, 55.576%

Path11

Path Summary:

Slack	0.275
Data Arrival Time	1.580
Data Required Time	1.305
From	led_s3
To	led_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.280	0.700	tNET	RR	1	R17C48[0][A]	led_s3/CLK
1.421	0.141	tC2Q	RF	2	R17C48[0][A]	led_s3/Q
1.427	0.006	tNET	FF	1	R17C48[0][A]	n47_s2/I0
1.580	0.153	tINS	FF	1	R17C48[0][A]	n47_s2/F
1.580	0.000	tNET	FF	1	R17C48[0][A]	led_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.280	0.700	tNET	RR	1	R17C48[0][A]	led_s3/CLK
1.305	0.025	tHld		1	R17C48[0][A]	led_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.581, 45.370%; route: 0.700, 54.630%

Path12

Path Summary:

Slack	0.278
Data Arrival Time	1.603
Data Required Time	1.325
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R4C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.441	0.141	tC2Q	RF	6	R4C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
1.450	0.009	tNET	FF	1	R4C6[0][A]	u_la0_top/u_ao_mem_ctrl/n248_s1/I1
1.603	0.153	tINS	FF	1	R4C6[0][A]	u_la0_top/u_ao_mem_ctrl/n248_s1/F
1.603	0.000	tNET	FF	1	R4C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R4C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.325	0.025	tHld		1	R4C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%

Path13

Path Summary:

Slack	0.278
Data Arrival Time	1.601
Data Required Time	1.323
From	key_filter_inst/state_0_s0
To	key_filter_inst/state_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.298	0.717	tNET	RR	1	R21C47[0][A]	key_filter_inst/state_0_s0/CLK
1.439	0.141	tC2Q	RF	7	R21C47[0][A]	key_filter_inst/state_0_s0/Q
1.448	0.009	tNET	FF	1	R21C47[0][A]	key_filter_inst/n166_s3/I1
1.601	0.153	tINS	FF	1	R21C47[0][A]	key_filter_inst/n166_s3/F
1.601	0.000	tNET	FF	1	R21C47[0][A]	key_filter_inst/state_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.298	0.717	tNET	RR	1	R21C47[0][A]	key_filter_inst/state_0_s0/CLK
1.323	0.025	tHld		1	R21C47[0][A]	key_filter_inst/state_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 44.758%; route: 0.717, 55.242%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.581, 44.758%; route: 0.717, 55.242%

Path14

Path Summary:

Slack	0.278
Data Arrival Time	1.592
Data Required Time	1.314
From	key_filter_inst/cnt_16_s0
To	key_filter_inst/cnt_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.289	0.708	tNET	RR	1	R18C46[1][A]	key_filter_inst/cnt_16_s0/CLK
1.430	0.141	tC2Q	RF	4	R18C46[1][A]	key_filter_inst/cnt_16_s0/Q
1.439	0.009	tNET	FF	1	R18C46[1][A]	key_filter_inst/n97_s2/I0
1.592	0.153	tINS	FF	1	R18C46[1][A]	key_filter_inst/n97_s2/F
1.592	0.000	tNET	FF	1	R18C46[1][A]	key_filter_inst/cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.289	0.708	tNET	RR	1	R18C46[1][A]	key_filter_inst/cnt_16_s0/CLK
1.314	0.025	tHld		1	R18C46[1][A]	key_filter_inst/cnt_16_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 45.062%; route: 0.708, 54.938%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.581, 45.062%; route: 0.708, 54.938%

Path15

Path Summary:

Slack	0.278
Data Arrival Time	1.603
Data Required Time	1.325
From	key_filter_inst/cnt_24_s0
To	key_filter_inst/cnt_24_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R20C47[1][A]	key_filter_inst/cnt_24_s0/CLK
1.441	0.141	tC2Q	RF	3	R20C47[1][A]	key_filter_inst/cnt_24_s0/Q
1.450	0.009	tNET	FF	1	R20C47[1][A]	key_filter_inst/n89_s2/I2
1.603	0.153	tINS	FF	1	R20C47[1][A]	key_filter_inst/n89_s2/F
1.603	0.000	tNET	FF	1	R20C47[1][A]	key_filter_inst/cnt_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R20C47[1][A]	key_filter_inst/cnt_24_s0/CLK
1.325	0.025	tHld		1	R20C47[1][A]	key_filter_inst/cnt_24_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 44.698%; route: 0.719, 55.302%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.581, 44.698%; route: 0.719, 55.302%

Path16

Path Summary:

Slack	0.278
Data Arrival Time	2.467
Data Required Time	2.189
From	u_icon_top/input_shift_reg_1_s0
To	u_icon_top/input_shift_reg_0_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.242	1.080	tNET	RR	1		u_icon_top/input_shift_reg_1_s0/CLK
2.386	0.144	tC2Q	RR	2		u_icon_top/input_shift_reg_1_s0/Q
2.467	0.081	tNET	RR	1		u_icon_top/input_shift_reg_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.242	1.080	tNET	RR	1		u_icon_top/input_shift_reg_0_s0/CLK
2.189	-0.053	tHld		1		u_icon_top/input_shift_reg_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 51.826%; route: 1.080, 48.174%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.081, 36.000%; tC2Q: 0.144, 64.000%
Required Clock Path Delay	cell: 1.162, 51.826%; route: 1.080, 48.174%

Path17

Path Summary:

Slack	0.278
Data Arrival Time	2.467
Data Required Time	2.189
From	u_icon_top/input_shift_reg_2_s0
To	u_icon_top/input_shift_reg_1_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.242	1.080	tNET	RR	1		u_icon_top/input_shift_reg_2_s0/CLK
2.386	0.144	tC2Q	RR	2		u_icon_top/input_shift_reg_2_s0/Q
2.467	0.081	tNET	RR	1		u_icon_top/input_shift_reg_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.242	1.080	tNET	RR	1		u_icon_top/input_shift_reg_1_s0/CLK
2.189	-0.053	tHld		1		u_icon_top/input_shift_reg_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 51.826%; route: 1.080, 48.174%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.081, 36.000%; tC2Q: 0.144, 64.000%
Required Clock Path Delay	cell: 1.162, 51.826%; route: 1.080, 48.174%

Path18

Path Summary:

Slack	0.278
Data Arrival Time	2.469
Data Required Time	2.191
From	u_icon_top/input_shift_reg_4_s0
To	u_icon_top/input_shift_reg_3_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.244	1.082	tNET	RR	1		u_icon_top/input_shift_reg_4_s0/CLK
2.388	0.144	tC2Q	RR	2		u_icon_top/input_shift_reg_4_s0/Q
2.469	0.081	tNET	RR	1		u_icon_top/input_shift_reg_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.244	1.082	tNET	RR	1		u_icon_top/input_shift_reg_3_s0/CLK
2.191	-0.053	tHld		1		u_icon_top/input_shift_reg_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 51.785%; route: 1.082, 48.215%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.081, 36.000%; tC2Q: 0.144, 64.000%
Required Clock Path Delay	cell: 1.162, 51.785%; route: 1.082, 48.215%

Path19

Path Summary:

Slack	0.278
Data Arrival Time	2.467
Data Required Time	2.189
From	u_icon_top/input_shift_reg_2_s0
To	u_icon_top/module_id_reg_2_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.242	1.080	tNET	RR	1		u_icon_top/input_shift_reg_2_s0/CLK
2.386	0.144	tC2Q	RR	2		u_icon_top/input_shift_reg_2_s0/Q
2.467	0.081	tNET	RR	1		u_icon_top/module_id_reg_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.242	1.080	tNET	RR	1		u_icon_top/module_id_reg_2_s0/CLK
2.189	-0.053	tHld		1		u_icon_top/module_id_reg_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 51.826%; route: 1.080, 48.174%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.081, 36.000%; tC2Q: 0.144, 64.000%
Required Clock Path Delay	cell: 1.162, 51.826%; route: 1.080, 48.174%

Path20

Path Summary:

Slack	0.281
Data Arrival Time	1.536
Data Required Time	1.255
From	u_la0_top/internal_reg_start_dly_0_s0
To	u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.308	0.727	tNET	RR	1	R2C5[2][A]	u_la0_top/internal_reg_start_dly_0_s0/CLK
1.452	0.144	tC2Q	RR	3	R2C5[2][A]	u_la0_top/internal_reg_start_dly_0_s0/Q
1.536	0.084	tNET	RR	1	R2C5[3][A]	u_la0_top/internal_reg_start_dly_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.308	0.727	tNET	RR	1	R2C5[3][A]	u_la0_top/internal_reg_start_dly_1_s0/CLK
1.255	-0.053	tHld		1	R2C5[3][A]	u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.424%; route: 0.727, 55.576%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.084, 36.842%; tC2Q: 0.144, 63.158%
Required Clock Path Delay	cell: 0.581, 44.424%; route: 0.727, 55.576%

Path21

Path Summary:

Slack	0.281
Data Arrival Time	1.612
Data Required Time	1.331
From	u_la0_top/triger_level_cnt_1_s1
To	u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.306	0.725	tNET	RR	1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/CLK
1.447	0.141	tC2Q	RF	5	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/Q
1.459	0.012	tNET	FF	1	R3C5[1][A]	u_la0_top/n1126_s3/I1
1.612	0.153	tINS	FF	1	R3C5[1][A]	u_la0_top/n1126_s3/F
1.612	0.000	tNET	FF	1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.306	0.725	tNET	RR	1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/CLK
1.331	0.025	tHld		1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 44.484%; route: 0.725, 55.516%
Arrival Data Path Delay	cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078%
Required Clock Path Delay	cell: 0.581, 44.484%; route: 0.725, 55.516%

Path22

Path Summary:

Slack	0.281
Data Arrival Time	2.541
Data Required Time	2.260
From	u_la0_top/word_count_14_s0
To	u_la0_top/word_count_14_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.235	1.073	tNET	RR	1		u_la0_top/word_count_14_s0/CLK
2.376	0.141	tC2Q	RF	5		u_la0_top/word_count_14_s0/Q
2.388	0.012	tNET	FF	1		u_la0_top/data_to_word_counter_14_s0/I1
2.541	0.153	tINS	FF	1		u_la0_top/data_to_word_counter_14_s0/F
2.541	0.000	tNET	FF	1		u_la0_top/word_count_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.235	1.073	tNET	RR	1		u_la0_top/word_count_14_s0/CLK
2.260	0.025	tHld		1		u_la0_top/word_count_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.162, 51.988%; route: 1.073, 48.012%
Arrival Data Path Delay	cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078%
Required Clock Path Delay	cell: 1.162, 51.988%; route: 1.073, 48.012%

Path23

Path Summary:

Slack	0.281
Data Arrival Time	2.470
Data Required Time	2.189
From	u_la0_top/data_register_17_s0
To	u_la0_top/internal_register_select_1_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.242	1.081	tNET	RR	1		u_la0_top/data_register_17_s0/CLK
2.386	0.144	tC2Q	RR	7		u_la0_top/data_register_17_s0/Q
2.470	0.084	tNET	RR	1		u_la0_top/internal_register_select_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.242	1.081	tNET	RR	1		u_la0_top/internal_register_select_1_s0/CLK
2.189	-0.053	tHld		1		u_la0_top/internal_register_select_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 51.814%; route: 1.081, 48.186%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.084, 36.842%; tC2Q: 0.144, 63.158%
Required Clock Path Delay	cell: 1.162, 51.814%; route: 1.081, 48.186%

Path24

Path Summary:

Slack	0.281
Data Arrival Time	2.469
Data Required Time	2.188
From	u_la0_top/data_register_15_s0
To	u_la0_top/data_register_14_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.241	1.079	tNET	RR	1		u_la0_top/data_register_15_s0/CLK
2.385	0.144	tC2Q	RR	4		u_la0_top/data_register_15_s0/Q
2.469	0.084	tNET	RR	1		u_la0_top/data_register_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.241	1.079	tNET	RR	1		u_la0_top/data_register_14_s0/CLK
2.188	-0.053	tHld		1		u_la0_top/data_register_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 51.855%; route: 1.079, 48.145%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.084, 36.842%; tC2Q: 0.144, 63.158%
Required Clock Path Delay	cell: 1.162, 51.855%; route: 1.079, 48.145%

Path25

Path Summary:

Slack	0.281
Data Arrival Time	2.470
Data Required Time	2.189
From	u_la0_top/data_register_17_s0
To	u_la0_top/data_register_16_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.242	1.081	tNET	RR	1		u_la0_top/data_register_17_s0/CLK
2.386	0.144	tC2Q	RR	7		u_la0_top/data_register_17_s0/Q
2.470	0.084	tNET	RR	1		u_la0_top/data_register_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
0.581	0.581	tINS	RR	1		tck_ibuf/O
0.581	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	211		u_gw_jtag/tck_o
2.242	1.081	tNET	RR	1		u_la0_top/data_register_16_s0/CLK
2.189	-0.053	tHld		1		u_la0_top/data_register_16_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 51.814%; route: 1.081, 48.186%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.084, 36.842%; tC2Q: 0.144, 63.158%
Required Clock Path Delay	cell: 1.162, 51.814%; route: 1.081, 48.186%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.696
Data Arrival Time	10.178
Data Required Time	11.874
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.178	2.660	tNET	FF	1	R2C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.152	1.565	tNET	RR	1	R2C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
11.874	-0.278	tSu		1	R2C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.012
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.660, 88.255%; tC2Q: 0.354, 11.745%
Required Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%

Path2

Path Summary:

Slack	1.696
Data Arrival Time	10.178
Data Required Time	11.874
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.178	2.660	tNET	FF	1	R2C7[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.152	1.565	tNET	RR	1	R2C7[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLK
11.874	-0.278	tSu		1	R2C7[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1

Path Statistics:

Clock Skew	-0.012
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.660, 88.255%; tC2Q: 0.354, 11.745%
Required Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%

Path3

Path Summary:

Slack	1.696
Data Arrival Time	10.178
Data Required Time	11.874
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.178	2.660	tNET	FF	1	R2C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.152	1.565	tNET	RR	1	R2C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
11.874	-0.278	tSu		1	R2C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	-0.012
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.660, 88.255%; tC2Q: 0.354, 11.745%
Required Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%

Path4

Path Summary:

Slack	1.696
Data Arrival Time	10.178
Data Required Time	11.874
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.178	2.660	tNET	FF	1	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.152	1.565	tNET	RR	1	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
11.874	-0.278	tSu		1	R2C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.012
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.660, 88.255%; tC2Q: 0.354, 11.745%
Required Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%

Path5

Path Summary:

Slack	1.696
Data Arrival Time	10.178
Data Required Time	11.874
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.178	2.660	tNET	FF	1	R2C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.152	1.565	tNET	RR	1	R2C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
11.874	-0.278	tSu		1	R2C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_10_s1

Path Statistics:

Clock Skew	-0.012
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.660, 88.255%; tC2Q: 0.354, 11.745%
Required Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%

Path6

Path Summary:

Slack	1.696
Data Arrival Time	10.178
Data Required Time	11.874
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_11_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.178	2.660	tNET	FF	1	R2C7[3][A]	u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.152	1.565	tNET	RR	1	R2C7[3][A]	u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLK
11.874	-0.278	tSu		1	R2C7[3][A]	u_la0_top/u_ao_mem_ctrl/capture_length_11_s1

Path Statistics:

Clock Skew	-0.012
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.660, 88.255%; tC2Q: 0.354, 11.745%
Required Clock Path Delay	cell: 0.587, 27.275%; route: 1.565, 72.725%

Path7

Path Summary:

Slack	1.703
Data Arrival Time	10.178
Data Required Time	11.881
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.178	2.660	tNET	FF	1	R2C6[0][B]	u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.159	1.572	tNET	RR	1	R2C6[0][B]	u_la0_top/internal_reg_start_syn_0_s0/CLK
11.881	-0.278	tSu		1	R2C6[0][B]	u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-0.005
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.660, 88.255%; tC2Q: 0.354, 11.745%
Required Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%

Path8

Path Summary:

Slack	1.703
Data Arrival Time	10.178
Data Required Time	11.881
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.178	2.660	tNET	FF	1	R2C6[0][A]	u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.159	1.572	tNET	RR	1	R2C6[0][A]	u_la0_top/internal_reg_start_syn_1_s0/CLK
11.881	-0.278	tSu		1	R2C6[0][A]	u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	-0.005
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.660, 88.255%; tC2Q: 0.354, 11.745%
Required Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%

Path9

Path Summary:

Slack	1.703
Data Arrival Time	10.178
Data Required Time	11.881
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.178	2.660	tNET	FF	1	R2C6[1][B]	u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.159	1.572	tNET	RR	1	R2C6[1][B]	u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
11.881	-0.278	tSu		1	R2C6[1][B]	u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-0.005
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.660, 88.255%; tC2Q: 0.354, 11.745%
Required Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%

Path10

Path Summary:

Slack	1.703
Data Arrival Time	10.178
Data Required Time	11.881
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.178	2.660	tNET	FF	1	R2C6[1][A]	u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.159	1.572	tNET	RR	1	R2C6[1][A]	u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
11.881	-0.278	tSu		1	R2C6[1][A]	u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	-0.005
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.660, 88.255%; tC2Q: 0.354, 11.745%
Required Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%

Path11

Path Summary:

Slack	1.718
Data Arrival Time	10.161
Data Required Time	11.879
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.161	2.643	tNET	FF	1	R3C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.157	1.571	tNET	RR	1	R3C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
11.879	-0.278	tSu		1	R3C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.643, 88.189%; tC2Q: 0.354, 11.811%
Required Clock Path Delay	cell: 0.587, 27.206%; route: 1.571, 72.794%

Path12

Path Summary:

Slack	1.718
Data Arrival Time	10.161
Data Required Time	11.879
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.161	2.643	tNET	FF	1	R3C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.157	1.571	tNET	RR	1	R3C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
11.879	-0.278	tSu		1	R3C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.643, 88.189%; tC2Q: 0.354, 11.811%
Required Clock Path Delay	cell: 0.587, 27.206%; route: 1.571, 72.794%

Path13

Path Summary:

Slack	1.718
Data Arrival Time	10.161
Data Required Time	11.879
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.161	2.643	tNET	FF	1	R3C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.157	1.571	tNET	RR	1	R3C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
11.879	-0.278	tSu		1	R3C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.643, 88.189%; tC2Q: 0.354, 11.811%
Required Clock Path Delay	cell: 0.587, 27.206%; route: 1.571, 72.794%

Path14

Path Summary:

Slack	1.718
Data Arrival Time	10.161
Data Required Time	11.879
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.161	2.643	tNET	FF	1	R3C6[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.157	1.571	tNET	RR	1	R3C6[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
11.879	-0.278	tSu		1	R3C6[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.643, 88.189%; tC2Q: 0.354, 11.811%
Required Clock Path Delay	cell: 0.587, 27.206%; route: 1.571, 72.794%

Path15

Path Summary:

Slack	1.718
Data Arrival Time	10.161
Data Required Time	11.879
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.161	2.643	tNET	FF	1	R3C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.157	1.571	tNET	RR	1	R3C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
11.879	-0.278	tSu		1	R3C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.643, 88.189%; tC2Q: 0.354, 11.811%
Required Clock Path Delay	cell: 0.587, 27.206%; route: 1.571, 72.794%

Path16

Path Summary:

Slack	1.718
Data Arrival Time	10.161
Data Required Time	11.879
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.161	2.643	tNET	FF	1	R3C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.157	1.571	tNET	RR	1	R3C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
11.879	-0.278	tSu		1	R3C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.643, 88.189%; tC2Q: 0.354, 11.811%
Required Clock Path Delay	cell: 0.587, 27.206%; route: 1.571, 72.794%

Path17

Path Summary:

Slack	1.718
Data Arrival Time	10.161
Data Required Time	11.879
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.161	2.643	tNET	FF	1	R3C6[3][A]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.157	1.571	tNET	RR	1	R3C6[3][A]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
11.879	-0.278	tSu		1	R3C6[3][A]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.643, 88.189%; tC2Q: 0.354, 11.811%
Required Clock Path Delay	cell: 0.587, 27.206%; route: 1.571, 72.794%

Path18

Path Summary:

Slack	1.725
Data Arrival Time	10.147
Data Required Time	11.872
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.147	2.629	tNET	FF	1	R3C7[0][A]	u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.150	1.563	tNET	RR	1	R3C7[0][A]	u_la0_top/u_ao_match_0/match_sep_s0/CLK
11.872	-0.278	tSu		1	R3C7[0][A]	u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.629, 88.132%; tC2Q: 0.354, 11.868%
Required Clock Path Delay	cell: 0.587, 27.301%; route: 1.563, 72.699%

Path19

Path Summary:

Slack	1.725
Data Arrival Time	10.147
Data Required Time	11.872
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.147	2.629	tNET	FF	1	R3C7[0][B]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.150	1.563	tNET	RR	1	R3C7[0][B]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
11.872	-0.278	tSu		1	R3C7[0][B]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.629, 88.132%; tC2Q: 0.354, 11.868%
Required Clock Path Delay	cell: 0.587, 27.301%; route: 1.563, 72.699%

Path20

Path Summary:

Slack	1.725
Data Arrival Time	10.147
Data Required Time	11.872
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.147	2.629	tNET	FF	1	R3C7[1][A]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.150	1.563	tNET	RR	1	R3C7[1][A]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK
11.872	-0.278	tSu		1	R3C7[1][A]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.629, 88.132%; tC2Q: 0.354, 11.868%
Required Clock Path Delay	cell: 0.587, 27.301%; route: 1.563, 72.699%

Path21

Path Summary:

Slack	1.725
Data Arrival Time	10.147
Data Required Time	11.872
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.147	2.629	tNET	FF	1	R3C7[1][B]	u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.150	1.563	tNET	RR	1	R3C7[1][B]	u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
11.872	-0.278	tSu		1	R3C7[1][B]	u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.629, 88.132%; tC2Q: 0.354, 11.868%
Required Clock Path Delay	cell: 0.587, 27.301%; route: 1.563, 72.699%

Path22

Path Summary:

Slack	1.725
Data Arrival Time	10.143
Data Required Time	11.868
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.143	2.625	tNET	FF	1	R5C7[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.146	1.559	tNET	RR	1	R5C7[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
11.868	-0.278	tSu		1	R5C7[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.018
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.625, 88.116%; tC2Q: 0.354, 11.884%
Required Clock Path Delay	cell: 0.587, 27.352%; route: 1.559, 72.648%

Path23

Path Summary:

Slack	1.725
Data Arrival Time	10.156
Data Required Time	11.881
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.156	2.638	tNET	FF	1	R2C4[0][A]	u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.159	1.572	tNET	RR	1	R2C4[0][A]	u_la0_top/capture_window_sel_5_s1/CLK
11.881	-0.278	tSu		1	R2C4[0][A]	u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	-0.005
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.638, 88.168%; tC2Q: 0.354, 11.832%
Required Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%

Path24

Path Summary:

Slack	1.725
Data Arrival Time	10.156
Data Required Time	11.881
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.156	2.638	tNET	FF	1	R2C4[0][B]	u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.159	1.572	tNET	RR	1	R2C4[0][B]	u_la0_top/capture_window_sel_6_s1/CLK
11.881	-0.278	tSu		1	R2C4[0][B]	u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	-0.005
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.638, 88.168%; tC2Q: 0.354, 11.832%
Required Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%

Path25

Path Summary:

Slack	1.725
Data Arrival Time	10.156
Data Required Time	11.881
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.591	0.591	tINS	FF	114	IOB29[A]	clk_ibuf/O
7.164	1.573	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
7.518	0.354	tC2Q	FF	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
10.156	2.638	tNET	FF	1	R2C4[1][A]	u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.587	0.587	tINS	RR	114	IOB29[A]	clk_ibuf/O
12.159	1.572	tNET	RR	1	R2C4[1][A]	u_la0_top/capture_window_sel_7_s1/CLK
11.881	-0.278	tSu		1	R2C4[1][A]	u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	-0.005
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.591, 27.322%; route: 1.573, 72.678%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.638, 88.168%; tC2Q: 0.354, 11.832%
Required Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	6.627
Data Arrival Time	7.878
Data Required Time	1.251
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.878	1.409	tNET	RR	1	R2C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.304	0.723	tNET	RR	1	R2C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.251	-0.053	tHld		1	R2C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.007
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.409, 89.917%; tC2Q: 0.158, 10.083%
Required Clock Path Delay	cell: 0.581, 44.561%; route: 0.723, 55.439%

Path2

Path Summary:

Slack	6.627
Data Arrival Time	7.878
Data Required Time	1.251
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.878	1.409	tNET	RR	1	R2C8[3][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.304	0.723	tNET	RR	1	R2C8[3][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
1.251	-0.053	tHld		1	R2C8[3][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-0.007
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.409, 89.917%; tC2Q: 0.158, 10.083%
Required Clock Path Delay	cell: 0.581, 44.561%; route: 0.723, 55.439%

Path3

Path Summary:

Slack	6.627
Data Arrival Time	7.878
Data Required Time	1.251
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.878	1.409	tNET	RR	1	R2C8[3][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.304	0.723	tNET	RR	1	R2C8[3][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
1.251	-0.053	tHld		1	R2C8[3][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew	-0.007
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.409, 89.917%; tC2Q: 0.158, 10.083%
Required Clock Path Delay	cell: 0.581, 44.561%; route: 0.723, 55.439%

Path4

Path Summary:

Slack	6.630
Data Arrival Time	7.885
Data Required Time	1.255
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.885	1.416	tNET	RR	1	R2C9[3][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.308	0.727	tNET	RR	1	R2C9[3][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.255	-0.053	tHld		1	R2C9[3][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.416, 89.965%; tC2Q: 0.158, 10.035%
Required Clock Path Delay	cell: 0.581, 44.424%; route: 0.727, 55.576%

Path5

Path Summary:

Slack	6.631
Data Arrival Time	7.886
Data Required Time	1.255
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.886	1.417	tNET	RR	1	R2C5[0][A]	u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.308	0.727	tNET	RR	1	R2C5[0][A]	u_la0_top/capture_window_sel_0_s3/CLK
1.255	-0.053	tHld		1	R2C5[0][A]	u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.417, 89.968%; tC2Q: 0.158, 10.032%
Required Clock Path Delay	cell: 0.581, 44.424%; route: 0.727, 55.576%

Path6

Path Summary:

Slack	6.631
Data Arrival Time	7.886
Data Required Time	1.255
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.886	1.417	tNET	RR	1	R2C5[0][B]	u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.308	0.727	tNET	RR	1	R2C5[0][B]	u_la0_top/triger_level_cnt_0_s3/CLK
1.255	-0.053	tHld		1	R2C5[0][B]	u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.417, 89.968%; tC2Q: 0.158, 10.032%
Required Clock Path Delay	cell: 0.581, 44.424%; route: 0.727, 55.576%

Path7

Path Summary:

Slack	6.631
Data Arrival Time	7.886
Data Required Time	1.255
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_end_dly_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.886	1.417	tNET	RR	1	R2C5[2][B]	u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.308	0.727	tNET	RR	1	R2C5[2][B]	u_la0_top/capture_end_dly_s0/CLK
1.255	-0.053	tHld		1	R2C5[2][B]	u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.417, 89.968%; tC2Q: 0.158, 10.032%
Required Clock Path Delay	cell: 0.581, 44.424%; route: 0.727, 55.576%

Path8

Path Summary:

Slack	6.631
Data Arrival Time	7.886
Data Required Time	1.255
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.886	1.417	tNET	RR	1	R2C5[1][A]	u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.308	0.727	tNET	RR	1	R2C5[1][A]	u_la0_top/triger_s0/CLK
1.255	-0.053	tHld		1	R2C5[1][A]	u_la0_top/triger_s0

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.417, 89.968%; tC2Q: 0.158, 10.032%
Required Clock Path Delay	cell: 0.581, 44.424%; route: 0.727, 55.576%

Path9

Path Summary:

Slack	6.631
Data Arrival Time	7.886
Data Required Time	1.255
From	u_la0_top/rst_ao_s0
To	u_la0_top/start_reg_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.886	1.417	tNET	RR	1	R2C5[1][B]	u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.308	0.727	tNET	RR	1	R2C5[1][B]	u_la0_top/start_reg_s0/CLK
1.255	-0.053	tHld		1	R2C5[1][B]	u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.417, 89.968%; tC2Q: 0.158, 10.032%
Required Clock Path Delay	cell: 0.581, 44.424%; route: 0.727, 55.576%

Path10

Path Summary:

Slack	6.631
Data Arrival Time	7.886
Data Required Time	1.255
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.886	1.417	tNET	RR	1	R2C5[2][A]	u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.308	0.727	tNET	RR	1	R2C5[2][A]	u_la0_top/internal_reg_start_dly_0_s0/CLK
1.255	-0.053	tHld		1	R2C5[2][A]	u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.417, 89.968%; tC2Q: 0.158, 10.032%
Required Clock Path Delay	cell: 0.581, 44.424%; route: 0.727, 55.576%

Path11

Path Summary:

Slack	6.631
Data Arrival Time	7.886
Data Required Time	1.255
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.886	1.417	tNET	RR	1	R2C5[3][A]	u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.308	0.727	tNET	RR	1	R2C5[3][A]	u_la0_top/internal_reg_start_dly_1_s0/CLK
1.255	-0.053	tHld		1	R2C5[3][A]	u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.417, 89.968%; tC2Q: 0.158, 10.032%
Required Clock Path Delay	cell: 0.581, 44.424%; route: 0.727, 55.576%

Path12

Path Summary:

Slack	6.631
Data Arrival Time	7.878
Data Required Time	1.247
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.878	1.410	tNET	RR	1	R4C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R4C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.247	-0.053	tHld		1	R4C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.010
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.410, 89.920%; tC2Q: 0.158, 10.080%
Required Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%

Path13

Path Summary:

Slack	6.631
Data Arrival Time	7.878
Data Required Time	1.247
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.878	1.410	tNET	RR	1	R4C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R4C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
1.247	-0.053	tHld		1	R4C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.010
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.410, 89.920%; tC2Q: 0.158, 10.080%
Required Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%

Path14

Path Summary:

Slack	6.631
Data Arrival Time	7.878
Data Required Time	1.247
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.878	1.410	tNET	RR	1	R4C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R4C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.247	-0.053	tHld		1	R4C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.010
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.410, 89.920%; tC2Q: 0.158, 10.080%
Required Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%

Path15

Path Summary:

Slack	6.631
Data Arrival Time	7.878
Data Required Time	1.247
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.878	1.410	tNET	RR	1	R4C6[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R4C6[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.247	-0.053	tHld		1	R4C6[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.010
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.410, 89.920%; tC2Q: 0.158, 10.080%
Required Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%

Path16

Path Summary:

Slack	6.631
Data Arrival Time	7.878
Data Required Time	1.247
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.878	1.410	tNET	RR	1	R4C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R4C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.247	-0.053	tHld		1	R4C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-0.010
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.410, 89.920%; tC2Q: 0.158, 10.080%
Required Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%

Path17

Path Summary:

Slack	6.631
Data Arrival Time	7.878
Data Required Time	1.247
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.878	1.410	tNET	RR	1	R4C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R4C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
1.247	-0.053	tHld		1	R4C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-0.010
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.410, 89.920%; tC2Q: 0.158, 10.080%
Required Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%

Path18

Path Summary:

Slack	6.631
Data Arrival Time	7.878
Data Required Time	1.247
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.878	1.410	tNET	RR	1	R4C6[3][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R4C6[3][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.247	-0.053	tHld		1	R4C6[3][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-0.010
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.410, 89.920%; tC2Q: 0.158, 10.080%
Required Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%

Path19

Path Summary:

Slack	6.632
Data Arrival Time	7.884
Data Required Time	1.251
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.884	1.415	tNET	RR	1	R4C5[0][A]	u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.304	0.723	tNET	RR	1	R4C5[0][A]	u_la0_top/capture_window_sel_1_s1/CLK
1.251	-0.053	tHld		1	R4C5[0][A]	u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	-0.006
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.415, 89.955%; tC2Q: 0.158, 10.045%
Required Clock Path Delay	cell: 0.581, 44.544%; route: 0.723, 55.456%

Path20

Path Summary:

Slack	6.632
Data Arrival Time	7.884
Data Required Time	1.251
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.884	1.415	tNET	RR	1	R4C5[0][B]	u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.304	0.723	tNET	RR	1	R4C5[0][B]	u_la0_top/capture_window_sel_2_s1/CLK
1.251	-0.053	tHld		1	R4C5[0][B]	u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.006
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.415, 89.955%; tC2Q: 0.158, 10.045%
Required Clock Path Delay	cell: 0.581, 44.544%; route: 0.723, 55.456%

Path21

Path Summary:

Slack	6.632
Data Arrival Time	7.884
Data Required Time	1.251
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.884	1.415	tNET	RR	1	R4C5[1][A]	u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.304	0.723	tNET	RR	1	R4C5[1][A]	u_la0_top/capture_window_sel_3_s1/CLK
1.251	-0.053	tHld		1	R4C5[1][A]	u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.006
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.415, 89.955%; tC2Q: 0.158, 10.045%
Required Clock Path Delay	cell: 0.581, 44.544%; route: 0.723, 55.456%

Path22

Path Summary:

Slack	6.632
Data Arrival Time	7.884
Data Required Time	1.251
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.884	1.415	tNET	RR	1	R4C5[1][B]	u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.304	0.723	tNET	RR	1	R4C5[1][B]	u_la0_top/capture_window_sel_4_s1/CLK
1.251	-0.053	tHld		1	R4C5[1][B]	u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	-0.006
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.415, 89.955%; tC2Q: 0.158, 10.045%
Required Clock Path Delay	cell: 0.581, 44.544%; route: 0.723, 55.456%

Path23

Path Summary:

Slack	6.634
Data Arrival Time	7.887
Data Required Time	1.253
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.887	1.419	tNET	RR	1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.306	0.725	tNET	RR	1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1/CLK
1.253	-0.053	tHld		1	R3C5[1][A]	u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.005
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.419, 89.979%; tC2Q: 0.158, 10.021%
Required Clock Path Delay	cell: 0.581, 44.484%; route: 0.725, 55.516%

Path24

Path Summary:

Slack	6.634
Data Arrival Time	7.887
Data Required Time	1.253
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.887	1.419	tNET	RR	1	R3C5[1][B]	u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.306	0.725	tNET	RR	1	R3C5[1][B]	u_la0_top/triger_level_cnt_2_s1/CLK
1.253	-0.053	tHld		1	R3C5[1][B]	u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.005
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.419, 89.979%; tC2Q: 0.158, 10.021%
Required Clock Path Delay	cell: 0.581, 44.484%; route: 0.725, 55.516%

Path25

Path Summary:

Slack	6.634
Data Arrival Time	7.887
Data Required Time	1.253
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.583	0.583	tINS	FF	114	IOB29[A]	clk_ibuf/O
6.311	0.728	tNET	FF	1	R2C6[2][A]	u_la0_top/rst_ao_s0/CLK
6.469	0.158	tC2Q	FR	61	R2C6[2][A]	u_la0_top/rst_ao_s0/Q
7.887	1.419	tNET	RR	1	R3C5[2][A]	u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.581	0.581	tINS	RR	114	IOB29[A]	clk_ibuf/O
1.306	0.725	tNET	RR	1	R3C5[2][A]	u_la0_top/triger_level_cnt_3_s1/CLK
1.253	-0.053	tHld		1	R3C5[2][A]	u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.005
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.583, 44.455%; route: 0.728, 55.545%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.419, 89.979%; tC2Q: 0.158, 10.021%
Required Clock Path Delay	cell: 0.581, 44.484%; route: 0.725, 55.516%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.279
Actual Width:	4.141
Required Width:	0.862
Type:	Low Pulse Width
Clock:	clk
Objects:	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.591	0.591	tINS	FF	clk_ibuf/O
7.143	1.552	tNET	FF	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.581	0.581	tINS	RR	clk_ibuf/O
11.284	0.703	tNET	RR	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW2

MPW Summary:

Slack:	3.289
Actual Width:	4.151
Required Width:	0.862
Type:	High Pulse Width
Clock:	clk
Objects:	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
0.587	0.587	tINS	RR	clk_ibuf/O
2.140	1.553	tNET	RR	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.583	0.583	tINS	FF	clk_ibuf/O
6.290	0.708	tNET	FF	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW3

MPW Summary:

Slack:	3.932
Actual Width:	4.132
Required Width:	0.200
Type:	Low Pulse Width
Clock:	clk
Objects:	key_filter_inst/cnt_22_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.591	0.591	tINS	FF	clk_ibuf/O
7.179	1.588	tNET	FF	key_filter_inst/cnt_22_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.581	0.581	tINS	RR	clk_ibuf/O
11.311	0.730	tNET	RR	key_filter_inst/cnt_22_s0/CLK

MPW4

MPW Summary:

Slack:	3.932
Actual Width:	4.132
Required Width:	0.200
Type:	Low Pulse Width
Clock:	clk
Objects:	key_filter_inst/cnt_20_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.591	0.591	tINS	FF	clk_ibuf/O
7.179	1.588	tNET	FF	key_filter_inst/cnt_20_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.581	0.581	tINS	RR	clk_ibuf/O
11.311	0.730	tNET	RR	key_filter_inst/cnt_20_s0/CLK

MPW5

MPW Summary:

Slack:	3.933
Actual Width:	4.133
Required Width:	0.200
Type:	Low Pulse Width
Clock:	clk
Objects:	key_filter_inst/cnt_23_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.591	0.591	tINS	FF	clk_ibuf/O
7.177	1.586	tNET	FF	key_filter_inst/cnt_23_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.581	0.581	tINS	RR	clk_ibuf/O
11.309	0.729	tNET	RR	key_filter_inst/cnt_23_s0/CLK

MPW6

MPW Summary:

Slack:	3.933
Actual Width:	4.133
Required Width:	0.200
Type:	Low Pulse Width
Clock:	clk
Objects:	key_filter_inst/cnt_19_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.591	0.591	tINS	FF	clk_ibuf/O
7.177	1.586	tNET	FF	key_filter_inst/cnt_19_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.581	0.581	tINS	RR	clk_ibuf/O
11.309	0.729	tNET	RR	key_filter_inst/cnt_19_s0/CLK

MPW7

MPW Summary:

Slack:	3.933
Actual Width:	4.133
Required Width:	0.200
Type:	Low Pulse Width
Clock:	clk
Objects:	key_filter_inst/key_flag_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.591	0.591	tINS	FF	clk_ibuf/O
7.177	1.586	tNET	FF	key_filter_inst/key_flag_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.581	0.581	tINS	RR	clk_ibuf/O
11.309	0.729	tNET	RR	key_filter_inst/key_flag_s1/CLK

MPW8

MPW Summary:

Slack:	3.936
Actual Width:	4.136
Required Width:	0.200
Type:	Low Pulse Width
Clock:	clk
Objects:	u_la0_top/internal_reg_start_dly_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.591	0.591	tINS	FF	clk_ibuf/O
7.171	1.580	tNET	FF	u_la0_top/internal_reg_start_dly_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.581	0.581	tINS	RR	clk_ibuf/O
11.308	0.727	tNET	RR	u_la0_top/internal_reg_start_dly_1_s0/CLK

MPW9

MPW Summary:

Slack:	3.936
Actual Width:	4.136
Required Width:	0.200
Type:	Low Pulse Width
Clock:	clk
Objects:	u_la0_top/triger_level_cnt_0_s3

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.591	0.591	tINS	FF	clk_ibuf/O
7.171	1.580	tNET	FF	u_la0_top/triger_level_cnt_0_s3/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.581	0.581	tINS	RR	clk_ibuf/O
11.308	0.727	tNET	RR	u_la0_top/triger_level_cnt_0_s3/CLK

MPW10

MPW Summary:

Slack:	3.936
Actual Width:	4.136
Required Width:	0.200
Type:	Low Pulse Width
Clock:	clk
Objects:	u_la0_top/capture_window_sel_0_s3

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.591	0.591	tINS	FF	clk_ibuf/O
7.171	1.580	tNET	FF	u_la0_top/capture_window_sel_0_s3/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.581	0.581	tINS	RR	clk_ibuf/O
11.308	0.727	tNET	RR	u_la0_top/capture_window_sel_0_s3/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
114	clk_d	6.790	1.588
22	key_filter_inst/n113_9	6.968	0.560
11	key_filter_inst/n100_8	6.790	0.561
8	key_filter_inst/n95_8	7.612	0.539
8	key_filter_inst/n109_8	6.790	0.552
7	key_filter_inst/state[0]	8.276	0.375
7	key_filter_inst/en_cnt	8.225	0.574
5	key_filter_inst/cnt[22]	7.639	0.178
5	key_filter_inst/cnt[13]	6.981	0.275
5	key_filter_inst/cnt[8]	7.313	0.123

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R18C46	33.33%
R20C47	27.78%
R18C47	25.00%
R21C47	22.22%
R17C46	22.22%
R20C46	22.22%
R17C47	20.83%
R21C46	19.44%
R18C45	9.72%
R21C45	6.94%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command