Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_usb\acm2108_ddr3_usb\src\fifo\temp\FIFO\fifo_define.v
C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_usb\acm2108_ddr3_usb\src\fifo\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW5AT-LV138PG484AC1/I0
Device GW5AT-138
Device Version B
Created Time Tue Sep 9 14:17:39 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo
Synthesis Process Running parser:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.331s, Peak memory usage = 76.824MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.824MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.824MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.824MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.824MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.824MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.824MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.824MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.824MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.824MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.824MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.824MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.327s, Peak memory usage = 91.066MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 91.066MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 91.066MB
Total Time and Memory Usage CPU time = 0h 0m 0.623s, Elapsed time = 0h 0m 0.731s, Peak memory usage = 91.066MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 50
I/O Buf 50
    IBUF 21
    OBUF 29
Register 103
    DFFPE 5
    DFFCE 98
LUT 91
    LUT2 28
    LUT3 23
    LUT4 40
ALU 21
    ALU 21
INV 2
    INV 2
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 114(93 LUT, 21 ALU) / 138240 <1%
Register 103 / 139095 <1%
  --Register as Latch 0 / 139095 0%
  --Register as FF 103 / 139095 <1%
BSRAM 1 / 340 <1%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 142.628(MHz) 8 TOP
2 WrClk 100.000(MHz) 207.792(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.989
Data Arrival Time 7.360
Data Required Time 10.349
From fifo_inst/rbin_num_4_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 58 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/rbin_num_4_s0/CLK
0.795 0.382 tC2Q RR 7 fifo_inst/rbin_num_4_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/Equal.rgraynext_6_s2/I0
1.786 0.579 tINS RR 1 fifo_inst/Equal.rgraynext_6_s2/F
2.199 0.413 tNET RR 1 fifo_inst/Equal.rgraynext_6_s1/I0
2.778 0.579 tINS RR 6 fifo_inst/Equal.rgraynext_6_s1/F
3.190 0.413 tNET RR 1 fifo_inst/rbin_num_next_6_s3/I1
3.758 0.567 tINS RR 2 fifo_inst/rbin_num_next_6_s3/F
4.170 0.413 tNET RR 1 fifo_inst/Equal.rgraynext_5_s1/I0
4.749 0.579 tINS RR 2 fifo_inst/Equal.rgraynext_5_s1/F
5.161 0.413 tNET RR 2 fifo_inst/n138_s0/I0
5.756 0.595 tINS RF 1 fifo_inst/n138_s0/COUT
5.756 0.000 tNET FF 2 fifo_inst/n139_s0/CIN
5.806 0.050 tINS FR 1 fifo_inst/n139_s0/COUT
5.806 0.000 tNET RR 2 fifo_inst/n140_s0/CIN
5.856 0.050 tINS RR 1 fifo_inst/n140_s0/COUT
5.856 0.000 tNET RR 2 fifo_inst/n141_s0/CIN
5.906 0.050 tINS RR 1 fifo_inst/n141_s0/COUT
5.906 0.000 tNET RR 2 fifo_inst/n142_s0/CIN
5.956 0.050 tINS RR 1 fifo_inst/n142_s0/COUT
6.369 0.413 tNET RR 1 fifo_inst/rempty_val_s1/I0
6.948 0.579 tINS RR 1 fifo_inst/rempty_val_s1/F
7.360 0.413 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 58 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.677, 52.932%; route: 2.887, 41.562%; tC2Q: 0.382, 5.506%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 4.066
Data Arrival Time 6.283
Data Required Time 10.349
From fifo_inst/Equal.rq2_wptr_10_s0
To fifo_inst/Rnum_10_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 58 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Equal.rq2_wptr_10_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Equal.rq2_wptr_10_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_7_s0/I0
1.786 0.579 tINS RR 4 fifo_inst/Equal.wcount_r_7_s0/F
2.199 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_4_s0/I3
2.487 0.289 tINS RR 4 fifo_inst/Equal.wcount_r_4_s0/F
2.900 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_1_s0/I3
3.189 0.289 tINS RR 2 fifo_inst/Equal.wcount_r_1_s0/F
3.601 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_0_s0/I1
4.169 0.567 tINS RR 1 fifo_inst/Equal.wcount_r_0_s0/F
4.581 0.413 tNET RR 2 fifo_inst/rcnt_sub_0_s/I0
5.176 0.595 tINS RF 1 fifo_inst/rcnt_sub_0_s/COUT
5.176 0.000 tNET FF 2 fifo_inst/rcnt_sub_1_s/CIN
5.226 0.050 tINS FR 1 fifo_inst/rcnt_sub_1_s/COUT
5.226 0.000 tNET RR 2 fifo_inst/rcnt_sub_2_s/CIN
5.276 0.050 tINS RR 1 fifo_inst/rcnt_sub_2_s/COUT
5.276 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
5.326 0.050 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
5.326 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
5.376 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
5.376 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.426 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.426 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
5.476 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
5.476 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
5.526 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
5.526 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
5.576 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
5.576 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
5.626 0.050 tINS RR 1 fifo_inst/rcnt_sub_9_s/COUT
5.626 0.000 tNET RR 2 fifo_inst/rcnt_sub_10_s/CIN
5.870 0.244 tINS RR 1 fifo_inst/rcnt_sub_10_s/SUM
6.283 0.413 tNET RR 1 fifo_inst/Rnum_10_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 58 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Rnum_10_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Rnum_10_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.012, 51.320%; route: 2.475, 42.164%; tC2Q: 0.382, 6.516%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 4.116
Data Arrival Time 6.233
Data Required Time 10.349
From fifo_inst/Equal.rq2_wptr_10_s0
To fifo_inst/Rnum_9_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 58 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Equal.rq2_wptr_10_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Equal.rq2_wptr_10_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_7_s0/I0
1.786 0.579 tINS RR 4 fifo_inst/Equal.wcount_r_7_s0/F
2.199 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_4_s0/I3
2.487 0.289 tINS RR 4 fifo_inst/Equal.wcount_r_4_s0/F
2.900 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_1_s0/I3
3.189 0.289 tINS RR 2 fifo_inst/Equal.wcount_r_1_s0/F
3.601 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_0_s0/I1
4.169 0.567 tINS RR 1 fifo_inst/Equal.wcount_r_0_s0/F
4.581 0.413 tNET RR 2 fifo_inst/rcnt_sub_0_s/I0
5.176 0.595 tINS RF 1 fifo_inst/rcnt_sub_0_s/COUT
5.176 0.000 tNET FF 2 fifo_inst/rcnt_sub_1_s/CIN
5.226 0.050 tINS FR 1 fifo_inst/rcnt_sub_1_s/COUT
5.226 0.000 tNET RR 2 fifo_inst/rcnt_sub_2_s/CIN
5.276 0.050 tINS RR 1 fifo_inst/rcnt_sub_2_s/COUT
5.276 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
5.326 0.050 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
5.326 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
5.376 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
5.376 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.426 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.426 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
5.476 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
5.476 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
5.526 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
5.526 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
5.576 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
5.576 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
5.820 0.244 tINS RR 1 fifo_inst/rcnt_sub_9_s/SUM
6.233 0.413 tNET RR 1 fifo_inst/Rnum_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 58 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Rnum_9_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Rnum_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.962, 50.902%; route: 2.475, 42.526%; tC2Q: 0.382, 6.572%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 4.166
Data Arrival Time 6.183
Data Required Time 10.349
From fifo_inst/Equal.rq2_wptr_10_s0
To fifo_inst/Rnum_8_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 58 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Equal.rq2_wptr_10_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Equal.rq2_wptr_10_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_7_s0/I0
1.786 0.579 tINS RR 4 fifo_inst/Equal.wcount_r_7_s0/F
2.199 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_4_s0/I3
2.487 0.289 tINS RR 4 fifo_inst/Equal.wcount_r_4_s0/F
2.900 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_1_s0/I3
3.189 0.289 tINS RR 2 fifo_inst/Equal.wcount_r_1_s0/F
3.601 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_0_s0/I1
4.169 0.567 tINS RR 1 fifo_inst/Equal.wcount_r_0_s0/F
4.581 0.413 tNET RR 2 fifo_inst/rcnt_sub_0_s/I0
5.176 0.595 tINS RF 1 fifo_inst/rcnt_sub_0_s/COUT
5.176 0.000 tNET FF 2 fifo_inst/rcnt_sub_1_s/CIN
5.226 0.050 tINS FR 1 fifo_inst/rcnt_sub_1_s/COUT
5.226 0.000 tNET RR 2 fifo_inst/rcnt_sub_2_s/CIN
5.276 0.050 tINS RR 1 fifo_inst/rcnt_sub_2_s/COUT
5.276 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
5.326 0.050 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
5.326 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
5.376 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
5.376 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.426 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.426 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
5.476 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
5.476 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
5.526 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
5.526 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
5.770 0.244 tINS RR 1 fifo_inst/rcnt_sub_8_s/SUM
6.183 0.413 tNET RR 1 fifo_inst/Rnum_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 58 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Rnum_8_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Rnum_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.912, 50.477%; route: 2.475, 42.894%; tC2Q: 0.382, 6.629%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 4.216
Data Arrival Time 6.133
Data Required Time 10.349
From fifo_inst/Equal.rq2_wptr_10_s0
To fifo_inst/Rnum_7_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 58 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Equal.rq2_wptr_10_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Equal.rq2_wptr_10_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_7_s0/I0
1.786 0.579 tINS RR 4 fifo_inst/Equal.wcount_r_7_s0/F
2.199 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_4_s0/I3
2.487 0.289 tINS RR 4 fifo_inst/Equal.wcount_r_4_s0/F
2.900 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_1_s0/I3
3.189 0.289 tINS RR 2 fifo_inst/Equal.wcount_r_1_s0/F
3.601 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_0_s0/I1
4.169 0.567 tINS RR 1 fifo_inst/Equal.wcount_r_0_s0/F
4.581 0.413 tNET RR 2 fifo_inst/rcnt_sub_0_s/I0
5.176 0.595 tINS RF 1 fifo_inst/rcnt_sub_0_s/COUT
5.176 0.000 tNET FF 2 fifo_inst/rcnt_sub_1_s/CIN
5.226 0.050 tINS FR 1 fifo_inst/rcnt_sub_1_s/COUT
5.226 0.000 tNET RR 2 fifo_inst/rcnt_sub_2_s/CIN
5.276 0.050 tINS RR 1 fifo_inst/rcnt_sub_2_s/COUT
5.276 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
5.326 0.050 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
5.326 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
5.376 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
5.376 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.426 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.426 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
5.476 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
5.476 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
5.720 0.244 tINS RR 1 fifo_inst/rcnt_sub_7_s/SUM
6.133 0.413 tNET RR 1 fifo_inst/Rnum_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 58 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Rnum_7_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Rnum_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.862, 50.044%; route: 2.475, 43.269%; tC2Q: 0.382, 6.687%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%