Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_usb\acm2108_ddr3_usb\src\rd_data_fifo\temp\FIFO\fifo_define.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_usb\acm2108_ddr3_usb\src\rd_data_fifo\temp\FIFO\fifo_parameter.v D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\edc.v D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo.v D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.03 (64-bit) |
| Part Number | GW5AT-LV138PG484AC1/I0 |
| Device | GW5AT-138 |
| Device Version | B |
| Created Time | Tue Sep 9 13:34:50 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | rd_data_fifo |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.338s, Peak memory usage = 77.410MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 77.410MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 77.410MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 77.410MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 77.410MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 77.410MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 77.410MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.410MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 77.410MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 77.410MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 77.410MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.410MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.937s, Elapsed time = 0h 0m 0.977s, Peak memory usage = 94.199MB Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 94.199MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 94.199MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 94.199MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 176 |
| I/O Buf | 176 |
| IBUF | 133 |
| OBUF | 43 |
| Register | 112 |
| DFFPE | 6 |
| DFFCE | 106 |
| LUT | 302 |
| LUT2 | 34 |
| LUT3 | 88 |
| LUT4 | 180 |
| ALU | 32 |
| ALU | 32 |
| INV | 4 |
| INV | 4 |
| BSRAM | 4 |
| SDPB | 4 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 338(306 LUT, 32 ALU) / 138240 | <1% |
| Register | 112 / 139095 | <1% |
| --Register as Latch | 0 / 139095 | 0% |
| --Register as FF | 112 / 139095 | <1% |
| BSRAM | 4 / 340 | 2% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | RdClk | Base | 10.000 | 100.000 | 0.000 | 5.000 | RdClk_ibuf/I | ||
| 2 | WrClk | Base | 10.000 | 100.000 | 0.000 | 5.000 | WrClk_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | RdClk | 100.000(MHz) | 142.071(MHz) | 8 | TOP |
| 2 | WrClk | 100.000(MHz) | 144.144(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 2.961 |
| Data Arrival Time | 7.388 |
| Data Required Time | 10.349 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Empty_s0 |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 7 | fifo_inst/Empty_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s4/I0 |
| 1.786 | 0.579 | tINS | RR | 10 | fifo_inst/rbin_num_next_2_s4/F |
| 2.199 | 0.413 | tNET | RR | 1 | fifo_inst/Small.rgraynext_2_s2/I1 |
| 2.766 | 0.567 | tINS | RR | 7 | fifo_inst/Small.rgraynext_2_s2/F |
| 3.179 | 0.413 | tNET | RR | 1 | fifo_inst/Small.rgraynext_3_s1/I1 |
| 3.746 | 0.567 | tINS | RR | 3 | fifo_inst/Small.rgraynext_3_s1/F |
| 4.159 | 0.413 | tNET | RR | 1 | fifo_inst/Small.rgraynext_4_s0/I1 |
| 4.726 | 0.567 | tINS | RR | 2 | fifo_inst/Small.rgraynext_4_s0/F |
| 5.139 | 0.413 | tNET | RR | 2 | fifo_inst/n681_s0/I0 |
| 5.734 | 0.595 | tINS | RF | 1 | fifo_inst/n681_s0/COUT |
| 5.734 | 0.000 | tNET | FF | 2 | fifo_inst/n682_s0/CIN |
| 5.784 | 0.050 | tINS | FR | 1 | fifo_inst/n682_s0/COUT |
| 5.784 | 0.000 | tNET | RR | 2 | fifo_inst/n683_s0/CIN |
| 5.834 | 0.050 | tINS | RR | 1 | fifo_inst/n683_s0/COUT |
| 5.834 | 0.000 | tNET | RR | 2 | fifo_inst/n684_s0/CIN |
| 5.884 | 0.050 | tINS | RR | 1 | fifo_inst/n684_s0/COUT |
| 5.884 | 0.000 | tNET | RR | 2 | fifo_inst/n685_s0/CIN |
| 5.934 | 0.050 | tINS | RR | 1 | fifo_inst/n685_s0/COUT |
| 5.934 | 0.000 | tNET | RR | 2 | fifo_inst/n686_s0/CIN |
| 5.984 | 0.050 | tINS | RR | 2 | fifo_inst/n686_s0/COUT |
| 6.396 | 0.413 | tNET | RR | 1 | fifo_inst/rempty_val_s1/I0 |
| 6.975 | 0.579 | tINS | RR | 1 | fifo_inst/rempty_val_s1/F |
| 7.388 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | fifo_inst/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.705, 53.118%; route: 2.887, 41.398%; tC2Q: 0.382, 5.484% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 3.005 |
| Data Arrival Time | 7.316 |
| Data Required Time | 10.321 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Small.mem_Small.mem_0_3_s |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 7 | fifo_inst/Empty_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s4/I0 |
| 1.786 | 0.579 | tINS | RR | 10 | fifo_inst/rbin_num_next_2_s4/F |
| 2.199 | 0.413 | tNET | RR | 1 | fifo_inst/Small.rgraynext_2_s2/I1 |
| 2.766 | 0.567 | tINS | RR | 7 | fifo_inst/Small.rgraynext_2_s2/F |
| 3.179 | 0.413 | tNET | RR | 1 | fifo_inst/Small.rgraynext_3_s1/I1 |
| 3.746 | 0.567 | tINS | RR | 3 | fifo_inst/Small.rgraynext_3_s1/F |
| 4.159 | 0.413 | tNET | RR | 1 | fifo_inst/Small.rgraynext_4_s0/I1 |
| 4.726 | 0.567 | tINS | RR | 2 | fifo_inst/Small.rgraynext_4_s0/F |
| 5.139 | 0.413 | tNET | RR | 2 | fifo_inst/n681_s0/I0 |
| 5.734 | 0.595 | tINS | RF | 1 | fifo_inst/n681_s0/COUT |
| 5.734 | 0.000 | tNET | FF | 2 | fifo_inst/n682_s0/CIN |
| 5.784 | 0.050 | tINS | FR | 1 | fifo_inst/n682_s0/COUT |
| 5.784 | 0.000 | tNET | RR | 2 | fifo_inst/n683_s0/CIN |
| 5.834 | 0.050 | tINS | RR | 1 | fifo_inst/n683_s0/COUT |
| 5.834 | 0.000 | tNET | RR | 2 | fifo_inst/n684_s0/CIN |
| 5.884 | 0.050 | tINS | RR | 1 | fifo_inst/n684_s0/COUT |
| 5.884 | 0.000 | tNET | RR | 2 | fifo_inst/n685_s0/CIN |
| 5.934 | 0.050 | tINS | RR | 1 | fifo_inst/n685_s0/COUT |
| 5.934 | 0.000 | tNET | RR | 2 | fifo_inst/n686_s0/CIN |
| 5.984 | 0.050 | tINS | RR | 2 | fifo_inst/n686_s0/COUT |
| 6.396 | 0.413 | tNET | RR | 1 | fifo_inst/n37_s1/I2 |
| 6.904 | 0.507 | tINS | RR | 4 | fifo_inst/n37_s1/F |
| 7.316 | 0.413 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_3_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_3_s/CLKB |
| 10.321 | -0.091 | tSu | 1 | fifo_inst/Small.mem_Small.mem_0_3_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.634, 52.635%; route: 2.887, 41.825%; tC2Q: 0.382, 5.540% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 3.005 |
| Data Arrival Time | 7.316 |
| Data Required Time | 10.321 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Small.mem_Small.mem_0_2_s |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 7 | fifo_inst/Empty_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s4/I0 |
| 1.786 | 0.579 | tINS | RR | 10 | fifo_inst/rbin_num_next_2_s4/F |
| 2.199 | 0.413 | tNET | RR | 1 | fifo_inst/Small.rgraynext_2_s2/I1 |
| 2.766 | 0.567 | tINS | RR | 7 | fifo_inst/Small.rgraynext_2_s2/F |
| 3.179 | 0.413 | tNET | RR | 1 | fifo_inst/Small.rgraynext_3_s1/I1 |
| 3.746 | 0.567 | tINS | RR | 3 | fifo_inst/Small.rgraynext_3_s1/F |
| 4.159 | 0.413 | tNET | RR | 1 | fifo_inst/Small.rgraynext_4_s0/I1 |
| 4.726 | 0.567 | tINS | RR | 2 | fifo_inst/Small.rgraynext_4_s0/F |
| 5.139 | 0.413 | tNET | RR | 2 | fifo_inst/n681_s0/I0 |
| 5.734 | 0.595 | tINS | RF | 1 | fifo_inst/n681_s0/COUT |
| 5.734 | 0.000 | tNET | FF | 2 | fifo_inst/n682_s0/CIN |
| 5.784 | 0.050 | tINS | FR | 1 | fifo_inst/n682_s0/COUT |
| 5.784 | 0.000 | tNET | RR | 2 | fifo_inst/n683_s0/CIN |
| 5.834 | 0.050 | tINS | RR | 1 | fifo_inst/n683_s0/COUT |
| 5.834 | 0.000 | tNET | RR | 2 | fifo_inst/n684_s0/CIN |
| 5.884 | 0.050 | tINS | RR | 1 | fifo_inst/n684_s0/COUT |
| 5.884 | 0.000 | tNET | RR | 2 | fifo_inst/n685_s0/CIN |
| 5.934 | 0.050 | tINS | RR | 1 | fifo_inst/n685_s0/COUT |
| 5.934 | 0.000 | tNET | RR | 2 | fifo_inst/n686_s0/CIN |
| 5.984 | 0.050 | tINS | RR | 2 | fifo_inst/n686_s0/COUT |
| 6.396 | 0.413 | tNET | RR | 1 | fifo_inst/n37_s1/I2 |
| 6.904 | 0.507 | tINS | RR | 4 | fifo_inst/n37_s1/F |
| 7.316 | 0.413 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_2_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_2_s/CLKB |
| 10.321 | -0.091 | tSu | 1 | fifo_inst/Small.mem_Small.mem_0_2_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.634, 52.635%; route: 2.887, 41.825%; tC2Q: 0.382, 5.540% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 3.005 |
| Data Arrival Time | 7.316 |
| Data Required Time | 10.321 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Small.mem_Small.mem_0_1_s |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 7 | fifo_inst/Empty_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s4/I0 |
| 1.786 | 0.579 | tINS | RR | 10 | fifo_inst/rbin_num_next_2_s4/F |
| 2.199 | 0.413 | tNET | RR | 1 | fifo_inst/Small.rgraynext_2_s2/I1 |
| 2.766 | 0.567 | tINS | RR | 7 | fifo_inst/Small.rgraynext_2_s2/F |
| 3.179 | 0.413 | tNET | RR | 1 | fifo_inst/Small.rgraynext_3_s1/I1 |
| 3.746 | 0.567 | tINS | RR | 3 | fifo_inst/Small.rgraynext_3_s1/F |
| 4.159 | 0.413 | tNET | RR | 1 | fifo_inst/Small.rgraynext_4_s0/I1 |
| 4.726 | 0.567 | tINS | RR | 2 | fifo_inst/Small.rgraynext_4_s0/F |
| 5.139 | 0.413 | tNET | RR | 2 | fifo_inst/n681_s0/I0 |
| 5.734 | 0.595 | tINS | RF | 1 | fifo_inst/n681_s0/COUT |
| 5.734 | 0.000 | tNET | FF | 2 | fifo_inst/n682_s0/CIN |
| 5.784 | 0.050 | tINS | FR | 1 | fifo_inst/n682_s0/COUT |
| 5.784 | 0.000 | tNET | RR | 2 | fifo_inst/n683_s0/CIN |
| 5.834 | 0.050 | tINS | RR | 1 | fifo_inst/n683_s0/COUT |
| 5.834 | 0.000 | tNET | RR | 2 | fifo_inst/n684_s0/CIN |
| 5.884 | 0.050 | tINS | RR | 1 | fifo_inst/n684_s0/COUT |
| 5.884 | 0.000 | tNET | RR | 2 | fifo_inst/n685_s0/CIN |
| 5.934 | 0.050 | tINS | RR | 1 | fifo_inst/n685_s0/COUT |
| 5.934 | 0.000 | tNET | RR | 2 | fifo_inst/n686_s0/CIN |
| 5.984 | 0.050 | tINS | RR | 2 | fifo_inst/n686_s0/COUT |
| 6.396 | 0.413 | tNET | RR | 1 | fifo_inst/n37_s1/I2 |
| 6.904 | 0.507 | tINS | RR | 4 | fifo_inst/n37_s1/F |
| 7.316 | 0.413 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_1_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_1_s/CLKB |
| 10.321 | -0.091 | tSu | 1 | fifo_inst/Small.mem_Small.mem_0_1_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.634, 52.635%; route: 2.887, 41.825%; tC2Q: 0.382, 5.540% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 3.005 |
| Data Arrival Time | 7.316 |
| Data Required Time | 10.321 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Small.mem_Small.mem_0_0_s |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 7 | fifo_inst/Empty_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s4/I0 |
| 1.786 | 0.579 | tINS | RR | 10 | fifo_inst/rbin_num_next_2_s4/F |
| 2.199 | 0.413 | tNET | RR | 1 | fifo_inst/Small.rgraynext_2_s2/I1 |
| 2.766 | 0.567 | tINS | RR | 7 | fifo_inst/Small.rgraynext_2_s2/F |
| 3.179 | 0.413 | tNET | RR | 1 | fifo_inst/Small.rgraynext_3_s1/I1 |
| 3.746 | 0.567 | tINS | RR | 3 | fifo_inst/Small.rgraynext_3_s1/F |
| 4.159 | 0.413 | tNET | RR | 1 | fifo_inst/Small.rgraynext_4_s0/I1 |
| 4.726 | 0.567 | tINS | RR | 2 | fifo_inst/Small.rgraynext_4_s0/F |
| 5.139 | 0.413 | tNET | RR | 2 | fifo_inst/n681_s0/I0 |
| 5.734 | 0.595 | tINS | RF | 1 | fifo_inst/n681_s0/COUT |
| 5.734 | 0.000 | tNET | FF | 2 | fifo_inst/n682_s0/CIN |
| 5.784 | 0.050 | tINS | FR | 1 | fifo_inst/n682_s0/COUT |
| 5.784 | 0.000 | tNET | RR | 2 | fifo_inst/n683_s0/CIN |
| 5.834 | 0.050 | tINS | RR | 1 | fifo_inst/n683_s0/COUT |
| 5.834 | 0.000 | tNET | RR | 2 | fifo_inst/n684_s0/CIN |
| 5.884 | 0.050 | tINS | RR | 1 | fifo_inst/n684_s0/COUT |
| 5.884 | 0.000 | tNET | RR | 2 | fifo_inst/n685_s0/CIN |
| 5.934 | 0.050 | tINS | RR | 1 | fifo_inst/n685_s0/COUT |
| 5.934 | 0.000 | tNET | RR | 2 | fifo_inst/n686_s0/CIN |
| 5.984 | 0.050 | tINS | RR | 2 | fifo_inst/n686_s0/COUT |
| 6.396 | 0.413 | tNET | RR | 1 | fifo_inst/n37_s1/I2 |
| 6.904 | 0.507 | tINS | RR | 4 | fifo_inst/n37_s1/F |
| 7.316 | 0.413 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_0_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_0_s/CLKB |
| 10.321 | -0.091 | tSu | 1 | fifo_inst/Small.mem_Small.mem_0_0_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.634, 52.635%; route: 2.887, 41.825%; tC2Q: 0.382, 5.540% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |