Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_usb\acm2108_ddr3_usb\src\wr_data_fifo\temp\FIFO\fifo_define.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_usb\acm2108_ddr3_usb\src\wr_data_fifo\temp\FIFO\fifo_parameter.v D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\edc.v D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo.v D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.03 (64-bit) |
| Part Number | GW5AT-LV138PG484AC1/I0 |
| Device | GW5AT-138 |
| Device Version | B |
| Created Time | Tue Sep 9 13:34:14 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | wr_data_fifo |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.375s, Peak memory usage = 77.129MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 77.129MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 77.129MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 77.129MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 77.129MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 77.129MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 77.129MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.129MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 77.129MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 77.129MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.129MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.129MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.352s, Peak memory usage = 92.535MB Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 92.535MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 92.535MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.67s, Elapsed time = 0h 0m 0.769s, Peak memory usage = 92.535MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 176 |
| I/O Buf | 176 |
| IBUF | 21 |
| OBUF | 155 |
| Register | 112 |
| DFFPE | 6 |
| DFFCE | 106 |
| LUT | 93 |
| LUT2 | 21 |
| LUT3 | 28 |
| LUT4 | 44 |
| ALU | 30 |
| ALU | 30 |
| INV | 3 |
| INV | 3 |
| BSRAM | 4 |
| SDPB | 4 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 126(96 LUT, 30 ALU) / 138240 | <1% |
| Register | 112 / 139095 | <1% |
| --Register as Latch | 0 / 139095 | 0% |
| --Register as FF | 112 / 139095 | <1% |
| BSRAM | 4 / 340 | 2% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | RdClk | Base | 10.000 | 100.000 | 0.000 | 5.000 | RdClk_ibuf/I | ||
| 2 | WrClk | Base | 10.000 | 100.000 | 0.000 | 5.000 | WrClk_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | RdClk | 100.000(MHz) | 127.186(MHz) | 9 | TOP |
| 2 | WrClk | 100.000(MHz) | 135.341(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 2.137 |
| Data Arrival Time | 8.211 |
| Data Required Time | 10.349 |
| From | fifo_inst/Big.rq2_wptr_6_s0 |
| To | fifo_inst/Almost_Empty_s0 |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 57 | RdClk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | fifo_inst/Big.rq2_wptr_6_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 2 | fifo_inst/Big.rq2_wptr_6_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | fifo_inst/Big.wcount_r_6_s1/I0 |
| 1.786 | 0.579 | tINS | RR | 3 | fifo_inst/Big.wcount_r_6_s1/F |
| 2.199 | 0.413 | tNET | RR | 1 | fifo_inst/Big.wcount_r_5_s0/I1 |
| 2.766 | 0.567 | tINS | RR | 2 | fifo_inst/Big.wcount_r_5_s0/F |
| 3.179 | 0.413 | tNET | RR | 1 | fifo_inst/Big.wcount_r_4_s0/I1 |
| 3.746 | 0.567 | tINS | RR | 1 | fifo_inst/Big.wcount_r_4_s0/F |
| 4.159 | 0.413 | tNET | RR | 2 | fifo_inst/rcnt_sub_4_s/I0 |
| 4.754 | 0.595 | tINS | RF | 1 | fifo_inst/rcnt_sub_4_s/COUT |
| 4.754 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_5_s/CIN |
| 4.804 | 0.050 | tINS | FR | 1 | fifo_inst/rcnt_sub_5_s/COUT |
| 4.804 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_6_s/CIN |
| 4.854 | 0.050 | tINS | RR | 1 | fifo_inst/rcnt_sub_6_s/COUT |
| 4.854 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_7_s/CIN |
| 4.904 | 0.050 | tINS | RR | 1 | fifo_inst/rcnt_sub_7_s/COUT |
| 4.904 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_8_s/CIN |
| 4.954 | 0.050 | tINS | RR | 1 | fifo_inst/rcnt_sub_8_s/COUT |
| 4.954 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_9_s/CIN |
| 5.198 | 0.244 | tINS | RR | 2 | fifo_inst/rcnt_sub_9_s/SUM |
| 5.610 | 0.413 | tNET | RR | 1 | fifo_inst/arempty_val_s2/I1 |
| 6.178 | 0.567 | tINS | RR | 1 | fifo_inst/arempty_val_s2/F |
| 6.590 | 0.413 | tNET | RR | 1 | fifo_inst/arempty_val_s1/I2 |
| 7.098 | 0.507 | tINS | RR | 1 | fifo_inst/arempty_val_s1/F |
| 7.510 | 0.413 | tNET | RR | 1 | fifo_inst/arempty_val_s0/I3 |
| 7.799 | 0.289 | tINS | RR | 1 | fifo_inst/arempty_val_s0/F |
| 8.211 | 0.413 | tNET | RR | 1 | fifo_inst/Almost_Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 57 | RdClk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_inst/Almost_Empty_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | fifo_inst/Almost_Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.116, 52.781%; route: 3.300, 42.314%; tC2Q: 0.382, 4.905% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 2.611 |
| Data Arrival Time | 7.738 |
| Data Required Time | 10.349 |
| From | fifo_inst/Big.wq2_rptr_6_s0 |
| To | fifo_inst/Almost_Full_s0 |
| Launch Clk | WrClk[R] |
| Latch Clk | WrClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | WrClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 63 | WrClk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | fifo_inst/Big.wq2_rptr_6_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 2 | fifo_inst/Big.wq2_rptr_6_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | fifo_inst/Big.rcount_w_1_9_s1/I0 |
| 1.786 | 0.579 | tINS | RR | 4 | fifo_inst/Big.rcount_w_1_9_s1/F |
| 2.199 | 0.413 | tNET | RR | 1 | fifo_inst/Big.rcount_w_1_6_s0/I3 |
| 2.487 | 0.289 | tINS | RR | 4 | fifo_inst/Big.rcount_w_1_6_s0/F |
| 2.900 | 0.413 | tNET | RR | 1 | fifo_inst/Big.rcount_w_1_5_s0/I1 |
| 3.468 | 0.567 | tINS | RR | 1 | fifo_inst/Big.rcount_w_1_5_s0/F |
| 3.880 | 0.413 | tNET | RR | 2 | fifo_inst/wcnt_sub_5_s/I1 |
| 4.480 | 0.600 | tINS | RF | 1 | fifo_inst/wcnt_sub_5_s/COUT |
| 4.480 | 0.000 | tNET | FF | 2 | fifo_inst/wcnt_sub_6_s/CIN |
| 4.724 | 0.244 | tINS | FR | 2 | fifo_inst/wcnt_sub_6_s/SUM |
| 5.136 | 0.413 | tNET | RR | 1 | fifo_inst/awfull_val_s3/I1 |
| 5.704 | 0.567 | tINS | RR | 1 | fifo_inst/awfull_val_s3/F |
| 6.116 | 0.413 | tNET | RR | 1 | fifo_inst/awfull_val_s2/I2 |
| 6.624 | 0.507 | tINS | RR | 1 | fifo_inst/awfull_val_s2/F |
| 7.036 | 0.413 | tNET | RR | 1 | fifo_inst/awfull_val_s0/I3 |
| 7.325 | 0.289 | tINS | RR | 1 | fifo_inst/awfull_val_s0/F |
| 7.738 | 0.413 | tNET | RR | 1 | fifo_inst/Almost_Full_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | WrClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 63 | WrClk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_inst/Almost_Full_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | fifo_inst/Almost_Full_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.642, 49.727%; route: 3.300, 45.051%; tC2Q: 0.382, 5.222% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 3.510 |
| Data Arrival Time | 6.839 |
| Data Required Time | 10.349 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Empty_s0 |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 57 | RdClk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 6 | fifo_inst/Empty_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s5/I0 |
| 1.786 | 0.579 | tINS | RR | 7 | fifo_inst/rbin_num_next_2_s5/F |
| 2.199 | 0.413 | tNET | RR | 1 | fifo_inst/Big.rgraynext_5_s1/I3 |
| 2.487 | 0.289 | tINS | RR | 7 | fifo_inst/Big.rgraynext_5_s1/F |
| 2.900 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_7_s4/I2 |
| 3.408 | 0.507 | tINS | RR | 7 | fifo_inst/rbin_num_next_7_s4/F |
| 3.820 | 0.413 | tNET | RR | 1 | fifo_inst/Big.rgraynext_7_s0/I2 |
| 4.328 | 0.507 | tINS | RR | 2 | fifo_inst/Big.rgraynext_7_s0/F |
| 4.740 | 0.413 | tNET | RR | 2 | fifo_inst/n682_s0/I0 |
| 5.335 | 0.595 | tINS | RF | 1 | fifo_inst/n682_s0/COUT |
| 5.335 | 0.000 | tNET | FF | 2 | fifo_inst/n683_s0/CIN |
| 5.385 | 0.050 | tINS | FR | 1 | fifo_inst/n683_s0/COUT |
| 5.385 | 0.000 | tNET | RR | 2 | fifo_inst/n684_s0/CIN |
| 5.435 | 0.050 | tINS | RR | 2 | fifo_inst/n684_s0/COUT |
| 5.848 | 0.413 | tNET | RR | 1 | fifo_inst/rempty_val_s1/I0 |
| 6.426 | 0.579 | tINS | RR | 1 | fifo_inst/rempty_val_s1/F |
| 6.839 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 57 | RdClk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | fifo_inst/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.156, 49.115%; route: 2.887, 44.933%; tC2Q: 0.382, 5.952% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 3.554 |
| Data Arrival Time | 6.768 |
| Data Required Time | 10.321 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Big.mem_Big.mem_0_3_s |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 57 | RdClk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 6 | fifo_inst/Empty_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s5/I0 |
| 1.786 | 0.579 | tINS | RR | 7 | fifo_inst/rbin_num_next_2_s5/F |
| 2.199 | 0.413 | tNET | RR | 1 | fifo_inst/Big.rgraynext_5_s1/I3 |
| 2.487 | 0.289 | tINS | RR | 7 | fifo_inst/Big.rgraynext_5_s1/F |
| 2.900 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_7_s4/I2 |
| 3.408 | 0.507 | tINS | RR | 7 | fifo_inst/rbin_num_next_7_s4/F |
| 3.820 | 0.413 | tNET | RR | 1 | fifo_inst/Big.rgraynext_7_s0/I2 |
| 4.328 | 0.507 | tINS | RR | 2 | fifo_inst/Big.rgraynext_7_s0/F |
| 4.740 | 0.413 | tNET | RR | 2 | fifo_inst/n682_s0/I0 |
| 5.335 | 0.595 | tINS | RF | 1 | fifo_inst/n682_s0/COUT |
| 5.335 | 0.000 | tNET | FF | 2 | fifo_inst/n683_s0/CIN |
| 5.385 | 0.050 | tINS | FR | 1 | fifo_inst/n683_s0/COUT |
| 5.385 | 0.000 | tNET | RR | 2 | fifo_inst/n684_s0/CIN |
| 5.435 | 0.050 | tINS | RR | 2 | fifo_inst/n684_s0/COUT |
| 5.848 | 0.413 | tNET | RR | 1 | fifo_inst/n34_s1/I2 |
| 6.355 | 0.507 | tINS | RR | 4 | fifo_inst/n34_s1/F |
| 6.768 | 0.413 | tNET | RR | 1 | fifo_inst/Big.mem_Big.mem_0_3_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 57 | RdClk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_inst/Big.mem_Big.mem_0_3_s/CLKB |
| 10.321 | -0.091 | tSu | 1 | fifo_inst/Big.mem_Big.mem_0_3_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.085, 48.544%; route: 2.887, 45.437%; tC2Q: 0.382, 6.019% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 3.554 |
| Data Arrival Time | 6.768 |
| Data Required Time | 10.321 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Big.mem_Big.mem_0_2_s |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 57 | RdClk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 6 | fifo_inst/Empty_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s5/I0 |
| 1.786 | 0.579 | tINS | RR | 7 | fifo_inst/rbin_num_next_2_s5/F |
| 2.199 | 0.413 | tNET | RR | 1 | fifo_inst/Big.rgraynext_5_s1/I3 |
| 2.487 | 0.289 | tINS | RR | 7 | fifo_inst/Big.rgraynext_5_s1/F |
| 2.900 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_7_s4/I2 |
| 3.408 | 0.507 | tINS | RR | 7 | fifo_inst/rbin_num_next_7_s4/F |
| 3.820 | 0.413 | tNET | RR | 1 | fifo_inst/Big.rgraynext_7_s0/I2 |
| 4.328 | 0.507 | tINS | RR | 2 | fifo_inst/Big.rgraynext_7_s0/F |
| 4.740 | 0.413 | tNET | RR | 2 | fifo_inst/n682_s0/I0 |
| 5.335 | 0.595 | tINS | RF | 1 | fifo_inst/n682_s0/COUT |
| 5.335 | 0.000 | tNET | FF | 2 | fifo_inst/n683_s0/CIN |
| 5.385 | 0.050 | tINS | FR | 1 | fifo_inst/n683_s0/COUT |
| 5.385 | 0.000 | tNET | RR | 2 | fifo_inst/n684_s0/CIN |
| 5.435 | 0.050 | tINS | RR | 2 | fifo_inst/n684_s0/COUT |
| 5.848 | 0.413 | tNET | RR | 1 | fifo_inst/n34_s1/I2 |
| 6.355 | 0.507 | tINS | RR | 4 | fifo_inst/n34_s1/F |
| 6.768 | 0.413 | tNET | RR | 1 | fifo_inst/Big.mem_Big.mem_0_2_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 57 | RdClk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_inst/Big.mem_Big.mem_0_2_s/CLKB |
| 10.321 | -0.091 | tSu | 1 | fifo_inst/Big.mem_Big.mem_0_2_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.085, 48.544%; route: 2.887, 45.437%; tC2Q: 0.382, 6.019% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |