Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\ACM2108\DDS_Module.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\ACM2108\acm2108_test.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\ACM2108\key_filter.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\ACM2108\sin_rom_a8d8.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\ACM2108\square_wave_rom_a8d8.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\ACM2108\triangular_rom_a8d8.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\FX2_CDC_Loopback.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\SPI_Slave.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\acm2108_ddr3_CDC.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\ad_8bit_to_16bit.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\cdc_cmd.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\cmd_ctrl.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\ddr3_ctrl_2port\ddr3_ctrl_2port.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\ddr3_ctrl_2port\fifo_ddr3_adapter.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\ddr3_memory_interface\ddr3_memory_interface.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\ddr_pll\ddr_pll.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\ddr_pll\ddr_pll_mod.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\fifo_in\fifo_in.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\fifo_top\fifo_top.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\gowin_pll\gowin_pll.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\gowin_pll\gowin_pll_mod.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\hc595_driver.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\hex8.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\pll_init.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\rd_data_fifo\rd_data_fifo.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\speed_ctrl.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\state_ctrl.v C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\wr_data_fifo\wr_data_fifo.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.03 (64-bit) |
| Part Number | GW5AT-LV138PG484AC1/I0 |
| Device | GW5AT-138 |
| Device Version | B |
| Created Time | Tue Sep 16 13:50:16 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | acm2108_ddr3_CDC |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.914s, Peak memory usage = 223.391MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.199s, Peak memory usage = 223.391MB Optimizing Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.156s, Peak memory usage = 223.391MB Optimizing Phase 2: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.299s, Peak memory usage = 223.391MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.2s, Peak memory usage = 223.391MB Inferring Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 223.391MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 223.391MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 223.391MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.382s, Peak memory usage = 223.391MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.117s, Peak memory usage = 223.391MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 223.391MB Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 236.430MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.399s, Peak memory usage = 236.430MB Generate output files: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.464s, Peak memory usage = 265.520MB |
| Total Time and Memory Usage | CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 265.520MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 114 |
| I/O Buf | 111 |
| IBUF | 26 |
| OBUF | 56 |
| TBUF | 2 |
| IOBUF | 24 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 5139 |
| DFFSE | 1 |
| DFFRE | 914 |
| DFFPE | 107 |
| DFFCE | 4117 |
| LUT | 4349 |
| LUT2 | 573 |
| LUT3 | 1798 |
| LUT4 | 1978 |
| ALU | 374 |
| ALU | 374 |
| INV | 47 |
| INV | 47 |
| IOLOGIC | 76 |
| IDES8_MEM | 16 |
| OSER8 | 24 |
| OSER8_MEM | 20 |
| IODELAY | 16 |
| BSRAM | 22 |
| SDPB | 17 |
| SDPX9B | 4 |
| pROM | 1 |
| CLOCK | 6 |
| PLL | 2 |
| CLKDIV | 1 |
| DQS | 2 |
| DDRDLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 4770(4396 LUT, 374 ALU) / 138240 | 4% |
| Register | 5139 / 139095 | 4% |
| --Register as Latch | 0 / 139095 | 0% |
| --Register as FF | 5139 / 139095 | 4% |
| BSRAM | 22 / 340 | 7% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | fx2_ifclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | fx2_ifclk_ibuf/I | ||
| 3 | SPI_SCLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | SPI_SCLK_ibuf/I | ||
| 4 | FX2_CDC_Loopback/hex8/clk_1K | Base | 10.000 | 100.000 | 0.000 | 5.000 | FX2_CDC_Loopback/hex8/clk_1K_s1/Q | ||
| 5 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk | Generated | 8.000 | 125.000 | 0.000 | 4.000 | clk_ibuf/I | clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT0 |
| 6 | Gowin_PLL/u_pll/PLL_inst/CLKOUT1.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT1 |
| 7 | ddr_pll/u_pll/PLL_inst/CLKOUT2.default_gen_clk | Generated | 2.500 | 400.000 | 0.000 | 1.250 | clk_ibuf/I | clk | ddr_pll/u_pll/PLL_inst/CLKOUT2 |
| 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | ddr_pll/u_pll/PLL_inst/CLKOUT2 | ddr_pll/u_pll/PLL_inst/CLKOUT2.default_gen_clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 110.803(MHz) | 9 | TOP |
| 2 | fx2_ifclk | 100.000(MHz) | 107.802(MHz) | 11 | TOP |
| 3 | SPI_SCLK | 100.000(MHz) | 266.134(MHz) | 4 | TOP |
| 4 | FX2_CDC_Loopback/hex8/clk_1K | 100.000(MHz) | 361.011(MHz) | 3 | TOP |
| 5 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk | 125.000(MHz) | 174.178(MHz) | 6 | TOP |
| 6 | ddr_pll/u_pll/PLL_inst/CLKOUT2.default_gen_clk | 400.000(MHz) | 1115.449(MHz) | 1 | TOP |
| 7 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 100.000(MHz) | 161.225(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -1.478 |
| Data Arrival Time | 26.092 |
| Data Required Time | 24.614 |
| From | acm2108_test/MODE_0_s1 |
| To | acm2108_test/DDS_Module/DA_Data_0_s1 |
| Launch Clk | clk[R] |
| Latch Clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 715 | clk_ibuf/O |
| 20.413 | 0.413 | tNET | RR | 1 | acm2108_test/MODE_0_s1/CLK |
| 20.795 | 0.382 | tC2Q | RR | 38 | acm2108_test/MODE_0_s1/Q |
| 21.208 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n81_s37/I2 |
| 21.715 | 0.507 | tINS | RR | 2 | acm2108_test/DDS_Module/n81_s37/F |
| 22.128 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n81_s34/I0 |
| 22.706 | 0.579 | tINS | RR | 2 | acm2108_test/DDS_Module/n81_s34/F |
| 23.119 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n81_s41/I0 |
| 23.698 | 0.579 | tINS | RR | 1 | acm2108_test/DDS_Module/n81_s41/F |
| 24.110 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n81_s42/I0 |
| 24.689 | 0.579 | tINS | RR | 1 | acm2108_test/DDS_Module/n81_s42/F |
| 25.101 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n81_s38/I0 |
| 25.680 | 0.579 | tINS | RR | 1 | acm2108_test/DDS_Module/n81_s38/F |
| 26.093 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 24.000 | 0.000 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 24.300 | 0.300 | tCL | RR | 66 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0 |
| 24.713 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_0_s1/CLK |
| 24.678 | -0.035 | tUnc | acm2108_test/DDS_Module/DA_Data_0_s1 | ||
| 24.614 | -0.064 | tSu | 1 | acm2108_test/DDS_Module/DA_Data_0_s1 |
| Clock Skew: | 0.300 |
| Setup Relationship: | 4.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.823, 49.692%; route: 2.475, 43.574%; tC2Q: 0.382, 6.734% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | -1.478 |
| Data Arrival Time | 26.092 |
| Data Required Time | 24.614 |
| From | acm2108_test/MODE_0_s1 |
| To | acm2108_test/DDS_Module/DA_Data_1_s1 |
| Launch Clk | clk[R] |
| Latch Clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 715 | clk_ibuf/O |
| 20.413 | 0.413 | tNET | RR | 1 | acm2108_test/MODE_0_s1/CLK |
| 20.795 | 0.382 | tC2Q | RR | 38 | acm2108_test/MODE_0_s1/Q |
| 21.208 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n80_s37/I2 |
| 21.715 | 0.507 | tINS | RR | 2 | acm2108_test/DDS_Module/n80_s37/F |
| 22.128 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n80_s34/I0 |
| 22.706 | 0.579 | tINS | RR | 2 | acm2108_test/DDS_Module/n80_s34/F |
| 23.119 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n80_s41/I0 |
| 23.698 | 0.579 | tINS | RR | 1 | acm2108_test/DDS_Module/n80_s41/F |
| 24.110 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n80_s42/I0 |
| 24.689 | 0.579 | tINS | RR | 1 | acm2108_test/DDS_Module/n80_s42/F |
| 25.101 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n80_s38/I0 |
| 25.680 | 0.579 | tINS | RR | 1 | acm2108_test/DDS_Module/n80_s38/F |
| 26.093 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 24.000 | 0.000 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 24.300 | 0.300 | tCL | RR | 66 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0 |
| 24.713 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_1_s1/CLK |
| 24.678 | -0.035 | tUnc | acm2108_test/DDS_Module/DA_Data_1_s1 | ||
| 24.614 | -0.064 | tSu | 1 | acm2108_test/DDS_Module/DA_Data_1_s1 |
| Clock Skew: | 0.300 |
| Setup Relationship: | 4.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.823, 49.692%; route: 2.475, 43.574%; tC2Q: 0.382, 6.734% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | -1.478 |
| Data Arrival Time | 26.092 |
| Data Required Time | 24.614 |
| From | acm2108_test/MODE_0_s1 |
| To | acm2108_test/DDS_Module/DA_Data_2_s1 |
| Launch Clk | clk[R] |
| Latch Clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 715 | clk_ibuf/O |
| 20.413 | 0.413 | tNET | RR | 1 | acm2108_test/MODE_0_s1/CLK |
| 20.795 | 0.382 | tC2Q | RR | 38 | acm2108_test/MODE_0_s1/Q |
| 21.208 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n79_s37/I2 |
| 21.715 | 0.507 | tINS | RR | 2 | acm2108_test/DDS_Module/n79_s37/F |
| 22.128 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n79_s34/I0 |
| 22.706 | 0.579 | tINS | RR | 2 | acm2108_test/DDS_Module/n79_s34/F |
| 23.119 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n79_s41/I0 |
| 23.698 | 0.579 | tINS | RR | 1 | acm2108_test/DDS_Module/n79_s41/F |
| 24.110 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n79_s42/I0 |
| 24.689 | 0.579 | tINS | RR | 1 | acm2108_test/DDS_Module/n79_s42/F |
| 25.101 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n79_s38/I0 |
| 25.680 | 0.579 | tINS | RR | 1 | acm2108_test/DDS_Module/n79_s38/F |
| 26.093 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 24.000 | 0.000 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 24.300 | 0.300 | tCL | RR | 66 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0 |
| 24.713 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_2_s1/CLK |
| 24.678 | -0.035 | tUnc | acm2108_test/DDS_Module/DA_Data_2_s1 | ||
| 24.614 | -0.064 | tSu | 1 | acm2108_test/DDS_Module/DA_Data_2_s1 |
| Clock Skew: | 0.300 |
| Setup Relationship: | 4.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.823, 49.692%; route: 2.475, 43.574%; tC2Q: 0.382, 6.734% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | -1.478 |
| Data Arrival Time | 26.092 |
| Data Required Time | 24.614 |
| From | acm2108_test/MODE_0_s1 |
| To | acm2108_test/DDS_Module/DA_Data_3_s1 |
| Launch Clk | clk[R] |
| Latch Clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 715 | clk_ibuf/O |
| 20.413 | 0.413 | tNET | RR | 1 | acm2108_test/MODE_0_s1/CLK |
| 20.795 | 0.382 | tC2Q | RR | 38 | acm2108_test/MODE_0_s1/Q |
| 21.208 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n78_s37/I2 |
| 21.715 | 0.507 | tINS | RR | 2 | acm2108_test/DDS_Module/n78_s37/F |
| 22.128 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n78_s34/I0 |
| 22.706 | 0.579 | tINS | RR | 2 | acm2108_test/DDS_Module/n78_s34/F |
| 23.119 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n78_s41/I0 |
| 23.698 | 0.579 | tINS | RR | 1 | acm2108_test/DDS_Module/n78_s41/F |
| 24.110 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n78_s42/I0 |
| 24.689 | 0.579 | tINS | RR | 1 | acm2108_test/DDS_Module/n78_s42/F |
| 25.101 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n78_s38/I0 |
| 25.680 | 0.579 | tINS | RR | 1 | acm2108_test/DDS_Module/n78_s38/F |
| 26.093 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 24.000 | 0.000 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 24.300 | 0.300 | tCL | RR | 66 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0 |
| 24.713 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_3_s1/CLK |
| 24.678 | -0.035 | tUnc | acm2108_test/DDS_Module/DA_Data_3_s1 | ||
| 24.614 | -0.064 | tSu | 1 | acm2108_test/DDS_Module/DA_Data_3_s1 |
| Clock Skew: | 0.300 |
| Setup Relationship: | 4.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.823, 49.692%; route: 2.475, 43.574%; tC2Q: 0.382, 6.734% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | -1.478 |
| Data Arrival Time | 26.092 |
| Data Required Time | 24.614 |
| From | acm2108_test/MODE_0_s1 |
| To | acm2108_test/DDS_Module/DA_Data_4_s1 |
| Launch Clk | clk[R] |
| Latch Clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 715 | clk_ibuf/O |
| 20.413 | 0.413 | tNET | RR | 1 | acm2108_test/MODE_0_s1/CLK |
| 20.795 | 0.382 | tC2Q | RR | 38 | acm2108_test/MODE_0_s1/Q |
| 21.208 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n77_s37/I2 |
| 21.715 | 0.507 | tINS | RR | 2 | acm2108_test/DDS_Module/n77_s37/F |
| 22.128 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n77_s34/I0 |
| 22.706 | 0.579 | tINS | RR | 2 | acm2108_test/DDS_Module/n77_s34/F |
| 23.119 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n77_s41/I0 |
| 23.698 | 0.579 | tINS | RR | 1 | acm2108_test/DDS_Module/n77_s41/F |
| 24.110 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n77_s42/I0 |
| 24.689 | 0.579 | tINS | RR | 1 | acm2108_test/DDS_Module/n77_s42/F |
| 25.101 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/n77_s38/I0 |
| 25.680 | 0.579 | tINS | RR | 1 | acm2108_test/DDS_Module/n77_s38/F |
| 26.093 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_4_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 24.000 | 0.000 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 24.300 | 0.300 | tCL | RR | 66 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0 |
| 24.713 | 0.413 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_4_s1/CLK |
| 24.678 | -0.035 | tUnc | acm2108_test/DDS_Module/DA_Data_4_s1 | ||
| 24.614 | -0.064 | tSu | 1 | acm2108_test/DDS_Module/DA_Data_4_s1 |
| Clock Skew: | 0.300 |
| Setup Relationship: | 4.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.823, 49.692%; route: 2.475, 43.574%; tC2Q: 0.382, 6.734% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |