Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\fifo_top\temp\FIFO\fifo_define.v
C:\Users\24165\Desktop\acg720_138_acm2108_108_ddr3_CDC\acm2108_ddr3_CDC\src\fifo_top\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW5AT-LV138PG484AC1/I0
Device GW5AT-138
Device Version B
Created Time Fri Sep 12 14:57:26 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.328s, Peak memory usage = 76.520MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.520MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.520MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.520MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 76.520MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.520MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.520MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.520MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.520MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 76.520MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.520MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.520MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.333s, Peak memory usage = 91.613MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 91.613MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 91.613MB
Total Time and Memory Usage CPU time = 0h 0m 0.638s, Elapsed time = 0h 0m 0.695s, Peak memory usage = 91.613MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 46
I/O Buf 46
    IBUF 21
    OBUF 25
Register 124
    DFFPE 6
    DFFCE 118
LUT 112
    LUT2 25
    LUT3 42
    LUT4 45
ALU 26
    ALU 26
INV 4
    INV 4
BSRAM 4
    SDPB 4

Resource Utilization Summary

Resource Usage Utilization
Logic 142(116 LUT, 26 ALU) / 138240 <1%
Register 124 / 139095 <1%
  --Register as Latch 0 / 139095 0%
  --Register as FF 124 / 139095 <1%
BSRAM 4 / 340 2%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 107.802(MHz) 11 TOP
2 WrClk 100.000(MHz) 172.302(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.724
Data Arrival Time 9.625
Data Required Time 10.349
From fifo_inst/Small.rq2_wptr_12_s0
To fifo_inst/Almost_Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 74 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Small.rq2_wptr_12_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Small.rq2_wptr_12_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/Small.wcount_r_1_10_s0/I0
1.786 0.579 tINS RR 4 fifo_inst/Small.wcount_r_1_10_s0/F
2.199 0.413 tNET RR 1 fifo_inst/Small.wcount_r_1_7_s0/I0
2.778 0.579 tINS RR 4 fifo_inst/Small.wcount_r_1_7_s0/F
3.190 0.413 tNET RR 1 fifo_inst/Small.wcount_r_1_5_s0/I0
3.769 0.579 tINS RR 2 fifo_inst/Small.wcount_r_1_5_s0/F
4.181 0.413 tNET RR 1 fifo_inst/Small.wcount_r_1_2_s0/I0
4.760 0.579 tINS RR 2 fifo_inst/Small.wcount_r_1_2_s0/F
5.173 0.413 tNET RR 1 fifo_inst/Small.wcount_r_1_1_s0/I0
5.751 0.579 tINS RR 1 fifo_inst/Small.wcount_r_1_1_s0/F
6.164 0.413 tNET RR 2 fifo_inst/rcnt_sub_1_s/I0
6.759 0.595 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
6.759 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
6.809 0.050 tINS FR 1 fifo_inst/rcnt_sub_2_s/COUT
6.809 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
6.859 0.050 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
6.859 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
6.909 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
6.909 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
6.959 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
6.959 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
7.009 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
7.009 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
7.253 0.244 tINS RR 2 fifo_inst/rcnt_sub_7_s/SUM
7.665 0.413 tNET RR 1 fifo_inst/arempty_val_s2/I1
8.233 0.567 tINS RR 1 fifo_inst/arempty_val_s2/F
8.645 0.413 tNET RR 1 fifo_inst/arempty_val_s0/I1
9.213 0.567 tINS RR 1 fifo_inst/arempty_val_s0/F
9.625 0.413 tNET RR 1 fifo_inst/Almost_Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 74 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Almost_Empty_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Almost_Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.118, 55.549%; route: 3.712, 40.299%; tC2Q: 0.382, 4.152%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 1.986
Data Arrival Time 8.363
Data Required Time 10.349
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 74 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.786 0.579 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.199 0.413 tNET RR 1 fifo_inst/rbin_num_next_5_s6/I0
2.778 0.579 tINS RR 10 fifo_inst/rbin_num_next_5_s6/F
3.190 0.413 tNET RR 1 fifo_inst/Small.rgraynext_5_s1/I0
3.769 0.579 tINS RR 1 fifo_inst/Small.rgraynext_5_s1/F
4.181 0.413 tNET RR 1 fifo_inst/Small.rgraynext_8_s1/I0
4.760 0.579 tINS RR 4 fifo_inst/Small.rgraynext_8_s1/F
5.173 0.413 tNET RR 1 fifo_inst/Small.rgraynext_8_s0/I0
5.751 0.579 tINS RR 2 fifo_inst/Small.rgraynext_8_s0/F
6.164 0.413 tNET RR 2 fifo_inst/n303_s0/I0
6.759 0.595 tINS RF 1 fifo_inst/n303_s0/COUT
6.759 0.000 tNET FF 2 fifo_inst/n304_s0/CIN
6.809 0.050 tINS FR 1 fifo_inst/n304_s0/COUT
6.809 0.000 tNET RR 2 fifo_inst/n305_s0/CIN
6.859 0.050 tINS RR 1 fifo_inst/n305_s0/COUT
6.859 0.000 tNET RR 2 fifo_inst/n306_s0/CIN
6.909 0.050 tINS RR 1 fifo_inst/n306_s0/COUT
6.909 0.000 tNET RR 2 fifo_inst/n307_s0/CIN
6.959 0.050 tINS RR 2 fifo_inst/n307_s0/COUT
7.371 0.413 tNET RR 1 fifo_inst/rempty_val_s1/I0
7.950 0.579 tINS RR 1 fifo_inst/rempty_val_s1/F
8.363 0.413 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 74 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.267, 53.680%; route: 3.300, 41.509%; tC2Q: 0.382, 4.811%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 2.030
Data Arrival Time 8.291
Data Required Time 10.321
From fifo_inst/Empty_s0
To fifo_inst/Small.mem_Small.mem_0_3_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 74 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.786 0.579 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.199 0.413 tNET RR 1 fifo_inst/rbin_num_next_5_s6/I0
2.778 0.579 tINS RR 10 fifo_inst/rbin_num_next_5_s6/F
3.190 0.413 tNET RR 1 fifo_inst/Small.rgraynext_5_s1/I0
3.769 0.579 tINS RR 1 fifo_inst/Small.rgraynext_5_s1/F
4.181 0.413 tNET RR 1 fifo_inst/Small.rgraynext_8_s1/I0
4.760 0.579 tINS RR 4 fifo_inst/Small.rgraynext_8_s1/F
5.173 0.413 tNET RR 1 fifo_inst/Small.rgraynext_8_s0/I0
5.751 0.579 tINS RR 2 fifo_inst/Small.rgraynext_8_s0/F
6.164 0.413 tNET RR 2 fifo_inst/n303_s0/I0
6.759 0.595 tINS RF 1 fifo_inst/n303_s0/COUT
6.759 0.000 tNET FF 2 fifo_inst/n304_s0/CIN
6.809 0.050 tINS FR 1 fifo_inst/n304_s0/COUT
6.809 0.000 tNET RR 2 fifo_inst/n305_s0/CIN
6.859 0.050 tINS RR 1 fifo_inst/n305_s0/COUT
6.859 0.000 tNET RR 2 fifo_inst/n306_s0/CIN
6.909 0.050 tINS RR 1 fifo_inst/n306_s0/COUT
6.909 0.000 tNET RR 2 fifo_inst/n307_s0/CIN
6.959 0.050 tINS RR 2 fifo_inst/n307_s0/COUT
7.371 0.413 tNET RR 1 fifo_inst/n38_s1/I2
7.879 0.507 tINS RR 4 fifo_inst/n38_s1/F
8.291 0.413 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_3_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 74 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_3_s/CLKB
10.321 -0.091 tSu 1 fifo_inst/Small.mem_Small.mem_0_3_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.196, 53.260%; route: 3.300, 41.885%; tC2Q: 0.382, 4.855%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 2.030
Data Arrival Time 8.291
Data Required Time 10.321
From fifo_inst/Empty_s0
To fifo_inst/Small.mem_Small.mem_0_2_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 74 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.786 0.579 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.199 0.413 tNET RR 1 fifo_inst/rbin_num_next_5_s6/I0
2.778 0.579 tINS RR 10 fifo_inst/rbin_num_next_5_s6/F
3.190 0.413 tNET RR 1 fifo_inst/Small.rgraynext_5_s1/I0
3.769 0.579 tINS RR 1 fifo_inst/Small.rgraynext_5_s1/F
4.181 0.413 tNET RR 1 fifo_inst/Small.rgraynext_8_s1/I0
4.760 0.579 tINS RR 4 fifo_inst/Small.rgraynext_8_s1/F
5.173 0.413 tNET RR 1 fifo_inst/Small.rgraynext_8_s0/I0
5.751 0.579 tINS RR 2 fifo_inst/Small.rgraynext_8_s0/F
6.164 0.413 tNET RR 2 fifo_inst/n303_s0/I0
6.759 0.595 tINS RF 1 fifo_inst/n303_s0/COUT
6.759 0.000 tNET FF 2 fifo_inst/n304_s0/CIN
6.809 0.050 tINS FR 1 fifo_inst/n304_s0/COUT
6.809 0.000 tNET RR 2 fifo_inst/n305_s0/CIN
6.859 0.050 tINS RR 1 fifo_inst/n305_s0/COUT
6.859 0.000 tNET RR 2 fifo_inst/n306_s0/CIN
6.909 0.050 tINS RR 1 fifo_inst/n306_s0/COUT
6.909 0.000 tNET RR 2 fifo_inst/n307_s0/CIN
6.959 0.050 tINS RR 2 fifo_inst/n307_s0/COUT
7.371 0.413 tNET RR 1 fifo_inst/n38_s1/I2
7.879 0.507 tINS RR 4 fifo_inst/n38_s1/F
8.291 0.413 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_2_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 74 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_2_s/CLKB
10.321 -0.091 tSu 1 fifo_inst/Small.mem_Small.mem_0_2_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.196, 53.260%; route: 3.300, 41.885%; tC2Q: 0.382, 4.855%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 2.030
Data Arrival Time 8.291
Data Required Time 10.321
From fifo_inst/Empty_s0
To fifo_inst/Small.mem_Small.mem_0_1_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 74 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.786 0.579 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.199 0.413 tNET RR 1 fifo_inst/rbin_num_next_5_s6/I0
2.778 0.579 tINS RR 10 fifo_inst/rbin_num_next_5_s6/F
3.190 0.413 tNET RR 1 fifo_inst/Small.rgraynext_5_s1/I0
3.769 0.579 tINS RR 1 fifo_inst/Small.rgraynext_5_s1/F
4.181 0.413 tNET RR 1 fifo_inst/Small.rgraynext_8_s1/I0
4.760 0.579 tINS RR 4 fifo_inst/Small.rgraynext_8_s1/F
5.173 0.413 tNET RR 1 fifo_inst/Small.rgraynext_8_s0/I0
5.751 0.579 tINS RR 2 fifo_inst/Small.rgraynext_8_s0/F
6.164 0.413 tNET RR 2 fifo_inst/n303_s0/I0
6.759 0.595 tINS RF 1 fifo_inst/n303_s0/COUT
6.759 0.000 tNET FF 2 fifo_inst/n304_s0/CIN
6.809 0.050 tINS FR 1 fifo_inst/n304_s0/COUT
6.809 0.000 tNET RR 2 fifo_inst/n305_s0/CIN
6.859 0.050 tINS RR 1 fifo_inst/n305_s0/COUT
6.859 0.000 tNET RR 2 fifo_inst/n306_s0/CIN
6.909 0.050 tINS RR 1 fifo_inst/n306_s0/COUT
6.909 0.000 tNET RR 2 fifo_inst/n307_s0/CIN
6.959 0.050 tINS RR 2 fifo_inst/n307_s0/COUT
7.371 0.413 tNET RR 1 fifo_inst/n38_s1/I2
7.879 0.507 tINS RR 4 fifo_inst/n38_s1/F
8.291 0.413 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_1_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 74 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_1_s/CLKB
10.321 -0.091 tSu 1 fifo_inst/Small.mem_Small.mem_0_1_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.196, 53.260%; route: 3.300, 41.885%; tC2Q: 0.382, 4.855%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%