Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\acm108_ddr3_usb\src\rd_data_fifo\temp\FIFO\fifo_define.v
C:\Users\24165\Desktop\acm108_ddr3_usb\src\rd_data_fifo\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW5AT-LV60PG484AC1/I0
Device GW5AT-60
Device Version B
Created Time Thu Sep 18 14:11:39 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module rd_data_fifo
Synthesis Process Running parser:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.333s, Peak memory usage = 77.383MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 77.383MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 77.383MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 77.383MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 77.383MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 77.383MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 77.383MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.383MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 77.383MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 77.383MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 77.383MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.383MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 94.648MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 94.648MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 94.648MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 94.648MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 176
I/O Buf 176
    IBUF 133
    OBUF 43
Register 95
    DFFPE 6
    DFFCE 89
LUT 345
    LUT2 36
    LUT3 86
    LUT4 223
ALU 32
    ALU 32
SSRAM 3
    RAM16S4 3
INV 5
    INV 5
BSRAM 4
    SDPB 4

Resource Utilization Summary

Resource Usage Utilization
Logic 400(350 LUT, 32 ALU, 3 RAM16) / 59904 <1%
Register 95 / 60780 <1%
  --Register as Latch 0 / 60780 0%
  --Register as FF 95 / 60780 <1%
BSRAM 4 / 118 4%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 113.782(MHz) 12 TOP
2 WrClk 100.000(MHz) 125.254(MHz) 11 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.211
Data Arrival Time 9.100
Data Required Time 10.311
From fifo_inst/Small.rq1_wptr_0_s2
To fifo_inst/Almost_Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 49 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Small.rq1_wptr_0_s2/CLK
0.757 0.382 tC2Q RR 9 fifo_inst/Small.rq1_wptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Small.rq1_wptr_0_s12/AD[0]
1.659 0.526 tINS RR 4 fifo_inst/Small.rq1_wptr_0_s12/DO[1]
2.034 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_10_s2/I0
2.560 0.526 tINS RR 1 fifo_inst/Small.wcount_r_1_10_s2/F
2.935 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_8_s0/I2
3.396 0.461 tINS RR 4 fifo_inst/Small.wcount_r_1_8_s0/F
3.771 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_4_s2/I3
4.034 0.262 tINS RR 2 fifo_inst/Small.wcount_r_1_4_s2/F
4.409 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_3_s1/I0
4.935 0.526 tINS RR 1 fifo_inst/Small.wcount_r_1_3_s1/F
5.310 0.375 tNET RR 2 fifo_inst/rcnt_sub_3_s/I0
5.866 0.556 tINS RF 1 fifo_inst/rcnt_sub_3_s/COUT
5.866 0.000 tNET FF 2 fifo_inst/rcnt_sub_4_s/CIN
5.916 0.050 tINS FR 1 fifo_inst/rcnt_sub_4_s/COUT
5.916 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.966 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.966 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
6.016 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
6.016 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
6.066 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
6.066 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
6.116 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
6.116 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
6.360 0.244 tINS RR 2 fifo_inst/rcnt_sub_9_s/SUM
6.735 0.375 tNET RR 1 fifo_inst/arempty_val_s3/I1
7.251 0.516 tINS RR 1 fifo_inst/arempty_val_s3/F
7.626 0.375 tNET RR 1 fifo_inst/arempty_val_s2/I2
8.088 0.461 tINS RR 1 fifo_inst/arempty_val_s2/F
8.463 0.375 tNET RR 1 fifo_inst/arempty_val_s0/I3
8.725 0.262 tINS RR 1 fifo_inst/arempty_val_s0/F
9.100 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 49 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Almost_Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.592, 52.636%; route: 3.750, 42.980%; tC2Q: 0.382, 4.384%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 2.016
Data Arrival Time 8.295
Data Required Time 10.311
From fifo_inst/Small.wq2_rptr_6_s0
To fifo_inst/Almost_Full_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 57 WrClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Small.wq2_rptr_6_s0/CLK
0.757 0.382 tC2Q RR 2 fifo_inst/Small.wq2_rptr_6_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/Small.rcount_w_6_s0/I0
1.659 0.526 tINS RR 4 fifo_inst/Small.rcount_w_6_s0/F
2.034 0.375 tNET RR 1 fifo_inst/Small.rcount_w_4_s0/I2
2.495 0.461 tINS RR 3 fifo_inst/Small.rcount_w_4_s0/F
2.870 0.375 tNET RR 1 fifo_inst/Small.rcount_w_1_s0/I3
3.133 0.262 tINS RR 2 fifo_inst/Small.rcount_w_1_s0/F
3.508 0.375 tNET RR 1 fifo_inst/Small.rcount_w_0_s0/I1
4.024 0.516 tINS RR 1 fifo_inst/Small.rcount_w_0_s0/F
4.399 0.375 tNET RR 2 fifo_inst/wcnt_sub_0_s/I1
4.961 0.562 tINS RF 1 fifo_inst/wcnt_sub_0_s/COUT
4.961 0.000 tNET FF 2 fifo_inst/wcnt_sub_1_s/CIN
5.011 0.050 tINS FR 1 fifo_inst/wcnt_sub_1_s/COUT
5.011 0.000 tNET RR 2 fifo_inst/wcnt_sub_2_s/CIN
5.061 0.050 tINS RR 1 fifo_inst/wcnt_sub_2_s/COUT
5.061 0.000 tNET RR 2 fifo_inst/wcnt_sub_3_s/CIN
5.111 0.050 tINS RR 1 fifo_inst/wcnt_sub_3_s/COUT
5.111 0.000 tNET RR 2 fifo_inst/wcnt_sub_4_s/CIN
5.161 0.050 tINS RR 1 fifo_inst/wcnt_sub_4_s/COUT
5.161 0.000 tNET RR 2 fifo_inst/wcnt_sub_5_s/CIN
5.211 0.050 tINS RR 1 fifo_inst/wcnt_sub_5_s/COUT
5.211 0.000 tNET RR 2 fifo_inst/wcnt_sub_6_s/CIN
5.261 0.050 tINS RR 1 fifo_inst/wcnt_sub_6_s/COUT
5.261 0.000 tNET RR 2 fifo_inst/wcnt_sub_7_s/CIN
5.311 0.050 tINS RR 1 fifo_inst/wcnt_sub_7_s/COUT
5.311 0.000 tNET RR 2 fifo_inst/wcnt_sub_8_s/CIN
5.555 0.244 tINS RR 2 fifo_inst/wcnt_sub_8_s/SUM
5.930 0.375 tNET RR 1 fifo_inst/awfull_val_s2/I1
6.446 0.516 tINS RR 1 fifo_inst/awfull_val_s2/F
6.821 0.375 tNET RR 1 fifo_inst/awfull_val_s1/I2
7.283 0.461 tINS RR 1 fifo_inst/awfull_val_s1/F
7.658 0.375 tNET RR 1 fifo_inst/awfull_val_s0/I3
7.920 0.262 tINS RR 1 fifo_inst/awfull_val_s0/F
8.295 0.375 tNET RR 1 fifo_inst/Almost_Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 57 WrClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Almost_Full_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Almost_Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.162, 52.556%; route: 3.375, 42.614%; tC2Q: 0.382, 4.830%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 3.426
Data Arrival Time 6.885
Data Required Time 10.311
From fifo_inst/Small.rq1_wptr_0_s2
To fifo_inst/Rnum_12_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 49 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Small.rq1_wptr_0_s2/CLK
0.757 0.382 tC2Q RR 9 fifo_inst/Small.rq1_wptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Small.rq1_wptr_0_s12/AD[0]
1.659 0.526 tINS RR 4 fifo_inst/Small.rq1_wptr_0_s12/DO[1]
2.034 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_10_s2/I0
2.560 0.526 tINS RR 1 fifo_inst/Small.wcount_r_1_10_s2/F
2.935 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_8_s0/I2
3.396 0.461 tINS RR 4 fifo_inst/Small.wcount_r_1_8_s0/F
3.771 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_4_s2/I3
4.034 0.262 tINS RR 2 fifo_inst/Small.wcount_r_1_4_s2/F
4.409 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_3_s1/I0
4.935 0.526 tINS RR 1 fifo_inst/Small.wcount_r_1_3_s1/F
5.310 0.375 tNET RR 2 fifo_inst/rcnt_sub_3_s/I0
5.866 0.556 tINS RF 1 fifo_inst/rcnt_sub_3_s/COUT
5.866 0.000 tNET FF 2 fifo_inst/rcnt_sub_4_s/CIN
5.916 0.050 tINS FR 1 fifo_inst/rcnt_sub_4_s/COUT
5.916 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.966 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.966 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
6.016 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
6.016 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
6.066 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
6.066 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
6.116 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
6.116 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
6.166 0.050 tINS RR 1 fifo_inst/rcnt_sub_9_s/COUT
6.166 0.000 tNET RR 2 fifo_inst/rcnt_sub_10_s/CIN
6.216 0.050 tINS RR 1 fifo_inst/rcnt_sub_10_s/COUT
6.216 0.000 tNET RR 2 fifo_inst/rcnt_sub_11_s/CIN
6.266 0.050 tINS RR 1 fifo_inst/rcnt_sub_11_s/COUT
6.266 0.000 tNET RR 2 fifo_inst/rcnt_sub_12_s/CIN
6.510 0.244 tINS RR 2 fifo_inst/rcnt_sub_12_s/SUM
6.885 0.375 tNET RR 1 fifo_inst/Rnum_12_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 49 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Rnum_12_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Rnum_12_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.502, 53.801%; route: 2.625, 40.323%; tC2Q: 0.382, 5.876%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 3.426
Data Arrival Time 6.885
Data Required Time 10.311
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 49 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 15 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s4/I0
1.659 0.526 tINS RR 11 fifo_inst/rbin_num_next_2_s4/F
2.034 0.375 tNET RR 1 fifo_inst/rbin_num_next_3_s6/I1
2.550 0.516 tINS RR 4 fifo_inst/rbin_num_next_3_s6/F
2.925 0.375 tNET RR 1 fifo_inst/rbin_num_next_5_s5/I2
3.386 0.461 tINS RR 7 fifo_inst/rbin_num_next_5_s5/F
3.761 0.375 tNET RR 1 fifo_inst/Small.rgraynext_1_s0/I1
4.278 0.516 tINS RR 2 fifo_inst/Small.rgraynext_1_s0/F
4.653 0.375 tNET RR 2 fifo_inst/n678_s0/I0
5.209 0.556 tINS RF 1 fifo_inst/n678_s0/COUT
5.209 0.000 tNET FF 2 fifo_inst/n679_s0/CIN
5.259 0.050 tINS FR 1 fifo_inst/n679_s0/COUT
5.259 0.000 tNET RR 2 fifo_inst/n680_s0/CIN
5.309 0.050 tINS RR 1 fifo_inst/n680_s0/COUT
5.309 0.000 tNET RR 2 fifo_inst/n681_s0/CIN
5.359 0.050 tINS RR 1 fifo_inst/n681_s0/COUT
5.359 0.000 tNET RR 2 fifo_inst/n682_s0/CIN
5.409 0.050 tINS RR 1 fifo_inst/n682_s0/COUT
5.409 0.000 tNET RR 2 fifo_inst/n683_s0/CIN
5.459 0.050 tINS RR 1 fifo_inst/n683_s0/COUT
5.459 0.000 tNET RR 2 fifo_inst/n684_s0/CIN
5.509 0.050 tINS RR 1 fifo_inst/n684_s0/COUT
5.509 0.000 tNET RR 2 fifo_inst/n685_s0/CIN
5.559 0.050 tINS RR 1 fifo_inst/n685_s0/COUT
5.559 0.000 tNET RR 2 fifo_inst/n686_s0/CIN
5.609 0.050 tINS RR 2 fifo_inst/n686_s0/COUT
5.984 0.375 tNET RR 1 fifo_inst/rempty_val_s1/I0
6.510 0.526 tINS RR 1 fifo_inst/rempty_val_s1/F
6.885 0.375 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 49 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.502, 53.801%; route: 2.625, 40.323%; tC2Q: 0.382, 5.876%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 3.464
Data Arrival Time 6.820
Data Required Time 10.284
From fifo_inst/Empty_s0
To fifo_inst/Small.mem_Small.mem_0_3_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 49 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 15 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s4/I0
1.659 0.526 tINS RR 11 fifo_inst/rbin_num_next_2_s4/F
2.034 0.375 tNET RR 1 fifo_inst/rbin_num_next_3_s6/I1
2.550 0.516 tINS RR 4 fifo_inst/rbin_num_next_3_s6/F
2.925 0.375 tNET RR 1 fifo_inst/rbin_num_next_5_s5/I2
3.386 0.461 tINS RR 7 fifo_inst/rbin_num_next_5_s5/F
3.761 0.375 tNET RR 1 fifo_inst/Small.rgraynext_1_s0/I1
4.278 0.516 tINS RR 2 fifo_inst/Small.rgraynext_1_s0/F
4.653 0.375 tNET RR 2 fifo_inst/n678_s0/I0
5.209 0.556 tINS RF 1 fifo_inst/n678_s0/COUT
5.209 0.000 tNET FF 2 fifo_inst/n679_s0/CIN
5.259 0.050 tINS FR 1 fifo_inst/n679_s0/COUT
5.259 0.000 tNET RR 2 fifo_inst/n680_s0/CIN
5.309 0.050 tINS RR 1 fifo_inst/n680_s0/COUT
5.309 0.000 tNET RR 2 fifo_inst/n681_s0/CIN
5.359 0.050 tINS RR 1 fifo_inst/n681_s0/COUT
5.359 0.000 tNET RR 2 fifo_inst/n682_s0/CIN
5.409 0.050 tINS RR 1 fifo_inst/n682_s0/COUT
5.409 0.000 tNET RR 2 fifo_inst/n683_s0/CIN
5.459 0.050 tINS RR 1 fifo_inst/n683_s0/COUT
5.459 0.000 tNET RR 2 fifo_inst/n684_s0/CIN
5.509 0.050 tINS RR 1 fifo_inst/n684_s0/COUT
5.509 0.000 tNET RR 2 fifo_inst/n685_s0/CIN
5.559 0.050 tINS RR 1 fifo_inst/n685_s0/COUT
5.559 0.000 tNET RR 2 fifo_inst/n686_s0/CIN
5.609 0.050 tINS RR 2 fifo_inst/n686_s0/COUT
5.984 0.375 tNET RR 1 fifo_inst/n37_s1/I2
6.445 0.461 tINS RR 4 fifo_inst/n37_s1/F
6.820 0.375 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_3_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 49 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_3_s/CLKB
10.284 -0.091 tSu 1 fifo_inst/Small.mem_Small.mem_0_3_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.437, 53.336%; route: 2.625, 40.729%; tC2Q: 0.382, 5.935%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%