Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\acm2108_ddr3_usb\src\fifo\temp\FIFO\fifo_define.v
C:\Users\24165\Desktop\acm2108_ddr3_usb\src\fifo\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW5AT-LV60PG484AC1/I0
Device GW5AT-60
Device Version B
Created Time Thu Sep 18 13:38:52 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo
Synthesis Process Running parser:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.329s, Peak memory usage = 76.875MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.875MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.875MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.875MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.875MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.875MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.875MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.875MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.875MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.875MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.875MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.875MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.386s, Peak memory usage = 91.656MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 91.656MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 91.656MB
Total Time and Memory Usage CPU time = 0h 0m 0.763s, Elapsed time = 0h 0m 0.784s, Peak memory usage = 91.656MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 50
I/O Buf 50
    IBUF 21
    OBUF 29
Register 84
    DFFPE 5
    DFFCE 79
LUT 105
    LUT2 27
    LUT3 33
    LUT4 45
ALU 21
    ALU 21
SSRAM 3
    RAM16S4 3
INV 3
    INV 3
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 147(108 LUT, 21 ALU, 3 RAM16) / 59904 <1%
Register 84 / 60780 <1%
  --Register as Latch 0 / 60780 0%
  --Register as FF 84 / 60780 <1%
BSRAM 1 / 118 <1%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 156.403(MHz) 8 TOP
2 WrClk 100.000(MHz) 225.925(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.606
Data Arrival Time 6.705
Data Required Time 10.311
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 42 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s4/I0
1.659 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s4/F
2.034 0.375 tNET RR 1 fifo_inst/rbin_num_next_5_s4/I0
2.560 0.526 tINS RR 7 fifo_inst/rbin_num_next_5_s4/F
2.935 0.375 tNET RR 1 fifo_inst/rbin_num_next_6_s3/I0
3.461 0.526 tINS RR 2 fifo_inst/rbin_num_next_6_s3/F
3.836 0.375 tNET RR 1 fifo_inst/Equal.rgraynext_5_s1/I2
4.297 0.461 tINS RR 2 fifo_inst/Equal.rgraynext_5_s1/F
4.672 0.375 tNET RR 2 fifo_inst/n138_s0/I0
5.229 0.556 tINS RF 1 fifo_inst/n138_s0/COUT
5.229 0.000 tNET FF 2 fifo_inst/n139_s0/CIN
5.279 0.050 tINS FR 1 fifo_inst/n139_s0/COUT
5.279 0.000 tNET RR 2 fifo_inst/n140_s0/CIN
5.329 0.050 tINS RR 1 fifo_inst/n140_s0/COUT
5.329 0.000 tNET RR 2 fifo_inst/n141_s0/CIN
5.379 0.050 tINS RR 1 fifo_inst/n141_s0/COUT
5.379 0.000 tNET RR 2 fifo_inst/n142_s0/CIN
5.429 0.050 tINS RR 1 fifo_inst/n142_s0/COUT
5.804 0.375 tNET RR 1 fifo_inst/rempty_val_s1/I0
6.330 0.526 tINS RR 1 fifo_inst/rempty_val_s1/F
6.705 0.375 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 42 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.322, 52.488%; route: 2.625, 41.469%; tC2Q: 0.382, 6.043%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 4.049
Data Arrival Time 6.263
Data Required Time 10.311
From fifo_inst/Equal.rq1_wptr_0_s2
To fifo_inst/Rnum_10_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 42 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Equal.rq1_wptr_0_s2/CLK
0.757 0.382 tC2Q RR 9 fifo_inst/Equal.rq1_wptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Equal.rq1_wptr_0_s12/AD[0]
1.659 0.526 tINS RR 4 fifo_inst/Equal.rq1_wptr_0_s12/DO[2]
2.034 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_8_s0/I0
2.560 0.526 tINS RR 7 fifo_inst/Equal.wcount_r_8_s0/F
2.935 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_4_s0/I0
3.461 0.526 tINS RR 2 fifo_inst/Equal.wcount_r_4_s0/F
3.836 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_2_s0/I0
4.362 0.526 tINS RR 1 fifo_inst/Equal.wcount_r_2_s0/F
4.737 0.375 tNET RR 2 fifo_inst/rcnt_sub_2_s/I0
5.294 0.556 tINS RF 1 fifo_inst/rcnt_sub_2_s/COUT
5.294 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
5.344 0.050 tINS FR 1 fifo_inst/rcnt_sub_3_s/COUT
5.344 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
5.394 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
5.394 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.444 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.444 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
5.494 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
5.494 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
5.544 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
5.544 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
5.594 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
5.594 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
5.644 0.050 tINS RR 1 fifo_inst/rcnt_sub_9_s/COUT
5.644 0.000 tNET RR 2 fifo_inst/rcnt_sub_10_s/CIN
5.888 0.244 tINS RR 1 fifo_inst/rcnt_sub_10_s/SUM
6.263 0.375 tNET RR 1 fifo_inst/Rnum_10_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 42 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Rnum_10_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Rnum_10_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.255, 55.286%; route: 2.250, 38.217%; tC2Q: 0.382, 6.497%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 4.099
Data Arrival Time 6.213
Data Required Time 10.311
From fifo_inst/Equal.rq1_wptr_0_s2
To fifo_inst/Rnum_9_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 42 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Equal.rq1_wptr_0_s2/CLK
0.757 0.382 tC2Q RR 9 fifo_inst/Equal.rq1_wptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Equal.rq1_wptr_0_s12/AD[0]
1.659 0.526 tINS RR 4 fifo_inst/Equal.rq1_wptr_0_s12/DO[2]
2.034 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_8_s0/I0
2.560 0.526 tINS RR 7 fifo_inst/Equal.wcount_r_8_s0/F
2.935 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_4_s0/I0
3.461 0.526 tINS RR 2 fifo_inst/Equal.wcount_r_4_s0/F
3.836 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_2_s0/I0
4.362 0.526 tINS RR 1 fifo_inst/Equal.wcount_r_2_s0/F
4.737 0.375 tNET RR 2 fifo_inst/rcnt_sub_2_s/I0
5.294 0.556 tINS RF 1 fifo_inst/rcnt_sub_2_s/COUT
5.294 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
5.344 0.050 tINS FR 1 fifo_inst/rcnt_sub_3_s/COUT
5.344 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
5.394 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
5.394 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.444 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.444 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
5.494 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
5.494 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
5.544 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
5.544 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
5.594 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
5.594 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
5.838 0.244 tINS RR 1 fifo_inst/rcnt_sub_9_s/SUM
6.213 0.375 tNET RR 1 fifo_inst/Rnum_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 42 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Rnum_9_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Rnum_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.205, 54.904%; route: 2.250, 38.544%; tC2Q: 0.382, 6.552%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 4.149
Data Arrival Time 6.162
Data Required Time 10.311
From fifo_inst/Equal.rq1_wptr_0_s2
To fifo_inst/Rnum_8_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 42 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Equal.rq1_wptr_0_s2/CLK
0.757 0.382 tC2Q RR 9 fifo_inst/Equal.rq1_wptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Equal.rq1_wptr_0_s12/AD[0]
1.659 0.526 tINS RR 4 fifo_inst/Equal.rq1_wptr_0_s12/DO[2]
2.034 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_8_s0/I0
2.560 0.526 tINS RR 7 fifo_inst/Equal.wcount_r_8_s0/F
2.935 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_4_s0/I0
3.461 0.526 tINS RR 2 fifo_inst/Equal.wcount_r_4_s0/F
3.836 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_2_s0/I0
4.362 0.526 tINS RR 1 fifo_inst/Equal.wcount_r_2_s0/F
4.737 0.375 tNET RR 2 fifo_inst/rcnt_sub_2_s/I0
5.294 0.556 tINS RF 1 fifo_inst/rcnt_sub_2_s/COUT
5.294 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
5.344 0.050 tINS FR 1 fifo_inst/rcnt_sub_3_s/COUT
5.344 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
5.394 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
5.394 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.444 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.444 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
5.494 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
5.494 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
5.544 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
5.544 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
5.788 0.244 tINS RR 1 fifo_inst/rcnt_sub_8_s/SUM
6.163 0.375 tNET RR 1 fifo_inst/Rnum_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 42 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Rnum_8_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Rnum_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.155, 54.514%; route: 2.250, 38.877%; tC2Q: 0.382, 6.609%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 4.199
Data Arrival Time 6.112
Data Required Time 10.311
From fifo_inst/Equal.rq1_wptr_0_s2
To fifo_inst/Rnum_7_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 42 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Equal.rq1_wptr_0_s2/CLK
0.757 0.382 tC2Q RR 9 fifo_inst/Equal.rq1_wptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Equal.rq1_wptr_0_s12/AD[0]
1.659 0.526 tINS RR 4 fifo_inst/Equal.rq1_wptr_0_s12/DO[2]
2.034 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_8_s0/I0
2.560 0.526 tINS RR 7 fifo_inst/Equal.wcount_r_8_s0/F
2.935 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_4_s0/I0
3.461 0.526 tINS RR 2 fifo_inst/Equal.wcount_r_4_s0/F
3.836 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_2_s0/I0
4.362 0.526 tINS RR 1 fifo_inst/Equal.wcount_r_2_s0/F
4.737 0.375 tNET RR 2 fifo_inst/rcnt_sub_2_s/I0
5.294 0.556 tINS RF 1 fifo_inst/rcnt_sub_2_s/COUT
5.294 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
5.344 0.050 tINS FR 1 fifo_inst/rcnt_sub_3_s/COUT
5.344 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
5.394 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
5.394 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.444 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.444 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
5.494 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
5.494 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
5.738 0.244 tINS RR 1 fifo_inst/rcnt_sub_7_s/SUM
6.113 0.375 tNET RR 1 fifo_inst/Rnum_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 42 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Rnum_7_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Rnum_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.105, 54.117%; route: 2.250, 39.216%; tC2Q: 0.382, 6.667%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%