Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\60k_acm2108_ddr3_usb\src\wr_data_fifo\temp\FIFO\fifo_define.v
C:\Users\24165\Desktop\60k_acm2108_ddr3_usb\src\wr_data_fifo\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW5AT-LV60PG484AC1/I0
Device GW5AT-60
Device Version B
Created Time Thu Sep 18 14:05:31 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module wr_data_fifo
Synthesis Process Running parser:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.331s, Peak memory usage = 77.301MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 77.301MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 77.301MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 77.301MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 77.301MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 77.301MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 77.301MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.301MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 77.301MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 77.301MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.301MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.301MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.401s, Peak memory usage = 92.871MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 92.871MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 92.871MB
Total Time and Memory Usage CPU time = 0h 0m 0.748s, Elapsed time = 0h 0m 0.775s, Peak memory usage = 92.871MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 176
I/O Buf 176
    IBUF 21
    OBUF 155
Register 95
    DFFPE 6
    DFFCE 89
LUT 110
    LUT2 20
    LUT3 41
    LUT4 49
ALU 30
    ALU 30
SSRAM 3
    RAM16S4 3
INV 4
    INV 4
BSRAM 4
    SDPB 4

Resource Utilization Summary

Resource Usage Utilization
Logic 162(114 LUT, 30 ALU, 3 RAM16) / 59904 <1%
Register 95 / 60780 <1%
  --Register as Latch 0 / 60780 0%
  --Register as FF 95 / 60780 <1%
BSRAM 4 / 118 4%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 117.233(MHz) 11 TOP
2 WrClk 100.000(MHz) 139.058(MHz) 10 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.470
Data Arrival Time 8.841
Data Required Time 10.311
From fifo_inst/Big.rq1_wptr_0_s2
To fifo_inst/Almost_Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 43 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Big.rq1_wptr_0_s2/CLK
0.757 0.382 tC2Q RR 9 fifo_inst/Big.rq1_wptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Big.rq1_wptr_0_s12/AD[0]
1.659 0.526 tINS RR 3 fifo_inst/Big.rq1_wptr_0_s12/DO[1]
2.034 0.375 tNET RR 1 fifo_inst/Big.wcount_r_7_s0/I0
2.560 0.526 tINS RR 2 fifo_inst/Big.wcount_r_7_s0/F
2.935 0.375 tNET RR 1 fifo_inst/Big.wcount_r_6_s1/I0
3.461 0.526 tINS RR 2 fifo_inst/Big.wcount_r_6_s1/F
3.836 0.375 tNET RR 1 fifo_inst/Big.wcount_r_5_s1/I0
4.362 0.526 tINS RR 6 fifo_inst/Big.wcount_r_5_s1/F
4.737 0.375 tNET RR 1 fifo_inst/Big.wcount_r_0_s0/I0
5.264 0.526 tINS RR 1 fifo_inst/Big.wcount_r_0_s0/F
5.639 0.375 tNET RR 2 fifo_inst/rcnt_sub_0_s/I0
6.195 0.556 tINS RF 1 fifo_inst/rcnt_sub_0_s/COUT
6.195 0.000 tNET FF 2 fifo_inst/rcnt_sub_1_s/CIN
6.245 0.050 tINS FR 1 fifo_inst/rcnt_sub_1_s/COUT
6.245 0.000 tNET RR 2 fifo_inst/rcnt_sub_2_s/CIN
6.295 0.050 tINS RR 1 fifo_inst/rcnt_sub_2_s/COUT
6.295 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
6.345 0.050 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
6.345 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
6.395 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
6.395 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
6.445 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
6.445 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
6.495 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
6.495 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
6.739 0.244 tINS RR 2 fifo_inst/rcnt_sub_7_s/SUM
7.114 0.375 tNET RR 1 fifo_inst/arempty_val_s2/I2
7.575 0.461 tINS RR 1 fifo_inst/arempty_val_s2/F
7.950 0.375 tNET RR 1 fifo_inst/arempty_val_s0/I1
8.466 0.516 tINS RR 1 fifo_inst/arempty_val_s0/F
8.841 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 43 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Almost_Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.709, 55.618%; route: 3.375, 39.864%; tC2Q: 0.382, 4.518%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 2.710
Data Arrival Time 7.601
Data Required Time 10.311
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 43 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 3 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_0_s4/I0
1.659 0.526 tINS RR 11 fifo_inst/rbin_num_next_0_s4/F
2.034 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s5/I0
2.560 0.526 tINS RR 5 fifo_inst/rbin_num_next_2_s5/F
2.935 0.375 tNET RR 1 fifo_inst/rbin_num_next_5_s6/I1
3.451 0.516 tINS RR 6 fifo_inst/rbin_num_next_5_s6/F
3.826 0.375 tNET RR 1 fifo_inst/rbin_num_next_6_s4/I1
4.343 0.516 tINS RR 7 fifo_inst/rbin_num_next_6_s4/F
4.718 0.375 tNET RR 1 fifo_inst/Big.rgraynext_6_s0/I0
5.244 0.526 tINS RR 2 fifo_inst/Big.rgraynext_6_s0/F
5.619 0.375 tNET RR 2 fifo_inst/n681_s0/I0
6.175 0.556 tINS RF 1 fifo_inst/n681_s0/COUT
6.175 0.000 tNET FF 2 fifo_inst/n682_s0/CIN
6.225 0.050 tINS FR 1 fifo_inst/n682_s0/COUT
6.225 0.000 tNET RR 2 fifo_inst/n683_s0/CIN
6.275 0.050 tINS RR 1 fifo_inst/n683_s0/COUT
6.275 0.000 tNET RR 2 fifo_inst/n684_s0/CIN
6.325 0.050 tINS RR 2 fifo_inst/n684_s0/COUT
6.700 0.375 tNET RR 1 fifo_inst/rempty_val_s1/I0
7.226 0.526 tINS RR 1 fifo_inst/rempty_val_s1/F
7.601 0.375 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 43 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.844, 53.192%; route: 3.000, 41.515%; tC2Q: 0.382, 5.293%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 2.747
Data Arrival Time 7.536
Data Required Time 10.284
From fifo_inst/Empty_s0
To fifo_inst/Big.mem_Big.mem_0_3_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 43 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 3 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_0_s4/I0
1.659 0.526 tINS RR 11 fifo_inst/rbin_num_next_0_s4/F
2.034 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s5/I0
2.560 0.526 tINS RR 5 fifo_inst/rbin_num_next_2_s5/F
2.935 0.375 tNET RR 1 fifo_inst/rbin_num_next_5_s6/I1
3.451 0.516 tINS RR 6 fifo_inst/rbin_num_next_5_s6/F
3.826 0.375 tNET RR 1 fifo_inst/rbin_num_next_6_s4/I1
4.343 0.516 tINS RR 7 fifo_inst/rbin_num_next_6_s4/F
4.718 0.375 tNET RR 1 fifo_inst/Big.rgraynext_6_s0/I0
5.244 0.526 tINS RR 2 fifo_inst/Big.rgraynext_6_s0/F
5.619 0.375 tNET RR 2 fifo_inst/n681_s0/I0
6.175 0.556 tINS RF 1 fifo_inst/n681_s0/COUT
6.175 0.000 tNET FF 2 fifo_inst/n682_s0/CIN
6.225 0.050 tINS FR 1 fifo_inst/n682_s0/COUT
6.225 0.000 tNET RR 2 fifo_inst/n683_s0/CIN
6.275 0.050 tINS RR 1 fifo_inst/n683_s0/COUT
6.275 0.000 tNET RR 2 fifo_inst/n684_s0/CIN
6.325 0.050 tINS RR 2 fifo_inst/n684_s0/COUT
6.700 0.375 tNET RR 1 fifo_inst/n34_s1/I2
7.161 0.461 tINS RR 4 fifo_inst/n34_s1/F
7.536 0.375 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_3_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 43 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_3_s/CLKB
10.284 -0.091 tSu 1 fifo_inst/Big.mem_Big.mem_0_3_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.779, 52.767%; route: 3.000, 41.892%; tC2Q: 0.382, 5.341%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 2.747
Data Arrival Time 7.536
Data Required Time 10.284
From fifo_inst/Empty_s0
To fifo_inst/Big.mem_Big.mem_0_2_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 43 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 3 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_0_s4/I0
1.659 0.526 tINS RR 11 fifo_inst/rbin_num_next_0_s4/F
2.034 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s5/I0
2.560 0.526 tINS RR 5 fifo_inst/rbin_num_next_2_s5/F
2.935 0.375 tNET RR 1 fifo_inst/rbin_num_next_5_s6/I1
3.451 0.516 tINS RR 6 fifo_inst/rbin_num_next_5_s6/F
3.826 0.375 tNET RR 1 fifo_inst/rbin_num_next_6_s4/I1
4.343 0.516 tINS RR 7 fifo_inst/rbin_num_next_6_s4/F
4.718 0.375 tNET RR 1 fifo_inst/Big.rgraynext_6_s0/I0
5.244 0.526 tINS RR 2 fifo_inst/Big.rgraynext_6_s0/F
5.619 0.375 tNET RR 2 fifo_inst/n681_s0/I0
6.175 0.556 tINS RF 1 fifo_inst/n681_s0/COUT
6.175 0.000 tNET FF 2 fifo_inst/n682_s0/CIN
6.225 0.050 tINS FR 1 fifo_inst/n682_s0/COUT
6.225 0.000 tNET RR 2 fifo_inst/n683_s0/CIN
6.275 0.050 tINS RR 1 fifo_inst/n683_s0/COUT
6.275 0.000 tNET RR 2 fifo_inst/n684_s0/CIN
6.325 0.050 tINS RR 2 fifo_inst/n684_s0/COUT
6.700 0.375 tNET RR 1 fifo_inst/n34_s1/I2
7.161 0.461 tINS RR 4 fifo_inst/n34_s1/F
7.536 0.375 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_2_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 43 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_2_s/CLKB
10.284 -0.091 tSu 1 fifo_inst/Big.mem_Big.mem_0_2_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.779, 52.767%; route: 3.000, 41.892%; tC2Q: 0.382, 5.341%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 2.747
Data Arrival Time 7.536
Data Required Time 10.284
From fifo_inst/Empty_s0
To fifo_inst/Big.mem_Big.mem_0_1_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 43 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 3 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_0_s4/I0
1.659 0.526 tINS RR 11 fifo_inst/rbin_num_next_0_s4/F
2.034 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s5/I0
2.560 0.526 tINS RR 5 fifo_inst/rbin_num_next_2_s5/F
2.935 0.375 tNET RR 1 fifo_inst/rbin_num_next_5_s6/I1
3.451 0.516 tINS RR 6 fifo_inst/rbin_num_next_5_s6/F
3.826 0.375 tNET RR 1 fifo_inst/rbin_num_next_6_s4/I1
4.343 0.516 tINS RR 7 fifo_inst/rbin_num_next_6_s4/F
4.718 0.375 tNET RR 1 fifo_inst/Big.rgraynext_6_s0/I0
5.244 0.526 tINS RR 2 fifo_inst/Big.rgraynext_6_s0/F
5.619 0.375 tNET RR 2 fifo_inst/n681_s0/I0
6.175 0.556 tINS RF 1 fifo_inst/n681_s0/COUT
6.175 0.000 tNET FF 2 fifo_inst/n682_s0/CIN
6.225 0.050 tINS FR 1 fifo_inst/n682_s0/COUT
6.225 0.000 tNET RR 2 fifo_inst/n683_s0/CIN
6.275 0.050 tINS RR 1 fifo_inst/n683_s0/COUT
6.275 0.000 tNET RR 2 fifo_inst/n684_s0/CIN
6.325 0.050 tINS RR 2 fifo_inst/n684_s0/COUT
6.700 0.375 tNET RR 1 fifo_inst/n34_s1/I2
7.161 0.461 tINS RR 4 fifo_inst/n34_s1/F
7.536 0.375 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_1_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 43 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_1_s/CLKB
10.284 -0.091 tSu 1 fifo_inst/Big.mem_Big.mem_0_1_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.779, 52.767%; route: 3.000, 41.892%; tC2Q: 0.382, 5.341%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%