Synthesis Messages

Report Title GowinSynthesis Report
Design File H:\0_gaoyun_p\1.9.9\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\USB_DEVICE_CONTROLLER\data\usb_device_controller_top.v
H:\0_gaoyun_p\1.9.9\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\USB_DEVICE_CONTROLLER\data\usb_device_controller.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version A
Created Time Tue Sep 23 09:08:22 2025
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module USB_Device_Controller_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.306s, Peak memory usage = 48.836MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 48.836MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 48.836MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 48.836MB
    Optimizing Phase 2: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.125s, Peak memory usage = 48.836MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 48.836MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 48.836MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 48.836MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 48.836MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 48.836MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 48.836MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 48.836MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 76.543MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.098s, Peak memory usage = 76.543MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.092s, Peak memory usage = 76.543MB
Total Time and Memory Usage CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 76.543MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 468
I/O Buf 464
    IBUF 376
    OBUF 88
Register 497
    DFFSE 38
    DFFRE 389
    DFFCE 70
LUT 1532
    LUT2 197
    LUT3 432
    LUT4 903
ALU 113
    ALU 113
INV 2
    INV 2

Resource Utilization Summary

Resource Usage Utilization
Logic 1647(1534 LUT, 113 ALU) / 23040 8%
Register 497 / 23685 3%
  --Register as Latch 0 / 23685 0%
  --Register as FF 497 / 23685 3%
BSRAM 0 / 56 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_i Base 10.000 100.0 0.000 5.000 clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_i 100.0(MHz) 146.4(MHz) 14 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.170
Data Arrival Time 7.516
Data Required Time 10.686
From u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0
To u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_2_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.587 0.587 tINS RR 497 clk_i_ibuf/O
0.737 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/CLK
1.043 0.306 tC2Q RR 11 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/Q
1.193 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1918_s7/I0
1.614 0.421 tINS RR 8 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1918_s7/F
1.764 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/descrom_start_10_s17/I0
2.185 0.421 tINS RR 11 u_usb_device_controller/u_usb_device_controller_utmi/descrom_start_10_s17/F
2.335 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s13/I1
2.748 0.413 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s13/F
2.898 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s9/I2
3.267 0.369 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s9/F
3.417 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s8/I0
3.838 0.421 tINS RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s8/F
3.988 0.150 tNET RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1482_s0/I1
4.438 0.450 tINS RF 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1482_s0/COUT
4.438 0.000 tNET FF 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1483_s0/CIN
4.478 0.040 tINS FR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1483_s0/COUT
4.478 0.000 tNET RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1484_s0/CIN
4.518 0.040 tINS RR 4 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1484_s0/COUT
4.668 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s46/I0
5.089 0.421 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s46/F
5.239 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1748_s42/I3
5.449 0.210 tINS RR 6 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1748_s42/F
5.599 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s18/I3
5.809 0.210 tINS RR 3 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s18/F
5.959 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s16/I2
6.328 0.369 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s16/F
6.478 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s13/I2
6.847 0.369 tINS RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s13/F
6.997 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1732_s11/I2
7.366 0.369 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1732_s11/F
7.516 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.587 0.587 tINS RR 497 clk_i_ibuf/O
10.737 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_2_s0/CLK
10.686 -0.051 tSu 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.587, 79.646%; route: 0.150, 20.354%
Arrival Data Path Delay: cell: 4.523, 66.721%; route: 1.950, 28.765%; tC2Q: 0.306, 4.514%
Required Clock Path Delay: cell: 0.587, 79.646%; route: 0.150, 20.354%

Path 2

Path Summary:
Slack 3.170
Data Arrival Time 7.516
Data Required Time 10.686
From u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0
To u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_3_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.587 0.587 tINS RR 497 clk_i_ibuf/O
0.737 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/CLK
1.043 0.306 tC2Q RR 11 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/Q
1.193 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1918_s7/I0
1.614 0.421 tINS RR 8 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1918_s7/F
1.764 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/descrom_start_10_s17/I0
2.185 0.421 tINS RR 11 u_usb_device_controller/u_usb_device_controller_utmi/descrom_start_10_s17/F
2.335 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s13/I1
2.748 0.413 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s13/F
2.898 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s9/I2
3.267 0.369 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s9/F
3.417 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s8/I0
3.838 0.421 tINS RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s8/F
3.988 0.150 tNET RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1482_s0/I1
4.438 0.450 tINS RF 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1482_s0/COUT
4.438 0.000 tNET FF 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1483_s0/CIN
4.478 0.040 tINS FR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1483_s0/COUT
4.478 0.000 tNET RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1484_s0/CIN
4.518 0.040 tINS RR 4 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1484_s0/COUT
4.668 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s46/I0
5.089 0.421 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s46/F
5.239 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1748_s42/I3
5.449 0.210 tINS RR 6 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1748_s42/F
5.599 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s18/I3
5.809 0.210 tINS RR 3 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s18/F
5.959 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s16/I2
6.328 0.369 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s16/F
6.478 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s13/I2
6.847 0.369 tINS RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s13/F
6.997 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s11/I2
7.366 0.369 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s11/F
7.516 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.587 0.587 tINS RR 497 clk_i_ibuf/O
10.737 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_3_s0/CLK
10.686 -0.051 tSu 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.587, 79.646%; route: 0.150, 20.354%
Arrival Data Path Delay: cell: 4.523, 66.721%; route: 1.950, 28.765%; tC2Q: 0.306, 4.514%
Required Clock Path Delay: cell: 0.587, 79.646%; route: 0.150, 20.354%

Path 3

Path Summary:
Slack 3.637
Data Arrival Time 7.049
Data Required Time 10.686
From u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0
To u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_0_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.587 0.587 tINS RR 497 clk_i_ibuf/O
0.737 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/CLK
1.043 0.306 tC2Q RR 11 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/Q
1.193 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1918_s7/I0
1.614 0.421 tINS RR 8 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1918_s7/F
1.764 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/descrom_start_10_s17/I0
2.185 0.421 tINS RR 11 u_usb_device_controller/u_usb_device_controller_utmi/descrom_start_10_s17/F
2.335 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s13/I1
2.748 0.413 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s13/F
2.898 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s9/I2
3.267 0.369 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s9/F
3.417 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s8/I0
3.838 0.421 tINS RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s8/F
3.988 0.150 tNET RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1482_s0/I1
4.438 0.450 tINS RF 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1482_s0/COUT
4.438 0.000 tNET FF 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1483_s0/CIN
4.478 0.040 tINS FR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1483_s0/COUT
4.478 0.000 tNET RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1484_s0/CIN
4.518 0.040 tINS RR 4 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1484_s0/COUT
4.668 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s46/I0
5.089 0.421 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s46/F
5.239 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1748_s42/I3
5.449 0.210 tINS RR 6 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1748_s42/F
5.599 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s17/I2
5.968 0.369 tINS RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1729_s17/F
6.118 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1738_s13/I0
6.539 0.421 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1738_s13/F
6.689 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1738_s14/I3
6.899 0.210 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1738_s14/F
7.049 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.587 0.587 tINS RR 497 clk_i_ibuf/O
10.737 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_0_s0/CLK
10.686 -0.051 tSu 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.587, 79.646%; route: 0.150, 20.354%
Arrival Data Path Delay: cell: 4.206, 66.635%; route: 1.800, 28.517%; tC2Q: 0.306, 4.848%
Required Clock Path Delay: cell: 0.587, 79.646%; route: 0.150, 20.354%

Path 4

Path Summary:
Slack 3.645
Data Arrival Time 7.041
Data Required Time 10.686
From u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0
To u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_9_s2
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.587 0.587 tINS RR 497 clk_i_ibuf/O
0.737 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/CLK
1.043 0.306 tC2Q RR 11 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/Q
1.193 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1918_s7/I0
1.614 0.421 tINS RR 8 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1918_s7/F
1.764 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/descrom_start_10_s17/I0
2.185 0.421 tINS RR 11 u_usb_device_controller/u_usb_device_controller_utmi/descrom_start_10_s17/F
2.335 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s13/I1
2.748 0.413 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s13/F
2.898 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s9/I2
3.267 0.369 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s9/F
3.417 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s8/I0
3.838 0.421 tINS RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s8/F
3.988 0.150 tNET RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1482_s0/I1
4.438 0.450 tINS RF 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1482_s0/COUT
4.438 0.000 tNET FF 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1483_s0/CIN
4.478 0.040 tINS FR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1483_s0/COUT
4.478 0.000 tNET RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1484_s0/CIN
4.518 0.040 tINS RR 4 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1484_s0/COUT
4.668 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s46/I0
5.089 0.421 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s46/F
5.239 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1748_s42/I3
5.449 0.210 tINS RR 6 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1748_s42/F
5.599 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s47/I1
6.012 0.413 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s47/F
6.162 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s40/I3
6.372 0.210 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s40/F
6.522 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s37/I2
6.891 0.369 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s37/F
7.041 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_9_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.587 0.587 tINS RR 497 clk_i_ibuf/O
10.737 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_9_s2/CLK
10.686 -0.051 tSu 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_state_9_s2
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.587, 79.646%; route: 0.150, 20.354%
Arrival Data Path Delay: cell: 4.198, 66.593%; route: 1.800, 28.553%; tC2Q: 0.306, 4.854%
Required Clock Path Delay: cell: 0.587, 79.646%; route: 0.150, 20.354%

Path 5

Path Summary:
Slack 3.645
Data Arrival Time 7.041
Data Required Time 10.686
From u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0
To u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_5_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.587 0.587 tINS RR 497 clk_i_ibuf/O
0.737 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/CLK
1.043 0.306 tC2Q RR 11 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_ctlparam_3_s0/Q
1.193 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1918_s7/I0
1.614 0.421 tINS RR 8 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1918_s7/F
1.764 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/descrom_start_10_s17/I0
2.185 0.421 tINS RR 11 u_usb_device_controller/u_usb_device_controller_utmi/descrom_start_10_s17/F
2.335 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s13/I1
2.748 0.413 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s13/F
2.898 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s9/I2
3.267 0.369 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s9/F
3.417 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s8/I0
3.838 0.421 tINS RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usbc_dsclen_13_s8/F
3.988 0.150 tNET RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1482_s0/I1
4.438 0.450 tINS RF 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1482_s0/COUT
4.438 0.000 tNET FF 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1483_s0/CIN
4.478 0.040 tINS FR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1483_s0/COUT
4.478 0.000 tNET RR 2 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1484_s0/CIN
4.518 0.040 tINS RR 4 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1484_s0/COUT
4.668 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s46/I0
5.089 0.421 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1746_s46/F
5.239 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1748_s42/I3
5.449 0.210 tINS RR 6 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1748_s42/F
5.599 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1723_s17/I2
5.968 0.369 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1723_s17/F
6.118 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1723_s14/I1
6.531 0.413 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1723_s14/F
6.681 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1723_s11/I3
6.891 0.210 tINS RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/n1723_s11/F
7.041 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.587 0.587 tINS RR 497 clk_i_ibuf/O
10.737 0.150 tNET RR 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_5_s0/CLK
10.686 -0.051 tSu 1 u_usb_device_controller/u_usb_device_controller_utmi/usb_control_inst/s_answerptr_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.587, 79.646%; route: 0.150, 20.354%
Arrival Data Path Delay: cell: 4.198, 66.593%; route: 1.800, 28.553%; tC2Q: 0.306, 4.854%
Required Clock Path Delay: cell: 0.587, 79.646%; route: 0.150, 20.354%