Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\ddr3_1_4code_hs.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\DDR3_TOP.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12 (64-bit)
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version A
Created Time Mon Oct 20 11:23:18 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DDR3_Memory_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.765s, Elapsed time = 0h 0m 0.821s, Peak memory usage = 118.535MB
Running netlist conversion:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 118.535MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.354s, Peak memory usage = 118.535MB
    Optimizing Phase 1: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.162s, Peak memory usage = 118.535MB
    Optimizing Phase 2: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.476s, Peak memory usage = 118.535MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.286s, Peak memory usage = 118.535MB
    Inferring Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 118.535MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 118.535MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 118.535MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.33s, Peak memory usage = 118.535MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.127s, Peak memory usage = 118.535MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.087s, Peak memory usage = 118.535MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 132.109MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.361s, Peak memory usage = 132.109MB
Generate output files:
    CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.47s, Peak memory usage = 135.121MB
Total Time and Memory Usage CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 135.121MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 371
I/O Buf 365
    IBUF 182
    OBUF 162
    TBUF 2
    IOBUF 16
    ELVDS_OBUF 1
    ELVDS_IOBUF 2
Register 3565
    DFFSE 1
    DFFRE 249
    DFFPE 66
    DFFCE 3249
LUT 2149
    LUT2 306
    LUT3 950
    LUT4 893
ALU 125
    ALU 125
INV 21
    INV 21
IOLOGIC 76
    IDES8_MEM 16
    OSER8 24
    OSER8_MEM 20
    IODELAY 16
BSRAM 8
    SDPB 4
    SDPX9B 4
CLOCK 4
    CLKDIV 1
    DQS 2
    DDRDLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 2295(2170 LUT, 125 ALU) / 23040 10%
Register 3565 / 23685 16%
  --Register as Latch 0 / 23685 0%
  --Register as FF 3565 / 23685 16%
BSRAM 8 / 56 15%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 memory_clk Base 10.000 100.000 0.000 5.000 memory_clk_ibuf/I
2 clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I
3 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk Generated 40.000 25.000 0.000 20.000 memory_clk_ibuf/I memory_clk gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 memory_clk 100.000(MHz) 1394.296(MHz) 1 TOP
2 clk 100.000(MHz) 238.892(MHz) 6 TOP
3 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk 25.000(MHz) 216.450(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.911
Data Arrival Time 1.917
Data Required Time 4.828
From gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0
To gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.290 0.290 tCL RR 3604 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.590 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK
0.896 0.306 tC2Q RR 11 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q
1.196 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0
1.617 0.421 tINS RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F
1.917 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.000 0.000 tINS FF 64 memory_clk_ibuf/O
5.280 0.280 tNET FF 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
5.245 -0.035 tUnc gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
4.828 -0.417 tSu 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: -0.310
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.421, 31.726%; route: 0.600, 45.214%; tC2Q: 0.306, 23.060%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 2

Path Summary:
Slack 2.911
Data Arrival Time 1.917
Data Required Time 4.828
From gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0
To gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.290 0.290 tCL RR 3604 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.590 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK
0.896 0.306 tC2Q RR 11 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q
1.196 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0
1.617 0.421 tINS RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F
1.917 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.000 0.000 tINS FF 64 memory_clk_ibuf/O
5.280 0.280 tNET FF 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
5.245 -0.035 tUnc gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
4.828 -0.417 tSu 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: -0.310
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.421, 31.726%; route: 0.600, 45.214%; tC2Q: 0.306, 23.060%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 3

Path Summary:
Slack 5.814
Data Arrival Time 4.435
Data Required Time 10.249
From gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3
To gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 40 clk_ibuf/O
0.300 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/CLK
0.606 0.306 tC2Q RR 6 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/Q
0.906 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/I0
1.327 0.421 tINS RR 4 gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/F
1.627 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/I1
2.040 0.413 tINS RR 4 gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/F
2.340 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n46_s2/I2
2.709 0.369 tINS RR 3 gw3_top/u_ddr_phy_top/ddr_sync/n46_s2/F
3.009 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n45_s2/I1
3.422 0.413 tINS RR 2 gw3_top/u_ddr_phy_top/ddr_sync/n45_s2/F
3.722 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n44_s1/I1
4.135 0.413 tINS RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n44_s1/F
4.435 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 40 clk_ibuf/O
10.300 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1/CLK
10.249 -0.051 tSu 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.029, 49.069%; route: 1.800, 43.531%; tC2Q: 0.306, 7.400%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 4

Path Summary:
Slack 6.017
Data Arrival Time 4.232
Data Required Time 10.249
From gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3
To gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_14_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 40 clk_ibuf/O
0.300 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/CLK
0.606 0.306 tC2Q RR 6 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/Q
0.906 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/I0
1.327 0.421 tINS RR 4 gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/F
1.627 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/I1
2.040 0.413 tINS RR 4 gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/F
2.340 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n46_s2/I2
2.709 0.369 tINS RR 3 gw3_top/u_ddr_phy_top/ddr_sync/n46_s2/F
3.009 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n45_s2/I1
3.422 0.413 tINS RR 2 gw3_top/u_ddr_phy_top/ddr_sync/n45_s2/F
3.722 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n43_s1/I3
3.932 0.210 tINS RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n43_s1/F
4.232 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_14_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 40 clk_ibuf/O
10.300 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_14_s1/CLK
10.249 -0.051 tSu 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_14_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.826, 46.440%; route: 1.800, 45.778%; tC2Q: 0.306, 7.782%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 5

Path Summary:
Slack 6.475
Data Arrival Time 3.774
Data Required Time 10.249
From gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3
To gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 40 clk_ibuf/O
0.300 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/CLK
0.606 0.306 tC2Q RR 6 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/Q
0.906 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/I0
1.327 0.421 tINS RR 4 gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/F
1.627 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/I1
2.040 0.413 tINS RR 4 gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/F
2.340 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n48_s4/I0
2.761 0.421 tINS RR 2 gw3_top/u_ddr_phy_top/ddr_sync/n48_s4/F
3.061 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n48_s5/I1
3.474 0.413 tINS RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n48_s5/F
3.774 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 40 clk_ibuf/O
10.300 0.300 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/CLK
10.249 -0.051 tSu 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.668, 48.014%; route: 1.500, 43.178%; tC2Q: 0.306, 8.808%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%