Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\acg525_acm2108_ddr3_udp\acm2108_ddr3_udp\src\fifo_rx\temp\FIFO\fifo_define.v
C:\Users\24165\Desktop\acg525_acm2108_ddr3_udp\acm2108_ddr3_udp\src\fifo_rx\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12 (64-bit)
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version A
Created Time Mon Oct 20 11:44:19 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo_rx
Synthesis Process Running parser:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.332s, Peak memory usage = 75.727MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 75.727MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 75.727MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 75.727MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 75.727MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 75.727MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 75.727MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 75.727MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 75.727MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 75.727MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 75.727MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 75.727MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.234s, Peak memory usage = 90.379MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 90.379MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 90.379MB
Total Time and Memory Usage CPU time = 0h 0m 0.498s, Elapsed time = 0h 0m 0.581s, Peak memory usage = 90.379MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 23
I/O Buf 23
    IBUF 13
    OBUF 10
Register 76
    DFFPE 5
    DFFCE 71
LUT 55
    LUT2 14
    LUT3 15
    LUT4 26
ALU 9
    ALU 9
INV 3
    INV 3
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 67(58 LUT, 9 ALU) / 23040 <1%
Register 76 / 23685 <1%
  --Register as Latch 0 / 23685 0%
  --Register as FF 76 / 23685 <1%
BSRAM 1 / 56 2%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 205.931(MHz) 8 TOP
2 WrClk 100.000(MHz) 283.688(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.144
Data Arrival Time 5.105
Data Required Time 10.249
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 39 RdClk_ibuf/O
0.300 0.300 tNET RR 1 fifo_inst/Empty_s0/CLK
0.606 0.306 tC2Q RR 6 fifo_inst/Empty_s0/Q
0.906 0.300 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.327 0.421 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
1.627 0.300 tNET RR 1 fifo_inst/rbin_num_next_5_s6/I3
1.837 0.210 tINS RR 7 fifo_inst/rbin_num_next_5_s6/F
2.137 0.300 tNET RR 1 fifo_inst/rbin_num_next_6_s5/I1
2.550 0.413 tINS RR 3 fifo_inst/rbin_num_next_6_s5/F
2.850 0.300 tNET RR 1 fifo_inst/Equal.rgraynext_5_s1/I2
3.219 0.369 tINS RR 2 fifo_inst/Equal.rgraynext_5_s1/F
3.519 0.300 tNET RR 2 fifo_inst/n100_s0/I0
3.964 0.445 tINS RF 1 fifo_inst/n100_s0/COUT
3.964 0.000 tNET FF 2 fifo_inst/n101_s0/CIN
4.004 0.040 tINS FR 1 fifo_inst/n101_s0/COUT
4.004 0.000 tNET RR 2 fifo_inst/n102_s0/CIN
4.044 0.040 tINS RR 1 fifo_inst/n102_s0/COUT
4.044 0.000 tNET RR 2 fifo_inst/n103_s0/CIN
4.084 0.040 tINS RR 2 fifo_inst/n103_s0/COUT
4.384 0.300 tNET RR 1 fifo_inst/rempty_val_s1/I0
4.805 0.421 tINS RR 1 fifo_inst/rempty_val_s1/F
5.105 0.300 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 39 RdClk_ibuf/O
10.300 0.300 tNET RR 1 fifo_inst/Empty_s0/CLK
10.249 -0.051 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.399, 49.928%; route: 2.100, 43.704%; tC2Q: 0.306, 6.368%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 2

Path Summary:
Slack 5.174
Data Arrival Time 5.053
Data Required Time 10.227
From fifo_inst/Empty_s0
To fifo_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 39 RdClk_ibuf/O
0.300 0.300 tNET RR 1 fifo_inst/Empty_s0/CLK
0.606 0.306 tC2Q RR 6 fifo_inst/Empty_s0/Q
0.906 0.300 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.327 0.421 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
1.627 0.300 tNET RR 1 fifo_inst/rbin_num_next_5_s6/I3
1.837 0.210 tINS RR 7 fifo_inst/rbin_num_next_5_s6/F
2.137 0.300 tNET RR 1 fifo_inst/rbin_num_next_6_s5/I1
2.550 0.413 tINS RR 3 fifo_inst/rbin_num_next_6_s5/F
2.850 0.300 tNET RR 1 fifo_inst/Equal.rgraynext_5_s1/I2
3.219 0.369 tINS RR 2 fifo_inst/Equal.rgraynext_5_s1/F
3.519 0.300 tNET RR 2 fifo_inst/n100_s0/I0
3.964 0.445 tINS RF 1 fifo_inst/n100_s0/COUT
3.964 0.000 tNET FF 2 fifo_inst/n101_s0/CIN
4.004 0.040 tINS FR 1 fifo_inst/n101_s0/COUT
4.004 0.000 tNET RR 2 fifo_inst/n102_s0/CIN
4.044 0.040 tINS RR 1 fifo_inst/n102_s0/COUT
4.044 0.000 tNET RR 2 fifo_inst/n103_s0/CIN
4.084 0.040 tINS RR 2 fifo_inst/n103_s0/COUT
4.384 0.300 tNET RR 1 fifo_inst/n33_s1/I2
4.753 0.369 tINS RR 1 fifo_inst/n33_s1/F
5.053 0.300 tNET RR 1 fifo_inst/Equal.mem_Equal.mem_0_0_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 39 RdClk_ibuf/O
10.300 0.300 tNET RR 1 fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB
10.227 -0.073 tSu 1 fifo_inst/Equal.mem_Equal.mem_0_0_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.347, 49.379%; route: 2.100, 44.183%; tC2Q: 0.306, 6.438%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 3

Path Summary:
Slack 6.475
Data Arrival Time 3.774
Data Required Time 10.249
From fifo_inst/Full_s0
To fifo_inst/Full_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 39 WrClk_ibuf/O
0.300 0.300 tNET RR 1 fifo_inst/Full_s0/CLK
0.606 0.306 tC2Q RR 6 fifo_inst/Full_s0/Q
0.906 0.300 tNET RR 1 fifo_inst/Equal.wgraynext_2_s1/I0
1.327 0.421 tINS RR 14 fifo_inst/Equal.wgraynext_2_s1/F
1.627 0.300 tNET RR 1 fifo_inst/Equal.wgraynext_4_s0/I0
2.048 0.421 tINS RR 2 fifo_inst/Equal.wgraynext_4_s0/F
2.348 0.300 tNET RR 1 fifo_inst/wfull_val_s2/I1
2.761 0.413 tINS RR 1 fifo_inst/wfull_val_s2/F
3.061 0.300 tNET RR 1 fifo_inst/wfull_val_s0/I1
3.474 0.413 tINS RR 1 fifo_inst/wfull_val_s0/F
3.774 0.300 tNET RR 1 fifo_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 39 WrClk_ibuf/O
10.300 0.300 tNET RR 1 fifo_inst/Full_s0/CLK
10.249 -0.051 tSu 1 fifo_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.668, 48.014%; route: 1.500, 43.178%; tC2Q: 0.306, 8.808%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 4

Path Summary:
Slack 6.670
Data Arrival Time 3.579
Data Required Time 10.249
From fifo_inst/Empty_s0
To fifo_inst/Equal.rptr_7_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 39 RdClk_ibuf/O
0.300 0.300 tNET RR 1 fifo_inst/Empty_s0/CLK
0.606 0.306 tC2Q RR 6 fifo_inst/Empty_s0/Q
0.906 0.300 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.327 0.421 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
1.627 0.300 tNET RR 1 fifo_inst/rbin_num_next_5_s6/I3
1.837 0.210 tINS RR 7 fifo_inst/rbin_num_next_5_s6/F
2.137 0.300 tNET RR 1 fifo_inst/rbin_num_next_7_s7/I0
2.558 0.421 tINS RR 4 fifo_inst/rbin_num_next_7_s7/F
2.858 0.300 tNET RR 1 fifo_inst/Equal.rgraynext_7_s0/I0
3.279 0.421 tINS RR 2 fifo_inst/Equal.rgraynext_7_s0/F
3.579 0.300 tNET RR 1 fifo_inst/Equal.rptr_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 39 RdClk_ibuf/O
10.300 0.300 tNET RR 1 fifo_inst/Equal.rptr_7_s0/CLK
10.249 -0.051 tSu 1 fifo_inst/Equal.rptr_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.473, 44.922%; route: 1.500, 45.746%; tC2Q: 0.306, 9.332%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 5

Path Summary:
Slack 6.730
Data Arrival Time 3.519
Data Required Time 10.249
From fifo_inst/Empty_s0
To fifo_inst/Equal.rptr_5_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 39 RdClk_ibuf/O
0.300 0.300 tNET RR 1 fifo_inst/Empty_s0/CLK
0.606 0.306 tC2Q RR 6 fifo_inst/Empty_s0/Q
0.906 0.300 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.327 0.421 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
1.627 0.300 tNET RR 1 fifo_inst/rbin_num_next_5_s6/I3
1.837 0.210 tINS RR 7 fifo_inst/rbin_num_next_5_s6/F
2.137 0.300 tNET RR 1 fifo_inst/rbin_num_next_6_s5/I1
2.550 0.413 tINS RR 3 fifo_inst/rbin_num_next_6_s5/F
2.850 0.300 tNET RR 1 fifo_inst/Equal.rgraynext_5_s1/I2
3.219 0.369 tINS RR 2 fifo_inst/Equal.rgraynext_5_s1/F
3.519 0.300 tNET RR 1 fifo_inst/Equal.rptr_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 39 RdClk_ibuf/O
10.300 0.300 tNET RR 1 fifo_inst/Equal.rptr_5_s0/CLK
10.249 -0.051 tSu 1 fifo_inst/Equal.rptr_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.413, 43.896%; route: 1.500, 46.598%; tC2Q: 0.306, 9.506%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%