Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\acg525_acm2108_ddr3_udp\acm2108_ddr3_udp\src\fifo_tx\temp\FIFO\fifo_define.v
C:\Users\24165\Desktop\acg525_acm2108_ddr3_udp\acm2108_ddr3_udp\src\fifo_tx\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12 (64-bit)
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version A
Created Time Mon Oct 20 11:45:03 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo_tx
Synthesis Process Running parser:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.334s, Peak memory usage = 76.117MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.117MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.117MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.117MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 76.117MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 76.117MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.117MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.117MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.117MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 76.117MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.117MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.117MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.362s, Peak memory usage = 90.957MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 90.957MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 90.957MB
Total Time and Memory Usage CPU time = 0h 0m 0.67s, Elapsed time = 0h 0m 0.727s, Peak memory usage = 90.957MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 54
I/O Buf 54
    IBUF 21
    OBUF 33
Register 116
    DFFPE 5
    DFFCE 111
LUT 104
    LUT2 30
    LUT3 32
    LUT4 42
ALU 33
    ALU 33
INV 4
    INV 4
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 141(108 LUT, 33 ALU) / 23040 <1%
Register 116 / 23685 <1%
  --Register as Latch 0 / 23685 0%
  --Register as FF 116 / 23685 <1%
BSRAM 1 / 56 2%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 196.271(MHz) 8 TOP
2 WrClk 100.000(MHz) 220.702(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.905
Data Arrival Time 5.344
Data Required Time 10.249
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 60 RdClk_ibuf/O
0.300 0.300 tNET RR 1 fifo_inst/Empty_s0/CLK
0.606 0.306 tC2Q RR 5 fifo_inst/Empty_s0/Q
0.906 0.300 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.327 0.421 tINS RR 8 fifo_inst/rbin_num_next_2_s6/F
1.627 0.300 tNET RR 1 fifo_inst/rbin_num_next_6_s6/I2
1.996 0.369 tINS RR 7 fifo_inst/rbin_num_next_6_s6/F
2.296 0.300 tNET RR 1 fifo_inst/rbin_num_next_7_s5/I1
2.709 0.413 tINS RR 3 fifo_inst/rbin_num_next_7_s5/F
3.009 0.300 tNET RR 1 fifo_inst/Small.rgraynext_5_s1/I2
3.378 0.369 tINS RR 2 fifo_inst/Small.rgraynext_5_s1/F
3.678 0.300 tNET RR 2 fifo_inst/n288_s0/I0
4.123 0.445 tINS RF 1 fifo_inst/n288_s0/COUT
4.123 0.000 tNET FF 2 fifo_inst/n289_s0/CIN
4.163 0.040 tINS FR 1 fifo_inst/n289_s0/COUT
4.163 0.000 tNET RR 2 fifo_inst/n290_s0/CIN
4.203 0.040 tINS RR 1 fifo_inst/n290_s0/COUT
4.203 0.000 tNET RR 2 fifo_inst/n291_s0/CIN
4.243 0.040 tINS RR 1 fifo_inst/n291_s0/COUT
4.243 0.000 tNET RR 2 fifo_inst/n292_s0/CIN
4.283 0.040 tINS RR 1 fifo_inst/n292_s0/COUT
4.283 0.000 tNET RR 2 fifo_inst/n293_s0/CIN
4.323 0.040 tINS RR 2 fifo_inst/n293_s0/COUT
4.623 0.300 tNET RR 1 fifo_inst/rempty_val_s1/I0
5.044 0.421 tINS RR 1 fifo_inst/rempty_val_s1/F
5.344 0.300 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 60 RdClk_ibuf/O
10.300 0.300 tNET RR 1 fifo_inst/Empty_s0/CLK
10.249 -0.051 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.638, 52.299%; route: 2.100, 41.634%; tC2Q: 0.306, 6.067%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 2

Path Summary:
Slack 4.935
Data Arrival Time 5.292
Data Required Time 10.227
From fifo_inst/Empty_s0
To fifo_inst/Small.mem_Small.mem_0_0_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 60 RdClk_ibuf/O
0.300 0.300 tNET RR 1 fifo_inst/Empty_s0/CLK
0.606 0.306 tC2Q RR 5 fifo_inst/Empty_s0/Q
0.906 0.300 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.327 0.421 tINS RR 8 fifo_inst/rbin_num_next_2_s6/F
1.627 0.300 tNET RR 1 fifo_inst/rbin_num_next_6_s6/I2
1.996 0.369 tINS RR 7 fifo_inst/rbin_num_next_6_s6/F
2.296 0.300 tNET RR 1 fifo_inst/rbin_num_next_7_s5/I1
2.709 0.413 tINS RR 3 fifo_inst/rbin_num_next_7_s5/F
3.009 0.300 tNET RR 1 fifo_inst/Small.rgraynext_5_s1/I2
3.378 0.369 tINS RR 2 fifo_inst/Small.rgraynext_5_s1/F
3.678 0.300 tNET RR 2 fifo_inst/n288_s0/I0
4.123 0.445 tINS RF 1 fifo_inst/n288_s0/COUT
4.123 0.000 tNET FF 2 fifo_inst/n289_s0/CIN
4.163 0.040 tINS FR 1 fifo_inst/n289_s0/COUT
4.163 0.000 tNET RR 2 fifo_inst/n290_s0/CIN
4.203 0.040 tINS RR 1 fifo_inst/n290_s0/COUT
4.203 0.000 tNET RR 2 fifo_inst/n291_s0/CIN
4.243 0.040 tINS RR 1 fifo_inst/n291_s0/COUT
4.243 0.000 tNET RR 2 fifo_inst/n292_s0/CIN
4.283 0.040 tINS RR 1 fifo_inst/n292_s0/COUT
4.283 0.000 tNET RR 2 fifo_inst/n293_s0/CIN
4.323 0.040 tINS RR 2 fifo_inst/n293_s0/COUT
4.623 0.300 tNET RR 1 fifo_inst/n36_s1/I2
4.992 0.369 tINS RR 1 fifo_inst/n36_s1/F
5.292 0.300 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_0_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 60 RdClk_ibuf/O
10.300 0.300 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_0_s/CLKB
10.227 -0.073 tSu 1 fifo_inst/Small.mem_Small.mem_0_0_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.586, 51.803%; route: 2.100, 42.067%; tC2Q: 0.306, 6.130%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 3

Path Summary:
Slack 5.469
Data Arrival Time 4.780
Data Required Time 10.249
From fifo_inst/Small.wq2_rptr_7_s0
To fifo_inst/Wnum_10_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 58 WrClk_ibuf/O
0.300 0.300 tNET RR 1 fifo_inst/Small.wq2_rptr_7_s0/CLK
0.606 0.306 tC2Q RR 2 fifo_inst/Small.wq2_rptr_7_s0/Q
0.906 0.300 tNET RR 1 fifo_inst/Small.rcount_w_7_s0/I0
1.327 0.421 tINS RR 4 fifo_inst/Small.rcount_w_7_s0/F
1.627 0.300 tNET RR 1 fifo_inst/Small.rcount_w_4_s0/I3
1.837 0.210 tINS RR 4 fifo_inst/Small.rcount_w_4_s0/F
2.137 0.300 tNET RR 1 fifo_inst/Small.rcount_w_2_s0/I2
2.506 0.369 tINS RR 2 fifo_inst/Small.rcount_w_2_s0/F
2.806 0.300 tNET RR 1 fifo_inst/Small.rcount_w_0_s0/I2
3.175 0.369 tINS RR 1 fifo_inst/Small.rcount_w_0_s0/F
3.475 0.300 tNET RR 2 fifo_inst/wcnt_sub_0_s/I1
3.925 0.450 tINS RF 1 fifo_inst/wcnt_sub_0_s/COUT
3.925 0.000 tNET FF 2 fifo_inst/wcnt_sub_1_s/CIN
3.965 0.040 tINS FR 1 fifo_inst/wcnt_sub_1_s/COUT
3.965 0.000 tNET RR 2 fifo_inst/wcnt_sub_2_s/CIN
4.005 0.040 tINS RR 1 fifo_inst/wcnt_sub_2_s/COUT
4.005 0.000 tNET RR 2 fifo_inst/wcnt_sub_3_s/CIN
4.045 0.040 tINS RR 1 fifo_inst/wcnt_sub_3_s/COUT
4.045 0.000 tNET RR 2 fifo_inst/wcnt_sub_4_s/CIN
4.085 0.040 tINS RR 1 fifo_inst/wcnt_sub_4_s/COUT
4.085 0.000 tNET RR 2 fifo_inst/wcnt_sub_5_s/CIN
4.125 0.040 tINS RR 1 fifo_inst/wcnt_sub_5_s/COUT
4.125 0.000 tNET RR 2 fifo_inst/wcnt_sub_6_s/CIN
4.165 0.040 tINS RR 1 fifo_inst/wcnt_sub_6_s/COUT
4.165 0.000 tNET RR 2 fifo_inst/wcnt_sub_7_s/CIN
4.205 0.040 tINS RR 1 fifo_inst/wcnt_sub_7_s/COUT
4.205 0.000 tNET RR 2 fifo_inst/wcnt_sub_8_s/CIN
4.245 0.040 tINS RR 1 fifo_inst/wcnt_sub_8_s/COUT
4.245 0.000 tNET RR 2 fifo_inst/wcnt_sub_9_s/CIN
4.285 0.040 tINS RR 1 fifo_inst/wcnt_sub_9_s/COUT
4.285 0.000 tNET RR 2 fifo_inst/wcnt_sub_10_s/CIN
4.480 0.195 tINS RR 1 fifo_inst/wcnt_sub_10_s/SUM
4.780 0.300 tNET RR 1 fifo_inst/Wnum_10_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 58 WrClk_ibuf/O
10.300 0.300 tNET RR 1 fifo_inst/Wnum_10_s0/CLK
10.249 -0.051 tSu 1 fifo_inst/Wnum_10_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.374, 52.991%; route: 1.800, 40.179%; tC2Q: 0.306, 6.830%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 4

Path Summary:
Slack 5.474
Data Arrival Time 4.775
Data Required Time 10.249
From fifo_inst/Small.rq2_wptr_10_s0
To fifo_inst/Rnum_11_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 60 RdClk_ibuf/O
0.300 0.300 tNET RR 1 fifo_inst/Small.rq2_wptr_10_s0/CLK
0.606 0.306 tC2Q RR 5 fifo_inst/Small.rq2_wptr_10_s0/Q
0.906 0.300 tNET RR 1 fifo_inst/Small.wcount_r_1_8_s0/I0
1.327 0.421 tINS RR 4 fifo_inst/Small.wcount_r_1_8_s0/F
1.627 0.300 tNET RR 1 fifo_inst/Small.wcount_r_1_5_s0/I3
1.837 0.210 tINS RR 4 fifo_inst/Small.wcount_r_1_5_s0/F
2.137 0.300 tNET RR 1 fifo_inst/Small.wcount_r_1_3_s0/I2
2.506 0.369 tINS RR 2 fifo_inst/Small.wcount_r_1_3_s0/F
2.806 0.300 tNET RR 1 fifo_inst/Small.wcount_r_1_1_s0/I2
3.175 0.369 tINS RR 1 fifo_inst/Small.wcount_r_1_1_s0/F
3.475 0.300 tNET RR 2 fifo_inst/rcnt_sub_1_s/I0
3.920 0.445 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
3.920 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
3.960 0.040 tINS FR 1 fifo_inst/rcnt_sub_2_s/COUT
3.960 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
4.000 0.040 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
4.000 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
4.040 0.040 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
4.040 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
4.080 0.040 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
4.080 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
4.120 0.040 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
4.120 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
4.160 0.040 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
4.160 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
4.200 0.040 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
4.200 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
4.240 0.040 tINS RR 1 fifo_inst/rcnt_sub_9_s/COUT
4.240 0.000 tNET RR 2 fifo_inst/rcnt_sub_10_s/CIN
4.280 0.040 tINS RR 1 fifo_inst/rcnt_sub_10_s/COUT
4.280 0.000 tNET RR 2 fifo_inst/rcnt_sub_11_s/CIN
4.475 0.195 tINS RR 1 fifo_inst/rcnt_sub_11_s/SUM
4.775 0.300 tNET RR 1 fifo_inst/Rnum_11_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 60 RdClk_ibuf/O
10.300 0.300 tNET RR 1 fifo_inst/Rnum_11_s0/CLK
10.249 -0.051 tSu 1 fifo_inst/Rnum_11_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.369, 52.939%; route: 1.800, 40.223%; tC2Q: 0.306, 6.838%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 5

Path Summary:
Slack 5.509
Data Arrival Time 4.740
Data Required Time 10.249
From fifo_inst/Small.wq2_rptr_7_s0
To fifo_inst/Wnum_9_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 58 WrClk_ibuf/O
0.300 0.300 tNET RR 1 fifo_inst/Small.wq2_rptr_7_s0/CLK
0.606 0.306 tC2Q RR 2 fifo_inst/Small.wq2_rptr_7_s0/Q
0.906 0.300 tNET RR 1 fifo_inst/Small.rcount_w_7_s0/I0
1.327 0.421 tINS RR 4 fifo_inst/Small.rcount_w_7_s0/F
1.627 0.300 tNET RR 1 fifo_inst/Small.rcount_w_4_s0/I3
1.837 0.210 tINS RR 4 fifo_inst/Small.rcount_w_4_s0/F
2.137 0.300 tNET RR 1 fifo_inst/Small.rcount_w_2_s0/I2
2.506 0.369 tINS RR 2 fifo_inst/Small.rcount_w_2_s0/F
2.806 0.300 tNET RR 1 fifo_inst/Small.rcount_w_0_s0/I2
3.175 0.369 tINS RR 1 fifo_inst/Small.rcount_w_0_s0/F
3.475 0.300 tNET RR 2 fifo_inst/wcnt_sub_0_s/I1
3.925 0.450 tINS RF 1 fifo_inst/wcnt_sub_0_s/COUT
3.925 0.000 tNET FF 2 fifo_inst/wcnt_sub_1_s/CIN
3.965 0.040 tINS FR 1 fifo_inst/wcnt_sub_1_s/COUT
3.965 0.000 tNET RR 2 fifo_inst/wcnt_sub_2_s/CIN
4.005 0.040 tINS RR 1 fifo_inst/wcnt_sub_2_s/COUT
4.005 0.000 tNET RR 2 fifo_inst/wcnt_sub_3_s/CIN
4.045 0.040 tINS RR 1 fifo_inst/wcnt_sub_3_s/COUT
4.045 0.000 tNET RR 2 fifo_inst/wcnt_sub_4_s/CIN
4.085 0.040 tINS RR 1 fifo_inst/wcnt_sub_4_s/COUT
4.085 0.000 tNET RR 2 fifo_inst/wcnt_sub_5_s/CIN
4.125 0.040 tINS RR 1 fifo_inst/wcnt_sub_5_s/COUT
4.125 0.000 tNET RR 2 fifo_inst/wcnt_sub_6_s/CIN
4.165 0.040 tINS RR 1 fifo_inst/wcnt_sub_6_s/COUT
4.165 0.000 tNET RR 2 fifo_inst/wcnt_sub_7_s/CIN
4.205 0.040 tINS RR 1 fifo_inst/wcnt_sub_7_s/COUT
4.205 0.000 tNET RR 2 fifo_inst/wcnt_sub_8_s/CIN
4.245 0.040 tINS RR 1 fifo_inst/wcnt_sub_8_s/COUT
4.245 0.000 tNET RR 2 fifo_inst/wcnt_sub_9_s/CIN
4.440 0.195 tINS RR 1 fifo_inst/wcnt_sub_9_s/SUM
4.740 0.300 tNET RR 1 fifo_inst/Wnum_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 58 WrClk_ibuf/O
10.300 0.300 tNET RR 1 fifo_inst/Wnum_9_s0/CLK
10.249 -0.051 tSu 1 fifo_inst/Wnum_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.334, 52.567%; route: 1.800, 40.541%; tC2Q: 0.306, 6.892%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%