Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\24165\Desktop\acg525_acm2108_ddr3_udp\acm2108_ddr3_udp\src\rd_data_fifo\temp\FIFO\fifo_define.v C:\Users\24165\Desktop\acg525_acm2108_ddr3_udp\acm2108_ddr3_udp\src\rd_data_fifo\temp\FIFO\fifo_parameter.v D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FIFO\data\edc.v D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FIFO\data\fifo.v D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FIFO\data\fifo_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12 (64-bit) |
| Part Number | GW5A-LV25UG324C2/I1 |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Mon Oct 20 11:45:40 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | rd_data_fifo |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.343s, Peak memory usage = 76.828MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.828MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 76.828MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 76.828MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 76.828MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 76.828MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.828MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.828MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.828MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 76.828MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.828MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.828MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 0.978s, Peak memory usage = 93.348MB Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 93.348MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 93.348MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 93.348MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 176 |
| I/O Buf | 176 |
| IBUF | 133 |
| OBUF | 43 |
| Register | 112 |
| DFFPE | 6 |
| DFFCE | 106 |
| LUT | 302 |
| LUT2 | 34 |
| LUT3 | 88 |
| LUT4 | 180 |
| ALU | 32 |
| ALU | 32 |
| INV | 4 |
| INV | 4 |
| BSRAM | 4 |
| SDPB | 4 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 338(306 LUT, 32 ALU) / 23040 | 2% |
| Register | 112 / 23685 | <1% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 112 / 23685 | <1% |
| BSRAM | 4 / 56 | 8% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | RdClk | Base | 10.000 | 100.000 | 0.000 | 5.000 | RdClk_ibuf/I | ||
| 2 | WrClk | Base | 10.000 | 100.000 | 0.000 | 5.000 | WrClk_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | RdClk | 100.000(MHz) | 192.938(MHz) | 8 | TOP |
| 2 | WrClk | 100.000(MHz) | 195.008(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.817 |
| Data Arrival Time | 5.432 |
| Data Required Time | 10.249 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Empty_s0 |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 7 | fifo_inst/Empty_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s4/I0 |
| 1.327 | 0.421 | tINS | RR | 10 | fifo_inst/rbin_num_next_2_s4/F |
| 1.627 | 0.300 | tNET | RR | 1 | fifo_inst/Small.rgraynext_2_s2/I1 |
| 2.040 | 0.413 | tINS | RR | 7 | fifo_inst/Small.rgraynext_2_s2/F |
| 2.340 | 0.300 | tNET | RR | 1 | fifo_inst/Small.rgraynext_3_s1/I1 |
| 2.753 | 0.413 | tINS | RR | 3 | fifo_inst/Small.rgraynext_3_s1/F |
| 3.053 | 0.300 | tNET | RR | 1 | fifo_inst/Small.rgraynext_4_s0/I1 |
| 3.466 | 0.413 | tINS | RR | 2 | fifo_inst/Small.rgraynext_4_s0/F |
| 3.766 | 0.300 | tNET | RR | 2 | fifo_inst/n681_s0/I0 |
| 4.211 | 0.445 | tINS | RF | 1 | fifo_inst/n681_s0/COUT |
| 4.211 | 0.000 | tNET | FF | 2 | fifo_inst/n682_s0/CIN |
| 4.251 | 0.040 | tINS | FR | 1 | fifo_inst/n682_s0/COUT |
| 4.251 | 0.000 | tNET | RR | 2 | fifo_inst/n683_s0/CIN |
| 4.291 | 0.040 | tINS | RR | 1 | fifo_inst/n683_s0/COUT |
| 4.291 | 0.000 | tNET | RR | 2 | fifo_inst/n684_s0/CIN |
| 4.331 | 0.040 | tINS | RR | 1 | fifo_inst/n684_s0/COUT |
| 4.331 | 0.000 | tNET | RR | 2 | fifo_inst/n685_s0/CIN |
| 4.371 | 0.040 | tINS | RR | 1 | fifo_inst/n685_s0/COUT |
| 4.371 | 0.000 | tNET | RR | 2 | fifo_inst/n686_s0/CIN |
| 4.411 | 0.040 | tINS | RR | 2 | fifo_inst/n686_s0/COUT |
| 4.711 | 0.300 | tNET | RR | 1 | fifo_inst/rempty_val_s1/I0 |
| 5.132 | 0.421 | tINS | RR | 1 | fifo_inst/rempty_val_s1/F |
| 5.432 | 0.300 | tNET | RR | 1 | fifo_inst/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 10.249 | -0.051 | tSu | 1 | fifo_inst/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 2.726, 53.117%; route: 2.100, 40.920%; tC2Q: 0.306, 5.963% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 2
Path Summary:| Slack | 4.847 |
| Data Arrival Time | 5.380 |
| Data Required Time | 10.227 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Small.mem_Small.mem_0_3_s |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 7 | fifo_inst/Empty_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s4/I0 |
| 1.327 | 0.421 | tINS | RR | 10 | fifo_inst/rbin_num_next_2_s4/F |
| 1.627 | 0.300 | tNET | RR | 1 | fifo_inst/Small.rgraynext_2_s2/I1 |
| 2.040 | 0.413 | tINS | RR | 7 | fifo_inst/Small.rgraynext_2_s2/F |
| 2.340 | 0.300 | tNET | RR | 1 | fifo_inst/Small.rgraynext_3_s1/I1 |
| 2.753 | 0.413 | tINS | RR | 3 | fifo_inst/Small.rgraynext_3_s1/F |
| 3.053 | 0.300 | tNET | RR | 1 | fifo_inst/Small.rgraynext_4_s0/I1 |
| 3.466 | 0.413 | tINS | RR | 2 | fifo_inst/Small.rgraynext_4_s0/F |
| 3.766 | 0.300 | tNET | RR | 2 | fifo_inst/n681_s0/I0 |
| 4.211 | 0.445 | tINS | RF | 1 | fifo_inst/n681_s0/COUT |
| 4.211 | 0.000 | tNET | FF | 2 | fifo_inst/n682_s0/CIN |
| 4.251 | 0.040 | tINS | FR | 1 | fifo_inst/n682_s0/COUT |
| 4.251 | 0.000 | tNET | RR | 2 | fifo_inst/n683_s0/CIN |
| 4.291 | 0.040 | tINS | RR | 1 | fifo_inst/n683_s0/COUT |
| 4.291 | 0.000 | tNET | RR | 2 | fifo_inst/n684_s0/CIN |
| 4.331 | 0.040 | tINS | RR | 1 | fifo_inst/n684_s0/COUT |
| 4.331 | 0.000 | tNET | RR | 2 | fifo_inst/n685_s0/CIN |
| 4.371 | 0.040 | tINS | RR | 1 | fifo_inst/n685_s0/COUT |
| 4.371 | 0.000 | tNET | RR | 2 | fifo_inst/n686_s0/CIN |
| 4.411 | 0.040 | tINS | RR | 2 | fifo_inst/n686_s0/COUT |
| 4.711 | 0.300 | tNET | RR | 1 | fifo_inst/n37_s1/I2 |
| 5.080 | 0.369 | tINS | RR | 4 | fifo_inst/n37_s1/F |
| 5.380 | 0.300 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_3_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_3_s/CLKB |
| 10.227 | -0.073 | tSu | 1 | fifo_inst/Small.mem_Small.mem_0_3_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 2.674, 52.637%; route: 2.100, 41.339%; tC2Q: 0.306, 6.024% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 3
Path Summary:| Slack | 4.847 |
| Data Arrival Time | 5.380 |
| Data Required Time | 10.227 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Small.mem_Small.mem_0_2_s |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 7 | fifo_inst/Empty_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s4/I0 |
| 1.327 | 0.421 | tINS | RR | 10 | fifo_inst/rbin_num_next_2_s4/F |
| 1.627 | 0.300 | tNET | RR | 1 | fifo_inst/Small.rgraynext_2_s2/I1 |
| 2.040 | 0.413 | tINS | RR | 7 | fifo_inst/Small.rgraynext_2_s2/F |
| 2.340 | 0.300 | tNET | RR | 1 | fifo_inst/Small.rgraynext_3_s1/I1 |
| 2.753 | 0.413 | tINS | RR | 3 | fifo_inst/Small.rgraynext_3_s1/F |
| 3.053 | 0.300 | tNET | RR | 1 | fifo_inst/Small.rgraynext_4_s0/I1 |
| 3.466 | 0.413 | tINS | RR | 2 | fifo_inst/Small.rgraynext_4_s0/F |
| 3.766 | 0.300 | tNET | RR | 2 | fifo_inst/n681_s0/I0 |
| 4.211 | 0.445 | tINS | RF | 1 | fifo_inst/n681_s0/COUT |
| 4.211 | 0.000 | tNET | FF | 2 | fifo_inst/n682_s0/CIN |
| 4.251 | 0.040 | tINS | FR | 1 | fifo_inst/n682_s0/COUT |
| 4.251 | 0.000 | tNET | RR | 2 | fifo_inst/n683_s0/CIN |
| 4.291 | 0.040 | tINS | RR | 1 | fifo_inst/n683_s0/COUT |
| 4.291 | 0.000 | tNET | RR | 2 | fifo_inst/n684_s0/CIN |
| 4.331 | 0.040 | tINS | RR | 1 | fifo_inst/n684_s0/COUT |
| 4.331 | 0.000 | tNET | RR | 2 | fifo_inst/n685_s0/CIN |
| 4.371 | 0.040 | tINS | RR | 1 | fifo_inst/n685_s0/COUT |
| 4.371 | 0.000 | tNET | RR | 2 | fifo_inst/n686_s0/CIN |
| 4.411 | 0.040 | tINS | RR | 2 | fifo_inst/n686_s0/COUT |
| 4.711 | 0.300 | tNET | RR | 1 | fifo_inst/n37_s1/I2 |
| 5.080 | 0.369 | tINS | RR | 4 | fifo_inst/n37_s1/F |
| 5.380 | 0.300 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_2_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_2_s/CLKB |
| 10.227 | -0.073 | tSu | 1 | fifo_inst/Small.mem_Small.mem_0_2_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 2.674, 52.637%; route: 2.100, 41.339%; tC2Q: 0.306, 6.024% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 4
Path Summary:| Slack | 4.847 |
| Data Arrival Time | 5.380 |
| Data Required Time | 10.227 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Small.mem_Small.mem_0_1_s |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 7 | fifo_inst/Empty_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s4/I0 |
| 1.327 | 0.421 | tINS | RR | 10 | fifo_inst/rbin_num_next_2_s4/F |
| 1.627 | 0.300 | tNET | RR | 1 | fifo_inst/Small.rgraynext_2_s2/I1 |
| 2.040 | 0.413 | tINS | RR | 7 | fifo_inst/Small.rgraynext_2_s2/F |
| 2.340 | 0.300 | tNET | RR | 1 | fifo_inst/Small.rgraynext_3_s1/I1 |
| 2.753 | 0.413 | tINS | RR | 3 | fifo_inst/Small.rgraynext_3_s1/F |
| 3.053 | 0.300 | tNET | RR | 1 | fifo_inst/Small.rgraynext_4_s0/I1 |
| 3.466 | 0.413 | tINS | RR | 2 | fifo_inst/Small.rgraynext_4_s0/F |
| 3.766 | 0.300 | tNET | RR | 2 | fifo_inst/n681_s0/I0 |
| 4.211 | 0.445 | tINS | RF | 1 | fifo_inst/n681_s0/COUT |
| 4.211 | 0.000 | tNET | FF | 2 | fifo_inst/n682_s0/CIN |
| 4.251 | 0.040 | tINS | FR | 1 | fifo_inst/n682_s0/COUT |
| 4.251 | 0.000 | tNET | RR | 2 | fifo_inst/n683_s0/CIN |
| 4.291 | 0.040 | tINS | RR | 1 | fifo_inst/n683_s0/COUT |
| 4.291 | 0.000 | tNET | RR | 2 | fifo_inst/n684_s0/CIN |
| 4.331 | 0.040 | tINS | RR | 1 | fifo_inst/n684_s0/COUT |
| 4.331 | 0.000 | tNET | RR | 2 | fifo_inst/n685_s0/CIN |
| 4.371 | 0.040 | tINS | RR | 1 | fifo_inst/n685_s0/COUT |
| 4.371 | 0.000 | tNET | RR | 2 | fifo_inst/n686_s0/CIN |
| 4.411 | 0.040 | tINS | RR | 2 | fifo_inst/n686_s0/COUT |
| 4.711 | 0.300 | tNET | RR | 1 | fifo_inst/n37_s1/I2 |
| 5.080 | 0.369 | tINS | RR | 4 | fifo_inst/n37_s1/F |
| 5.380 | 0.300 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_1_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_1_s/CLKB |
| 10.227 | -0.073 | tSu | 1 | fifo_inst/Small.mem_Small.mem_0_1_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 2.674, 52.637%; route: 2.100, 41.339%; tC2Q: 0.306, 6.024% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 5
Path Summary:| Slack | 4.847 |
| Data Arrival Time | 5.380 |
| Data Required Time | 10.227 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Small.mem_Small.mem_0_0_s |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 7 | fifo_inst/Empty_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s4/I0 |
| 1.327 | 0.421 | tINS | RR | 10 | fifo_inst/rbin_num_next_2_s4/F |
| 1.627 | 0.300 | tNET | RR | 1 | fifo_inst/Small.rgraynext_2_s2/I1 |
| 2.040 | 0.413 | tINS | RR | 7 | fifo_inst/Small.rgraynext_2_s2/F |
| 2.340 | 0.300 | tNET | RR | 1 | fifo_inst/Small.rgraynext_3_s1/I1 |
| 2.753 | 0.413 | tINS | RR | 3 | fifo_inst/Small.rgraynext_3_s1/F |
| 3.053 | 0.300 | tNET | RR | 1 | fifo_inst/Small.rgraynext_4_s0/I1 |
| 3.466 | 0.413 | tINS | RR | 2 | fifo_inst/Small.rgraynext_4_s0/F |
| 3.766 | 0.300 | tNET | RR | 2 | fifo_inst/n681_s0/I0 |
| 4.211 | 0.445 | tINS | RF | 1 | fifo_inst/n681_s0/COUT |
| 4.211 | 0.000 | tNET | FF | 2 | fifo_inst/n682_s0/CIN |
| 4.251 | 0.040 | tINS | FR | 1 | fifo_inst/n682_s0/COUT |
| 4.251 | 0.000 | tNET | RR | 2 | fifo_inst/n683_s0/CIN |
| 4.291 | 0.040 | tINS | RR | 1 | fifo_inst/n683_s0/COUT |
| 4.291 | 0.000 | tNET | RR | 2 | fifo_inst/n684_s0/CIN |
| 4.331 | 0.040 | tINS | RR | 1 | fifo_inst/n684_s0/COUT |
| 4.331 | 0.000 | tNET | RR | 2 | fifo_inst/n685_s0/CIN |
| 4.371 | 0.040 | tINS | RR | 1 | fifo_inst/n685_s0/COUT |
| 4.371 | 0.000 | tNET | RR | 2 | fifo_inst/n686_s0/CIN |
| 4.411 | 0.040 | tINS | RR | 2 | fifo_inst/n686_s0/COUT |
| 4.711 | 0.300 | tNET | RR | 1 | fifo_inst/n37_s1/I2 |
| 5.080 | 0.369 | tINS | RR | 4 | fifo_inst/n37_s1/F |
| 5.380 | 0.300 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_0_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 63 | RdClk_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | fifo_inst/Small.mem_Small.mem_0_0_s/CLKB |
| 10.227 | -0.073 | tSu | 1 | fifo_inst/Small.mem_Small.mem_0_0_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 2.674, 52.637%; route: 2.100, 41.339%; tC2Q: 0.306, 6.024% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |