Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\ACM2108\DDS_Module.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\ACM2108\acm2108_test.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\ACM2108\key_filter.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\ACM2108\sin_rom_a8d8.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\ACM2108\square_wave_rom_a8d8.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\ACM2108\triangular_rom_a8d8.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\FX2_CDC_Loopback.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\SPI_Slave.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\acm2108_ddr3_CDC.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\ad_8bit_to_16bit.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\cdc_cmd.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\cmd_ctrl.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\ddr3_ctrl_2port\ddr3_ctrl_2port.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\ddr3_ctrl_2port\fifo_ddr3_adapter.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\ddr3_memory_interface\ddr3_memory_interface.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\ddr_pll\ddr_pll.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\ddr_pll\ddr_pll_mod.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\fifo_in\fifo_in.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\fifo_top\fifo_top.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\gowin_pll\gowin_pll.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\gowin_pll\gowin_pll_mod.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\hc595_driver.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\hex8.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\pll_init.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\rd_data_fifo\rd_data_fifo.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\speed_ctrl.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\state_ctrl.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\wr_data_fifo\wr_data_fifo.v C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\pll_mDRP_intf.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12 (64-bit) |
| Part Number | GW5AT-LV60PG484AC1/I0 |
| Device | GW5AT-60 |
| Device Version | B |
| Created Time | Tue Oct 14 10:19:11 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | acm2108_ddr3_CDC |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 0.978s, Peak memory usage = 2085.566MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.687s, Elapsed time = 0h 0m 0.69s, Peak memory usage = 2085.566MB Optimizing Phase 1: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.368s, Peak memory usage = 2085.566MB Optimizing Phase 2: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.622s, Peak memory usage = 2085.566MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.345s, Peak memory usage = 2085.566MB Inferring Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 2085.566MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 2085.566MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 2085.566MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.612s, Peak memory usage = 2085.566MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.143s, Peak memory usage = 2085.566MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 2085.566MB Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 2085.566MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.609s, Elapsed time = 0h 0m 0.703s, Peak memory usage = 2085.566MB Generate output files: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.448s, Peak memory usage = 2085.566MB |
| Total Time and Memory Usage | CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 2085.566MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 114 |
| I/O Buf | 111 |
| IBUF | 26 |
| OBUF | 56 |
| TBUF | 2 |
| IOBUF | 24 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 5278 |
| DFFSE | 3 |
| DFFRE | 1063 |
| DFFPE | 107 |
| DFFCE | 4105 |
| LUT | 4591 |
| LUT2 | 665 |
| LUT3 | 1817 |
| LUT4 | 2109 |
| ALU | 378 |
| ALU | 378 |
| INV | 53 |
| INV | 53 |
| IOLOGIC | 76 |
| IDES8_MEM | 16 |
| OSER8 | 24 |
| OSER8_MEM | 20 |
| IODELAY | 16 |
| BSRAM | 24 |
| SDPB | 17 |
| SDPX9B | 4 |
| pROM | 3 |
| CLOCK | 6 |
| CLKDIV | 1 |
| DQS | 2 |
| DDRDLL | 1 |
| PLLA | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 5022(4644 LUT, 378 ALU) / 59904 | 9% |
| Register | 5278 / 60780 | 9% |
| --Register as Latch | 0 / 60780 | 0% |
| --Register as FF | 5278 / 60780 | 9% |
| BSRAM | 24 / 118 | 21% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | fx2_ifclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | fx2_ifclk_ibuf/I | ||
| 3 | SPI_SCLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | SPI_SCLK_ibuf/I | ||
| 4 | FX2_CDC_Loopback/hex8/clk_1K | Base | 10.000 | 100.000 | 0.000 | 5.000 | FX2_CDC_Loopback/hex8/clk_1K_s1/Q | ||
| 5 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 8.000 | 125.000 | 0.000 | 4.000 | clk_ibuf/I | clk | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 6 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | clk | Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 7 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | Generated | 2.500 | 400.000 | 0.000 | 1.250 | clk_ibuf/I | clk | ddr_pll/u_pll/PLLA_inst/CLKOUT2 |
| 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | ddr_pll/u_pll/PLLA_inst/CLKOUT2 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 135.731(MHz) | 8 | TOP |
| 2 | fx2_ifclk | 100.000(MHz) | 117.165(MHz) | 11 | TOP |
| 3 | SPI_SCLK | 100.000(MHz) | 289.331(MHz) | 4 | TOP |
| 4 | FX2_CDC_Loopback/hex8/clk_1K | 100.000(MHz) | 294.551(MHz) | 4 | TOP |
| 5 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | 125.000(MHz) | 190.340(MHz) | 6 | TOP |
| 6 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | 400.000(MHz) | 1164.144(MHz) | 1 | TOP |
| 7 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 100.000(MHz) | 173.160(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -1.034 |
| Data Arrival Time | 2.396 |
| Data Required Time | 1.363 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0 |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.362 | 0.362 | tCL | RR | 3689 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.737 | 0.375 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK |
| 1.120 | 0.382 | tC2Q | RR | 11 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q |
| 1.495 | 0.375 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0 |
| 2.021 | 0.526 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
| 2.396 | 0.375 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.250 | 0.000 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 1.531 | 0.281 | tCL | FF | 64 | ddr_pll/u_pll/PLLA_inst/CLKOUT2 |
| 1.882 | 0.350 | tNET | FF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 1.847 | -0.035 | tUnc | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 1.363 | -0.484 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.106 |
| Setup Relationship: | 1.250 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:| Slack | -1.034 |
| Data Arrival Time | 2.396 |
| Data Required Time | 1.363 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0 |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.362 | 0.362 | tCL | RR | 3689 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.737 | 0.375 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK |
| 1.120 | 0.382 | tC2Q | RR | 11 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q |
| 1.495 | 0.375 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0 |
| 2.021 | 0.526 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
| 2.396 | 0.375 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.250 | 0.000 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 1.531 | 0.281 | tCL | FF | 64 | ddr_pll/u_pll/PLLA_inst/CLKOUT2 |
| 1.882 | 0.350 | tNET | FF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 1.847 | -0.035 | tUnc | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 1.363 | -0.484 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.106 |
| Setup Relationship: | 1.250 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:| Slack | -1.016 |
| Data Arrival Time | 25.574 |
| Data Required Time | 24.558 |
| From | acm2108_test/MODE_0_s1 |
| To | acm2108_test/DDS_Module/DA_Data_0_s1 |
| Launch Clk | clk[R] |
| Latch Clk | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 842 | clk_ibuf/O |
| 20.375 | 0.375 | tNET | RR | 1 | acm2108_test/MODE_0_s1/CLK |
| 20.757 | 0.382 | tC2Q | RR | 36 | acm2108_test/MODE_0_s1/Q |
| 21.132 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/n81_s37/I2 |
| 21.594 | 0.461 | tINS | RR | 2 | acm2108_test/DDS_Module/n81_s37/F |
| 21.969 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/n81_s33/I0 |
| 22.495 | 0.526 | tINS | RR | 2 | acm2108_test/DDS_Module/n81_s33/F |
| 22.870 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/n81_s41/I0 |
| 23.396 | 0.526 | tINS | RR | 1 | acm2108_test/DDS_Module/n81_s41/F |
| 23.771 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/n81_s42/I0 |
| 24.298 | 0.526 | tINS | RR | 1 | acm2108_test/DDS_Module/n81_s42/F |
| 24.673 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/n81_s38/I0 |
| 25.199 | 0.526 | tINS | RR | 1 | acm2108_test/DDS_Module/n81_s38/F |
| 25.574 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 24.000 | 0.000 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 24.281 | 0.281 | tCL | RR | 66 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 24.656 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_0_s1/CLK |
| 24.622 | -0.035 | tUnc | acm2108_test/DDS_Module/DA_Data_0_s1 | ||
| 24.558 | -0.064 | tSu | 1 | acm2108_test/DDS_Module/DA_Data_0_s1 |
| Clock Skew: | 0.281 |
| Setup Relationship: | 4.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.566, 49.362%; route: 2.250, 43.280%; tC2Q: 0.382, 7.358% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:| Slack | -1.016 |
| Data Arrival Time | 25.574 |
| Data Required Time | 24.558 |
| From | acm2108_test/MODE_0_s1 |
| To | acm2108_test/DDS_Module/DA_Data_1_s1 |
| Launch Clk | clk[R] |
| Latch Clk | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 842 | clk_ibuf/O |
| 20.375 | 0.375 | tNET | RR | 1 | acm2108_test/MODE_0_s1/CLK |
| 20.757 | 0.382 | tC2Q | RR | 36 | acm2108_test/MODE_0_s1/Q |
| 21.132 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/n80_s37/I2 |
| 21.594 | 0.461 | tINS | RR | 2 | acm2108_test/DDS_Module/n80_s37/F |
| 21.969 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/n80_s33/I0 |
| 22.495 | 0.526 | tINS | RR | 2 | acm2108_test/DDS_Module/n80_s33/F |
| 22.870 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/n80_s41/I0 |
| 23.396 | 0.526 | tINS | RR | 1 | acm2108_test/DDS_Module/n80_s41/F |
| 23.771 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/n80_s42/I0 |
| 24.298 | 0.526 | tINS | RR | 1 | acm2108_test/DDS_Module/n80_s42/F |
| 24.673 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/n80_s38/I0 |
| 25.199 | 0.526 | tINS | RR | 1 | acm2108_test/DDS_Module/n80_s38/F |
| 25.574 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 24.000 | 0.000 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 24.281 | 0.281 | tCL | RR | 66 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 24.656 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_1_s1/CLK |
| 24.622 | -0.035 | tUnc | acm2108_test/DDS_Module/DA_Data_1_s1 | ||
| 24.558 | -0.064 | tSu | 1 | acm2108_test/DDS_Module/DA_Data_1_s1 |
| Clock Skew: | 0.281 |
| Setup Relationship: | 4.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.566, 49.362%; route: 2.250, 43.280%; tC2Q: 0.382, 7.358% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:| Slack | -1.016 |
| Data Arrival Time | 25.574 |
| Data Required Time | 24.558 |
| From | acm2108_test/MODE_0_s1 |
| To | acm2108_test/DDS_Module/DA_Data_2_s1 |
| Launch Clk | clk[R] |
| Latch Clk | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 842 | clk_ibuf/O |
| 20.375 | 0.375 | tNET | RR | 1 | acm2108_test/MODE_0_s1/CLK |
| 20.757 | 0.382 | tC2Q | RR | 36 | acm2108_test/MODE_0_s1/Q |
| 21.132 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/n79_s37/I2 |
| 21.594 | 0.461 | tINS | RR | 2 | acm2108_test/DDS_Module/n79_s37/F |
| 21.969 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/n79_s33/I0 |
| 22.495 | 0.526 | tINS | RR | 2 | acm2108_test/DDS_Module/n79_s33/F |
| 22.870 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/n79_s41/I0 |
| 23.396 | 0.526 | tINS | RR | 1 | acm2108_test/DDS_Module/n79_s41/F |
| 23.771 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/n79_s42/I0 |
| 24.298 | 0.526 | tINS | RR | 1 | acm2108_test/DDS_Module/n79_s42/F |
| 24.673 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/n79_s38/I0 |
| 25.199 | 0.526 | tINS | RR | 1 | acm2108_test/DDS_Module/n79_s38/F |
| 25.574 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 24.000 | 0.000 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 24.281 | 0.281 | tCL | RR | 66 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 24.656 | 0.375 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_2_s1/CLK |
| 24.622 | -0.035 | tUnc | acm2108_test/DDS_Module/DA_Data_2_s1 | ||
| 24.558 | -0.064 | tSu | 1 | acm2108_test/DDS_Module/DA_Data_2_s1 |
| Clock Skew: | 0.281 |
| Setup Relationship: | 4.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.566, 49.362%; route: 2.250, 43.280%; tC2Q: 0.382, 7.358% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |