Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\wr_data_fifo\temp\FIFO\fifo_define.v
C:\Users\24165\Desktop\acm2108_ddr3_CDC\src\wr_data_fifo\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12 (64-bit)
Part Number GW5AT-LV60PG484AC1/I0
Device GW5AT-60
Device Version B
Created Time Tue Oct 14 09:09:35 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module wr_data_fifo
Synthesis Process Running parser:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.332s, Peak memory usage = 77.223MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 77.223MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 77.223MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 77.223MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 77.223MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 77.223MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.223MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.223MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 77.223MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 77.223MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 77.223MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.223MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.336s, Peak memory usage = 92.215MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 92.215MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 92.215MB
Total Time and Memory Usage CPU time = 0h 0m 0.668s, Elapsed time = 0h 0m 0.72s, Peak memory usage = 92.215MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 176
I/O Buf 176
    IBUF 21
    OBUF 155
Register 112
    DFFPE 6
    DFFCE 106
LUT 93
    LUT2 21
    LUT3 28
    LUT4 44
ALU 30
    ALU 30
INV 3
    INV 3
BSRAM 4
    SDPB 4

Resource Utilization Summary

Resource Usage Utilization
Logic 126(96 LUT, 30 ALU) / 59904 <1%
Register 112 / 60780 <1%
  --Register as Latch 0 / 60780 0%
  --Register as FF 112 / 60780 <1%
BSRAM 4 / 118 4%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 138.026(MHz) 9 TOP
2 WrClk 100.000(MHz) 147.113(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.755
Data Arrival Time 7.556
Data Required Time 10.311
From fifo_inst/Big.rq2_wptr_6_s0
To fifo_inst/Almost_Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 57 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Big.rq2_wptr_6_s0/CLK
0.757 0.382 tC2Q RR 2 fifo_inst/Big.rq2_wptr_6_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/Big.wcount_r_6_s1/I0
1.659 0.526 tINS RR 3 fifo_inst/Big.wcount_r_6_s1/F
2.034 0.375 tNET RR 1 fifo_inst/Big.wcount_r_5_s0/I1
2.550 0.516 tINS RR 2 fifo_inst/Big.wcount_r_5_s0/F
2.925 0.375 tNET RR 1 fifo_inst/Big.wcount_r_4_s0/I1
3.441 0.516 tINS RR 1 fifo_inst/Big.wcount_r_4_s0/F
3.816 0.375 tNET RR 2 fifo_inst/rcnt_sub_4_s/I0
4.373 0.556 tINS RF 1 fifo_inst/rcnt_sub_4_s/COUT
4.373 0.000 tNET FF 2 fifo_inst/rcnt_sub_5_s/CIN
4.423 0.050 tINS FR 1 fifo_inst/rcnt_sub_5_s/COUT
4.423 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
4.473 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
4.473 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
4.523 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
4.523 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
4.573 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
4.573 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
4.816 0.244 tINS RR 2 fifo_inst/rcnt_sub_9_s/SUM
5.191 0.375 tNET RR 1 fifo_inst/arempty_val_s2/I1
5.708 0.516 tINS RR 1 fifo_inst/arempty_val_s2/F
6.083 0.375 tNET RR 1 fifo_inst/arempty_val_s1/I2
6.544 0.461 tINS RR 1 fifo_inst/arempty_val_s1/F
6.919 0.375 tNET RR 1 fifo_inst/arempty_val_s0/I3
7.181 0.262 tINS RR 1 fifo_inst/arempty_val_s0/F
7.556 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 57 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Almost_Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.799, 52.899%; route: 3.000, 41.775%; tC2Q: 0.382, 5.326%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 3.202
Data Arrival Time 7.109
Data Required Time 10.311
From fifo_inst/Big.wq2_rptr_6_s0
To fifo_inst/Almost_Full_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 63 WrClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Big.wq2_rptr_6_s0/CLK
0.757 0.382 tC2Q RR 2 fifo_inst/Big.wq2_rptr_6_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/Big.rcount_w_1_9_s1/I0
1.659 0.526 tINS RR 4 fifo_inst/Big.rcount_w_1_9_s1/F
2.034 0.375 tNET RR 1 fifo_inst/Big.rcount_w_1_6_s0/I3
2.296 0.262 tINS RR 4 fifo_inst/Big.rcount_w_1_6_s0/F
2.671 0.375 tNET RR 1 fifo_inst/Big.rcount_w_1_5_s0/I1
3.188 0.516 tINS RR 1 fifo_inst/Big.rcount_w_1_5_s0/F
3.562 0.375 tNET RR 2 fifo_inst/wcnt_sub_5_s/I1
4.125 0.562 tINS RF 1 fifo_inst/wcnt_sub_5_s/COUT
4.125 0.000 tNET FF 2 fifo_inst/wcnt_sub_6_s/CIN
4.369 0.244 tINS FR 2 fifo_inst/wcnt_sub_6_s/SUM
4.744 0.375 tNET RR 1 fifo_inst/awfull_val_s3/I1
5.260 0.516 tINS RR 1 fifo_inst/awfull_val_s3/F
5.635 0.375 tNET RR 1 fifo_inst/awfull_val_s2/I2
6.096 0.461 tINS RR 1 fifo_inst/awfull_val_s2/F
6.471 0.375 tNET RR 1 fifo_inst/awfull_val_s0/I3
6.734 0.262 tINS RR 1 fifo_inst/awfull_val_s0/F
7.109 0.375 tNET RR 1 fifo_inst/Almost_Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 63 WrClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Almost_Full_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Almost_Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.351, 49.768%; route: 3.000, 44.552%; tC2Q: 0.382, 5.680%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 4.035
Data Arrival Time 6.276
Data Required Time 10.311
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 57 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s5/I0
1.659 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s5/F
2.034 0.375 tNET RR 1 fifo_inst/Big.rgraynext_5_s1/I3
2.296 0.262 tINS RR 7 fifo_inst/Big.rgraynext_5_s1/F
2.671 0.375 tNET RR 1 fifo_inst/rbin_num_next_7_s4/I2
3.133 0.461 tINS RR 7 fifo_inst/rbin_num_next_7_s4/F
3.508 0.375 tNET RR 1 fifo_inst/Big.rgraynext_7_s0/I2
3.969 0.461 tINS RR 2 fifo_inst/Big.rgraynext_7_s0/F
4.344 0.375 tNET RR 2 fifo_inst/n682_s0/I0
4.900 0.556 tINS RF 1 fifo_inst/n682_s0/COUT
4.900 0.000 tNET FF 2 fifo_inst/n683_s0/CIN
4.950 0.050 tINS FR 1 fifo_inst/n683_s0/COUT
4.950 0.000 tNET RR 2 fifo_inst/n684_s0/CIN
5.000 0.050 tINS RR 2 fifo_inst/n684_s0/COUT
5.375 0.375 tNET RR 1 fifo_inst/rempty_val_s1/I0
5.901 0.526 tINS RR 1 fifo_inst/rempty_val_s1/F
6.276 0.375 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 57 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.894, 49.036%; route: 2.625, 44.482%; tC2Q: 0.382, 6.482%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 4.072
Data Arrival Time 6.211
Data Required Time 10.284
From fifo_inst/Empty_s0
To fifo_inst/Big.mem_Big.mem_0_3_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 57 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s5/I0
1.659 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s5/F
2.034 0.375 tNET RR 1 fifo_inst/Big.rgraynext_5_s1/I3
2.296 0.262 tINS RR 7 fifo_inst/Big.rgraynext_5_s1/F
2.671 0.375 tNET RR 1 fifo_inst/rbin_num_next_7_s4/I2
3.133 0.461 tINS RR 7 fifo_inst/rbin_num_next_7_s4/F
3.508 0.375 tNET RR 1 fifo_inst/Big.rgraynext_7_s0/I2
3.969 0.461 tINS RR 2 fifo_inst/Big.rgraynext_7_s0/F
4.344 0.375 tNET RR 2 fifo_inst/n682_s0/I0
4.900 0.556 tINS RF 1 fifo_inst/n682_s0/COUT
4.900 0.000 tNET FF 2 fifo_inst/n683_s0/CIN
4.950 0.050 tINS FR 1 fifo_inst/n683_s0/COUT
4.950 0.000 tNET RR 2 fifo_inst/n684_s0/CIN
5.000 0.050 tINS RR 2 fifo_inst/n684_s0/COUT
5.375 0.375 tNET RR 1 fifo_inst/n34_s1/I2
5.836 0.461 tINS RR 4 fifo_inst/n34_s1/F
6.211 0.375 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_3_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 57 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_3_s/CLKB
10.284 -0.091 tSu 1 fifo_inst/Big.mem_Big.mem_0_3_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.829, 48.468%; route: 2.625, 44.978%; tC2Q: 0.382, 6.554%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 4.072
Data Arrival Time 6.211
Data Required Time 10.284
From fifo_inst/Empty_s0
To fifo_inst/Big.mem_Big.mem_0_2_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 57 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s5/I0
1.659 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s5/F
2.034 0.375 tNET RR 1 fifo_inst/Big.rgraynext_5_s1/I3
2.296 0.262 tINS RR 7 fifo_inst/Big.rgraynext_5_s1/F
2.671 0.375 tNET RR 1 fifo_inst/rbin_num_next_7_s4/I2
3.133 0.461 tINS RR 7 fifo_inst/rbin_num_next_7_s4/F
3.508 0.375 tNET RR 1 fifo_inst/Big.rgraynext_7_s0/I2
3.969 0.461 tINS RR 2 fifo_inst/Big.rgraynext_7_s0/F
4.344 0.375 tNET RR 2 fifo_inst/n682_s0/I0
4.900 0.556 tINS RF 1 fifo_inst/n682_s0/COUT
4.900 0.000 tNET FF 2 fifo_inst/n683_s0/CIN
4.950 0.050 tINS FR 1 fifo_inst/n683_s0/COUT
4.950 0.000 tNET RR 2 fifo_inst/n684_s0/CIN
5.000 0.050 tINS RR 2 fifo_inst/n684_s0/COUT
5.375 0.375 tNET RR 1 fifo_inst/n34_s1/I2
5.836 0.461 tINS RR 4 fifo_inst/n34_s1/F
6.211 0.375 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_2_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 57 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_2_s/CLKB
10.284 -0.091 tSu 1 fifo_inst/Big.mem_Big.mem_0_2_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.829, 48.468%; route: 2.625, 44.978%; tC2Q: 0.382, 6.554%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%