Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\DVP_Capture\DVP_Capture.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\camera_init\camera_init.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\camera_init\i2c_control\i2c_bit_shift.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\camera_init\i2c_control\i2c_control.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\camera_init\ov5640_init_table_jpeg.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\camera_init\ov5640_init_table_rgb.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\camera_pll\camera_pll.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\camera_pll\camera_pll_mod.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\ddr3_ctrl_2port\ddr3_ctrl_2port.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\ddr3_ctrl_2port\fifo_ddr3_adapter.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\ddr3_memory_interface\ddr3_memory_interface.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\ddr_pll\ddr_pll.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\ddr_pll\ddr_pll_mod.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\dvi_tx\dvi_tx.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\gowin_ddr\gowin_ddr.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\ov5640_ddr3_hdmi.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\pll_init.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\pll_mDRP_intf.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\rd_data_fifo\rd_data_fifo.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\vga\disp_driver.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\vga\disp_parameter_cfg.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\vga\dvi_encoder.v C:\Users\24165\Desktop\ch43_ov5640_ddr3_hdmi\src\wr_data_fifo\wr_data_fifo.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12 (64-bit) |
| Part Number | GW5A-EV25UG324SC2/I1 |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Fri Oct 17 11:19:42 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | gao_ov5640_ddr_hdmi |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 756.578MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.703s, Elapsed time = 0h 0m 0.718s, Peak memory usage = 756.578MB Optimizing Phase 1: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.321s, Peak memory usage = 756.578MB Optimizing Phase 2: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.6s, Peak memory usage = 756.578MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.264s, Peak memory usage = 756.578MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 756.578MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 756.578MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 756.578MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.402s, Peak memory usage = 756.578MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.117s, Peak memory usage = 756.578MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 756.578MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 756.578MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.463s, Peak memory usage = 756.578MB Generate output files: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.325s, Peak memory usage = 756.578MB |
| Total Time and Memory Usage | CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 756.578MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 78 |
| I/O Buf | 71 |
| IBUF | 13 |
| OBUF | 32 |
| TBUF | 2 |
| IOBUF | 17 |
| TLVDS_OBUF | 4 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 4239 |
| DFFSE | 4 |
| DFFRE | 478 |
| DFFPE | 84 |
| DFFCE | 3673 |
| LUT | 3736 |
| LUT2 | 541 |
| LUT3 | 1397 |
| LUT4 | 1798 |
| ALU | 270 |
| ALU | 270 |
| INV | 47 |
| INV | 47 |
| IOLOGIC | 80 |
| IDES8_MEM | 16 |
| OSER8 | 24 |
| OSER8_MEM | 20 |
| OSER10 | 4 |
| IODELAY | 16 |
| BSRAM | 19 |
| SDPB | 12 |
| SDPX9B | 4 |
| pROM | 3 |
| CLOCK | 7 |
| CLKDIV | 2 |
| DQS | 2 |
| DDRDLL | 1 |
| PLLA | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 4053(3783 LUT, 270 ALU) / 23040 | 18% |
| Register | 4239 / 23736 | 18% |
| --Register as Latch | 0 / 23736 | 0% |
| --Register as FF | 4239 / 23736 | 18% |
| BSRAM | 19 / 56 | 34% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk50M | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk50M_ibuf/I | ||
| 2 | camera_pclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | camera_pclk_ibuf/I | ||
| 3 | your_instance_name/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 2.667 | 375.000 | 0.000 | 1.333 | clk50M_ibuf/I | clk50M | your_instance_name/u_pll/PLLA_inst/CLKOUT0 |
| 4 | your_instance_name/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | clk50M_ibuf/I | clk50M | your_instance_name/u_pll/PLLA_inst/CLKOUT1 |
| 5 | your_instance_name/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | clk50M_ibuf/I | clk50M | your_instance_name/u_pll/PLLA_inst/CLKOUT2 |
| 6 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | Generated | 2.500 | 400.000 | 0.000 | 1.250 | clk50M_ibuf/I | clk50M | ddr_pll/u_pll/PLLA_inst/CLKOUT2 |
| 7 | u_clkdiv/CLKOUT.default_gen_clk | Generated | 13.333 | 75.000 | 0.000 | 6.667 | your_instance_name/u_pll/PLLA_inst/CLKOUT0 | your_instance_name/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | u_clkdiv/CLKOUT |
| 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | ddr_pll/u_pll/PLLA_inst/CLKOUT2 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk50M | 50.000(MHz) | 227.324(MHz) | 7 | TOP |
| 2 | camera_pclk | 100.000(MHz) | 205.973(MHz) | 7 | TOP |
| 3 | your_instance_name/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | 50.000(MHz) | 232.775(MHz) | 6 | TOP |
| 4 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | 400.000(MHz) | 1394.296(MHz) | 1 | TOP |
| 5 | u_clkdiv/CLKOUT.default_gen_clk | 75.000(MHz) | 138.102(MHz) | 10 | TOP |
| 6 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 100.000(MHz) | 216.450(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -0.595 |
| Data Arrival Time | 1.917 |
| Data Required Time | 1.322 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0 |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.290 | 0.290 | tCL | RR | 3689 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.590 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK |
| 0.896 | 0.306 | tC2Q | RR | 11 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q |
| 1.196 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0 |
| 1.617 | 0.421 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
| 1.917 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.250 | 0.000 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 1.494 | 0.244 | tCL | FF | 64 | ddr_pll/u_pll/PLLA_inst/CLKOUT2 |
| 1.774 | 0.280 | tNET | FF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 1.739 | -0.035 | tUnc | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 1.322 | -0.417 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.066 |
| Setup Relationship: | 1.250 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 0.421, 31.726%; route: 0.600, 45.214%; tC2Q: 0.306, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 2
Path Summary:| Slack | -0.595 |
| Data Arrival Time | 1.917 |
| Data Required Time | 1.322 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0 |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.290 | 0.290 | tCL | RR | 3689 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.590 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK |
| 0.896 | 0.306 | tC2Q | RR | 11 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q |
| 1.196 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0 |
| 1.617 | 0.421 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
| 1.917 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.250 | 0.000 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 1.494 | 0.244 | tCL | FF | 64 | ddr_pll/u_pll/PLLA_inst/CLKOUT2 |
| 1.774 | 0.280 | tNET | FF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 1.739 | -0.035 | tUnc | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 1.322 | -0.417 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.066 |
| Setup Relationship: | 1.250 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 0.421, 31.726%; route: 0.600, 45.214%; tC2Q: 0.306, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 3
Path Summary:| Slack | 1.783 |
| Data Arrival Time | 1.261 |
| Data Required Time | 3.044 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem |
| Launch Clk | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| Latch Clk | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 0.244 | 0.244 | tCL | RR | 64 | ddr_pll/u_pll/PLLA_inst/CLKOUT2 |
| 0.544 | 0.300 | tNET | RR | 5 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.961 | 0.417 | tC2Q | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] |
| 1.261 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 2.500 | 0.000 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 2.744 | 0.244 | tCL | RR | 64 | ddr_pll/u_pll/PLLA_inst/CLKOUT2 |
| 3.044 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK |
| 3.044 | 0.000 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem |
| Clock Skew: | 0.000 |
| Setup Relationship: | 2.500 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.300, 41.829%; tC2Q: 0.417, 58.171% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 4
Path Summary:| Slack | 1.783 |
| Data Arrival Time | 1.261 |
| Data Required Time | 3.044 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem |
| Launch Clk | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| Latch Clk | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 0.244 | 0.244 | tCL | RR | 64 | ddr_pll/u_pll/PLLA_inst/CLKOUT2 |
| 0.544 | 0.300 | tNET | RR | 5 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.961 | 0.417 | tC2Q | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] |
| 1.261 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[1] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 2.500 | 0.000 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 2.744 | 0.244 | tCL | RR | 64 | ddr_pll/u_pll/PLLA_inst/CLKOUT2 |
| 3.044 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK |
| 3.044 | 0.000 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem |
| Clock Skew: | 0.000 |
| Setup Relationship: | 2.500 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.300, 41.829%; tC2Q: 0.417, 58.171% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 5
Path Summary:| Slack | 1.783 |
| Data Arrival Time | 1.261 |
| Data Required Time | 3.044 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem |
| Launch Clk | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| Latch Clk | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 0.244 | 0.244 | tCL | RR | 64 | ddr_pll/u_pll/PLLA_inst/CLKOUT2 |
| 0.544 | 0.300 | tNET | RR | 5 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 0.961 | 0.417 | tC2Q | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] |
| 1.261 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[0] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 2.500 | 0.000 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 2.744 | 0.244 | tCL | RR | 64 | ddr_pll/u_pll/PLLA_inst/CLKOUT2 |
| 3.044 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK |
| 3.044 | 0.000 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem |
| Clock Skew: | 0.000 |
| Setup Relationship: | 2.500 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.300, 41.829%; tC2Q: 0.417, 58.171% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |