Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\DVI_TX\data\dvi_tx_top.v D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\DVI_TX\data\rgb2dvi.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12 (64-bit) |
| Part Number | GW5A-EV25UG324SC2/I1 |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Thu Oct 16 17:08:36 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | DVI_TX_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.14s, Peak memory usage = 69.441MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 69.441MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 69.441MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 69.441MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 69.441MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 69.441MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 69.441MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 69.441MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 69.441MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 69.441MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 69.441MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 69.441MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 94.918MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 94.918MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 94.918MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 94.918MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 38 |
| I/O Buf | 34 |
| IBUF | 30 |
| TLVDS_OBUF | 4 |
| Register | 73 |
| DFFPE | 3 |
| DFFCE | 70 |
| LUT | 225 |
| LUT2 | 35 |
| LUT3 | 57 |
| LUT4 | 133 |
| ALU | 69 |
| ALU | 69 |
| INV | 4 |
| INV | 4 |
| IOLOGIC | 4 |
| OSER10 | 4 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 298(229 LUT, 69 ALU) / 23040 | 2% |
| Register | 73 / 23736 | <1% |
| --Register as Latch | 0 / 23736 | 0% |
| --Register as FF | 73 / 23736 | <1% |
| BSRAM | 0 / 56 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | I_rgb_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | I_rgb_clk_ibuf/I | ||
| 2 | I_serial_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | I_serial_clk_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_rgb_clk | 100.000(MHz) | 138.102(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 2.759 |
| Data Arrival Time | 7.490 |
| Data Required Time | 10.249 |
| From | rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0 |
| To | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 |
| Launch Clk | I_rgb_clk[R] |
| Latch Clk | I_rgb_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_rgb_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 3 | rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/I0 |
| 1.327 | 0.421 | tINS | RR | 5 | rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/F |
| 1.627 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n686_s2/I1 |
| 2.040 | 0.413 | tINS | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n686_s2/F |
| 2.340 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/I0 |
| 2.761 | 0.421 | tINS | RR | 4 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/F |
| 3.061 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/I2 |
| 3.430 | 0.369 | tINS | RR | 3 | rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/F |
| 3.730 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/I0 |
| 4.151 | 0.421 | tINS | RR | 4 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/F |
| 4.451 | 0.300 | tNET | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/I1 |
| 5.035 | 0.584 | tINS | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/SUM |
| 5.335 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6/I0 |
| 5.756 | 0.421 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6/F |
| 6.056 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3/I0 |
| 6.477 | 0.421 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3/F |
| 6.777 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/I1 |
| 7.190 | 0.413 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/F |
| 7.490 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_rgb_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/CLK |
| 10.249 | -0.051 | tSu | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 3.884, 54.019%; route: 3.000, 41.725%; tC2Q: 0.306, 4.256% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 2
Path Summary:| Slack | 3.436 |
| Data Arrival Time | 6.813 |
| Data Required Time | 10.249 |
| From | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_0_s0 |
| To | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 |
| Launch Clk | I_rgb_clk[R] |
| Latch Clk | I_rgb_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_rgb_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_0_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 12 | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_0_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s21/I0 |
| 1.327 | 0.421 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s21/F |
| 1.627 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s19/I1 |
| 2.040 | 0.413 | tINS | RR | 4 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s19/F |
| 2.340 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/I0 |
| 2.761 | 0.421 | tINS | RR | 3 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17/F |
| 3.061 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I1 |
| 3.474 | 0.413 | tINS | RR | 5 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F |
| 3.774 | 0.300 | tNET | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/I1 |
| 4.358 | 0.584 | tINS | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/SUM |
| 4.658 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6/I0 |
| 5.079 | 0.421 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6/F |
| 5.379 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3/I0 |
| 5.800 | 0.421 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3/F |
| 6.100 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1/I1 |
| 6.513 | 0.413 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1/F |
| 6.813 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_rgb_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/CLK |
| 10.249 | -0.051 | tSu | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 3.507, 53.846%; route: 2.700, 41.456%; tC2Q: 0.306, 4.698% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 3
Path Summary:| Slack | 3.472 |
| Data Arrival Time | 6.777 |
| Data Required Time | 10.249 |
| From | rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0 |
| To | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 |
| Launch Clk | I_rgb_clk[R] |
| Latch Clk | I_rgb_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_rgb_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 3 | rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/I0 |
| 1.327 | 0.421 | tINS | RR | 5 | rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/F |
| 1.627 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n686_s2/I1 |
| 2.040 | 0.413 | tINS | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n686_s2/F |
| 2.340 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/I0 |
| 2.761 | 0.421 | tINS | RR | 4 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/F |
| 3.061 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/I2 |
| 3.430 | 0.369 | tINS | RR | 3 | rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/F |
| 3.730 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/I0 |
| 4.151 | 0.421 | tINS | RR | 4 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/F |
| 4.451 | 0.300 | tNET | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n365_s3/I1 |
| 5.035 | 0.584 | tINS | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n365_s3/SUM |
| 5.335 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n604_s2/I0 |
| 5.756 | 0.421 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n604_s2/F |
| 6.056 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1/I0 |
| 6.477 | 0.421 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1/F |
| 6.777 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_rgb_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/CLK |
| 10.249 | -0.051 | tSu | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 3.471, 53.590%; route: 2.700, 41.686%; tC2Q: 0.306, 4.724% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 4
Path Summary:| Slack | 3.480 |
| Data Arrival Time | 6.769 |
| Data Required Time | 10.249 |
| From | rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0 |
| To | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 |
| Launch Clk | I_rgb_clk[R] |
| Latch Clk | I_rgb_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_rgb_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 5 | rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n686_s2/I0 |
| 1.327 | 0.421 | tINS | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_b/n686_s2/F |
| 1.627 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s17/I1 |
| 2.040 | 0.413 | tINS | RR | 6 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s17/F |
| 2.340 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s17/I0 |
| 2.761 | 0.421 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s17/F |
| 3.061 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15/I2 |
| 3.430 | 0.369 | tINS | RR | 5 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15/F |
| 3.730 | 0.300 | tNET | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/I1 |
| 4.314 | 0.584 | tINS | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/SUM |
| 4.614 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6/I0 |
| 5.035 | 0.421 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6/F |
| 5.335 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3/I0 |
| 5.756 | 0.421 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3/F |
| 6.056 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/I1 |
| 6.469 | 0.413 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/F |
| 6.769 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_rgb_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLK |
| 10.249 | -0.051 | tSu | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 3.463, 53.532%; route: 2.700, 41.738%; tC2Q: 0.306, 4.730% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 5
Path Summary:| Slack | 3.955 |
| Data Arrival Time | 6.294 |
| Data Required Time | 10.249 |
| From | rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0 |
| To | rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0 |
| Launch Clk | I_rgb_clk[R] |
| Latch Clk | I_rgb_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_rgb_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 3 | rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/I0 |
| 1.327 | 0.421 | tINS | RR | 5 | rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5/F |
| 1.627 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n686_s2/I1 |
| 2.040 | 0.413 | tINS | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n686_s2/F |
| 2.340 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/I0 |
| 2.761 | 0.421 | tINS | RR | 4 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/F |
| 3.061 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/I0 |
| 3.482 | 0.421 | tINS | RR | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/F |
| 3.782 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/I1 |
| 4.195 | 0.413 | tINS | RR | 8 | rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/F |
| 4.495 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n679_s1/I2 |
| 4.864 | 0.369 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n679_s1/F |
| 5.164 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n679_s0/I0 |
| 5.273 | 0.109 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n679_s0/O |
| 5.573 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n689_s0/I0 |
| 5.994 | 0.421 | tINS | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n689_s0/F |
| 6.294 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_rgb_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0/CLK |
| 10.249 | -0.051 | tSu | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 2.988, 49.850%; route: 2.700, 45.045%; tC2Q: 0.306, 5.105% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |