Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\24165\Desktop\acm2108_ddr3_udp\src\ACM2108\DDS_Module.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\ACM2108\acm2108_test.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\ACM2108\key_filter.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\ACM2108\sin_rom_a8d8.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\ACM2108\square_wave_rom_a8d8.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\ACM2108\triangular_rom_a8d8.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\acm2108_ddr3_udp.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\ad_8bit_to_16bit.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\cmd_rx.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\ddr3_ctrl_2port\ddr3_ctrl_2port.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\ddr3_ctrl_2port\fifo_ddr3_adapter.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\ddr3_memory_interface\ddr3_memory_interface.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\ddr_pll\ddr_pll.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\ddr_pll\ddr_pll_mod.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\eth_cmd.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\eth_pll\eth_pll.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\eth_pll\eth_pll_mod.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\eth_send_ctrl.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\eth_udp_gmii\crc32_d8.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\eth_udp_gmii\eth_udp_rx_gmii.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\eth_udp_gmii\eth_udp_tx_gmii.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\eth_udp_gmii\ip_checksum.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\fifo_rx\fifo_rx.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\fifo_tx\fifo_tx.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\gmii_rgmii_gmii\gmii_to_rgmii.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\gmii_rgmii_gmii\rgmii_to_gmii.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\gowin_pll\gowin_pll.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\gowin_pll\gowin_pll_mod.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\pll_init.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\pll_mDRP_intf.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\rd_data_fifo\rd_data_fifo.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\speed_ctrl.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\state_ctrl.v C:\Users\24165\Desktop\acm2108_ddr3_udp\src\wr_data_fifo\wr_data_fifo.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12 (64-bit) |
| Part Number | GW5A-LV25UG324C2/I1 |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Fri Oct 24 10:12:53 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | acm2108_ddr3_udp |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 933.816MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.796s, Elapsed time = 0h 0m 0.792s, Peak memory usage = 933.816MB Optimizing Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.322s, Peak memory usage = 933.816MB Optimizing Phase 2: CPU time = 0h 0m 0.687s, Elapsed time = 0h 0m 0.68s, Peak memory usage = 933.816MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.299s, Peak memory usage = 933.816MB Inferring Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 933.816MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 933.816MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 933.816MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.542s, Peak memory usage = 933.816MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.1s, Peak memory usage = 933.816MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 933.816MB Tech-Mapping Phase 3: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 933.816MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.45s, Peak memory usage = 933.816MB Generate output files: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.41s, Peak memory usage = 933.816MB |
| Total Time and Memory Usage | CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 933.816MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 86 |
| I/O Buf | 83 |
| IBUF | 17 |
| OBUF | 45 |
| TBUF | 2 |
| IOBUF | 16 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 5251 |
| DFFSE | 4 |
| DFFRE | 623 |
| DFFPE | 123 |
| DFFCE | 4501 |
| LUT | 4596 |
| LUT2 | 613 |
| LUT3 | 1634 |
| LUT4 | 2349 |
| ALU | 552 |
| ALU | 552 |
| INV | 60 |
| INV | 60 |
| IOLOGIC | 87 |
| IDDR | 5 |
| ODDR | 6 |
| IDES8_MEM | 16 |
| OSER8 | 24 |
| OSER8_MEM | 20 |
| IODELAY | 16 |
| BSRAM | 21 |
| SDPB | 14 |
| SDPX9B | 4 |
| pROM | 3 |
| CLOCK | 7 |
| CLKDIV | 1 |
| DQS | 2 |
| DDRDLL | 1 |
| PLLA | 3 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 5208(4656 LUT, 552 ALU) / 23040 | 23% |
| Register | 5251 / 23685 | 23% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 5251 / 23685 | 23% |
| BSRAM | 21 / 56 | 38% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | rgmii_rx_clk_i | Base | 8.000 | 125.000 | 0.000 | 4.000 | rgmii_rx_clk_i_ibuf/I | ||
| 3 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | clk | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 4 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | Generated | 8.000 | 125.000 | 0.000 | 4.000 | clk_ibuf/I | clk | Gowin_PLL/u_pll/PLLA_inst/CLKOUT2 |
| 5 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT3.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | clk | Gowin_PLL/u_pll/PLLA_inst/CLKOUT3 |
| 6 | eth_pll/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 8.000 | 125.000 | 0.000 | 4.000 | rgmii_rx_clk_i_ibuf/I | rgmii_rx_clk_i | eth_pll/u_pll/PLLA_inst/CLKOUT0 |
| 7 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | Generated | 2.500 | 400.000 | 0.000 | 1.250 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | ddr_pll/u_pll/PLLA_inst/CLKOUT2 |
| 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | ddr_pll/u_pll/PLLA_inst/CLKOUT2 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 206.101(MHz) | 8 | TOP |
| 2 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | 50.000(MHz) | 155.642(MHz) | 9 | TOP |
| 3 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | 125.000(MHz) | 287.853(MHz) | 5 | TOP |
| 4 | eth_pll/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | 125.000(MHz) | 139.024(MHz) | 12 | TOP |
| 5 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | 400.000(MHz) | 1394.296(MHz) | 1 | TOP |
| 6 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 100.000(MHz) | 216.450(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -0.351 |
| Data Arrival Time | 1.917 |
| Data Required Time | 1.566 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0 |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.290 | 0.290 | tCL | RR | 3689 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.590 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK |
| 0.896 | 0.306 | tC2Q | RR | 11 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q |
| 1.196 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0 |
| 1.617 | 0.421 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
| 1.917 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.250 | 0.000 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 1.738 | 0.488 | tCL | FF | 64 | ddr_pll/u_pll/PLLA_inst/CLKOUT2 |
| 2.018 | 0.280 | tNET | FF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 1.983 | -0.035 | tUnc | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 1.566 | -0.417 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.178 |
| Setup Relationship: | 1.250 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 0.421, 31.726%; route: 0.600, 45.214%; tC2Q: 0.306, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 2
Path Summary:| Slack | -0.351 |
| Data Arrival Time | 1.917 |
| Data Required Time | 1.566 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0 |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.290 | 0.290 | tCL | RR | 3689 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.590 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK |
| 0.896 | 0.306 | tC2Q | RR | 11 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q |
| 1.196 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0 |
| 1.617 | 0.421 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
| 1.917 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.250 | 0.000 | ddr_pll/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 1.738 | 0.488 | tCL | FF | 64 | ddr_pll/u_pll/PLLA_inst/CLKOUT2 |
| 2.018 | 0.280 | tNET | FF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 1.983 | -0.035 | tUnc | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 1.566 | -0.417 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.178 |
| Setup Relationship: | 1.250 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 0.421, 31.726%; route: 0.600, 45.214%; tC2Q: 0.306, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 3
Path Summary:| Slack | 0.484 |
| Data Arrival Time | 23.974 |
| Data Required Time | 24.458 |
| From | acm2108_test/MODE_0_s1 |
| To | acm2108_test/DDS_Module/DA_Data_0_s1 |
| Launch Clk | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | Gowin_PLL/u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 20.244 | 0.244 | tCL | RR | 744 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 20.544 | 0.300 | tNET | RR | 1 | acm2108_test/MODE_0_s1/CLK |
| 20.850 | 0.306 | tC2Q | RR | 38 | acm2108_test/MODE_0_s1/Q |
| 21.150 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/n81_s37/I2 |
| 21.519 | 0.369 | tINS | RR | 2 | acm2108_test/DDS_Module/n81_s37/F |
| 21.819 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/n81_s33/I0 |
| 22.240 | 0.421 | tINS | RR | 1 | acm2108_test/DDS_Module/n81_s33/F |
| 22.540 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/n81_s39/I0 |
| 22.961 | 0.421 | tINS | RR | 1 | acm2108_test/DDS_Module/n81_s39/F |
| 23.261 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/n81_s38/I1 |
| 23.674 | 0.413 | tINS | RR | 1 | acm2108_test/DDS_Module/n81_s38/F |
| 23.974 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 24.000 | 0.000 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 24.244 | 0.244 | tCL | RR | 65 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT2 |
| 24.544 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_0_s1/CLK |
| 24.509 | -0.035 | tUnc | acm2108_test/DDS_Module/DA_Data_0_s1 | ||
| 24.458 | -0.051 | tSu | 1 | acm2108_test/DDS_Module/DA_Data_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 4.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 1.624, 47.347%; route: 1.500, 43.732%; tC2Q: 0.306, 8.921% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 4
Path Summary:| Slack | 0.484 |
| Data Arrival Time | 23.974 |
| Data Required Time | 24.458 |
| From | acm2108_test/MODE_0_s1 |
| To | acm2108_test/DDS_Module/DA_Data_1_s1 |
| Launch Clk | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | Gowin_PLL/u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 20.244 | 0.244 | tCL | RR | 744 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 20.544 | 0.300 | tNET | RR | 1 | acm2108_test/MODE_0_s1/CLK |
| 20.850 | 0.306 | tC2Q | RR | 38 | acm2108_test/MODE_0_s1/Q |
| 21.150 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/n80_s37/I2 |
| 21.519 | 0.369 | tINS | RR | 2 | acm2108_test/DDS_Module/n80_s37/F |
| 21.819 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/n80_s33/I0 |
| 22.240 | 0.421 | tINS | RR | 1 | acm2108_test/DDS_Module/n80_s33/F |
| 22.540 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/n80_s39/I0 |
| 22.961 | 0.421 | tINS | RR | 1 | acm2108_test/DDS_Module/n80_s39/F |
| 23.261 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/n80_s38/I1 |
| 23.674 | 0.413 | tINS | RR | 1 | acm2108_test/DDS_Module/n80_s38/F |
| 23.974 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 24.000 | 0.000 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 24.244 | 0.244 | tCL | RR | 65 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT2 |
| 24.544 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_1_s1/CLK |
| 24.509 | -0.035 | tUnc | acm2108_test/DDS_Module/DA_Data_1_s1 | ||
| 24.458 | -0.051 | tSu | 1 | acm2108_test/DDS_Module/DA_Data_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 4.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 1.624, 47.347%; route: 1.500, 43.732%; tC2Q: 0.306, 8.921% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 5
Path Summary:| Slack | 0.484 |
| Data Arrival Time | 23.974 |
| Data Required Time | 24.458 |
| From | acm2108_test/MODE_0_s1 |
| To | acm2108_test/DDS_Module/DA_Data_2_s1 |
| Launch Clk | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | Gowin_PLL/u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 20.244 | 0.244 | tCL | RR | 744 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 20.544 | 0.300 | tNET | RR | 1 | acm2108_test/MODE_0_s1/CLK |
| 20.850 | 0.306 | tC2Q | RR | 38 | acm2108_test/MODE_0_s1/Q |
| 21.150 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/n79_s37/I2 |
| 21.519 | 0.369 | tINS | RR | 2 | acm2108_test/DDS_Module/n79_s37/F |
| 21.819 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/n79_s33/I0 |
| 22.240 | 0.421 | tINS | RR | 1 | acm2108_test/DDS_Module/n79_s33/F |
| 22.540 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/n79_s39/I0 |
| 22.961 | 0.421 | tINS | RR | 1 | acm2108_test/DDS_Module/n79_s39/F |
| 23.261 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/n79_s38/I1 |
| 23.674 | 0.413 | tINS | RR | 1 | acm2108_test/DDS_Module/n79_s38/F |
| 23.974 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 24.000 | 0.000 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 24.244 | 0.244 | tCL | RR | 65 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT2 |
| 24.544 | 0.300 | tNET | RR | 1 | acm2108_test/DDS_Module/DA_Data_2_s1/CLK |
| 24.509 | -0.035 | tUnc | acm2108_test/DDS_Module/DA_Data_2_s1 | ||
| 24.458 | -0.051 | tSu | 1 | acm2108_test/DDS_Module/DA_Data_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 4.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 1.624, 47.347%; route: 1.500, 43.732%; tC2Q: 0.306, 8.921% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |