ila_0.v,verilog,xil_defaultlib,../../../../project_1.srcs/sources_1/new/ip/ila_0/sim/ila_0.v,incdir="../../../../project_1.srcs/sources_1/new/ip/ila_0/hdl/verilog"
glbl.v,Verilog,xil_defaultlib,glbl.v
