Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\24165\Desktop\acg720_138_piano\src\bintobcd\adjust.v C:\Users\24165\Desktop\acg720_138_piano\src\bintobcd\bintobcd.v C:\Users\24165\Desktop\acg720_138_piano\src\bintobcd\shift_adjust.v C:\Users\24165\Desktop\acg720_138_piano\src\gt9147_driver\gt9147_driver.v C:\Users\24165\Desktop\acg720_138_piano\src\gt9147_driver\i2c_bit_shift.v C:\Users\24165\Desktop\acg720_138_piano\src\gt9147_driver\i2c_control.v C:\Users\24165\Desktop\acg720_138_piano\src\gt9147_driver\key_filter.v C:\Users\24165\Desktop\acg720_138_piano\src\HEX8\HC595_Driver.v C:\Users\24165\Desktop\acg720_138_piano\src\HEX8\HEX_top.v C:\Users\24165\Desktop\acg720_138_piano\src\HEX8\HEX8.v C:\Users\24165\Desktop\acg720_138_piano\src\key_process\edge_check.v C:\Users\24165\Desktop\acg720_138_piano\src\key_process\key.v C:\Users\24165\Desktop\acg720_138_piano\src\key_process\key_filters.v C:\Users\24165\Desktop\acg720_138_piano\src\buzzer.v C:\Users\24165\Desktop\acg720_138_piano\src\ibeep.v C:\Users\24165\Desktop\acg720_138_piano\src\piano.v C:\Users\24165\Desktop\acg720_138_piano\src\piano_ctrl.v C:\Users\24165\Desktop\acg720_138_piano\src\gowin_pll\gowin_pll.v C:\Users\24165\Desktop\acg720_138_piano\src\gowin_pll\gowin_pll_mod.v C:\Users\24165\Desktop\acg720_138_piano\src\pll_init.v C:\Users\24165\Desktop\acg720_138_piano\src\vga\disp_driver.v C:\Users\24165\Desktop\acg720_138_piano\src\vga\disp_parameter_cfg.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02_SP2 (64-bit) |
| Part Number | GW5AT-LV138PG484AC1/I0 |
| Device | GW5AT-138 |
| Device Version | B |
| Created Time | Mon Sep 14 16:17:43 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | piano |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.296s, Peak memory usage = 325.734MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 325.734MB Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 325.734MB Optimizing Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.154s, Peak memory usage = 325.734MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.084s, Peak memory usage = 325.734MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 325.734MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 325.734MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 325.734MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.104s, Peak memory usage = 325.734MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 325.734MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 325.734MB Tech-Mapping Phase 3: CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 358.059MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.165s, Peak memory usage = 358.059MB Generate output files: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.09s, Peak memory usage = 358.059MB |
| Total Time and Memory Usage | CPU time = 0h 0m 13s, Elapsed time = 0h 0m 14s, Peak memory usage = 358.059MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 32 |
| I/O Buf | 32 |
| IBUF | 3 |
| OBUF | 27 |
| IOBUF | 2 |
| Register | 502 |
| DFFRE | 70 |
| DFFPE | 11 |
| DFFCE | 421 |
| LUT | 1310 |
| LUT2 | 89 |
| LUT3 | 409 |
| LUT4 | 812 |
| ALU | 59 |
| ALU | 59 |
| INV | 9 |
| INV | 9 |
| CLOCK | 1 |
| PLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1378(1319 LUT, 59 ALU) / 138240 | <1% |
| Register | 502 / 139095 | <1% |
| --Register as Latch | 0 / 139095 | 0% |
| --Register as FF | 502 / 139095 | <1% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | u_gt9147_driver/u_HEX_top/HEX8/clk_1K | Base | 10.000 | 100.000 | 0.000 | 5.000 | u_gt9147_driver/u_HEX_top/HEX8/clk_1K_s1/Q | ||
| 3 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT0 |
| 4 | Gowin_PLL/u_pll/PLL_inst/CLKOUT1.default_gen_clk | Generated | 30.000 | 33.333 | 0.000 | 15.000 | clk_ibuf/I | clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT1 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 230.880(MHz) | 5 | TOP |
| 2 | u_gt9147_driver/u_HEX_top/HEX8/clk_1K | 100.000(MHz) | 401.123(MHz) | 3 | TOP |
| 3 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk | 50.000(MHz) | 119.298(MHz) | 10 | TOP |
| 4 | Gowin_PLL/u_pll/PLL_inst/CLKOUT1.default_gen_clk | 33.333(MHz) | 66.970(MHz) | 17 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.815 |
| Data Arrival Time | 36.835 |
| Data Required Time | 40.650 |
| From | u_gt9147_driver/position_28_s0 |
| To | u_buzzer/key_1_s0 |
| Launch Clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT1.default_gen_clk[R] |
| Latch Clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 30.000 | active clock edge time | |||
| 30.000 | 0.000 | Gowin_PLL/u_pll/PLL_inst/CLKOUT1.default_gen_clk | |||
| 30.371 | 0.371 | tCL | RR | 361 | Gowin_PLL/u_pll/PLL_inst/CLKOUT1 |
| 30.743 | 0.371 | tNET | RR | 1 | u_gt9147_driver/position_28_s0/CLK |
| 31.087 | 0.344 | tC2Q | RR | 1 | u_gt9147_driver/position_28_s0/Q |
| 31.458 | 0.371 | tNET | RR | 1 | u_buzzer/n230_s6/I0 |
| 31.979 | 0.521 | tINS | RR | 2 | u_buzzer/n230_s6/F |
| 32.350 | 0.371 | tNET | RR | 1 | u_buzzer/n234_s19/I3 |
| 32.610 | 0.260 | tINS | RR | 9 | u_buzzer/n234_s19/F |
| 32.981 | 0.371 | tNET | RR | 1 | u_buzzer/n234_s28/I2 |
| 33.438 | 0.457 | tINS | RR | 1 | u_buzzer/n234_s28/F |
| 33.809 | 0.371 | tNET | RR | 1 | u_buzzer/n234_s13/I3 |
| 34.069 | 0.260 | tINS | RR | 2 | u_buzzer/n234_s13/F |
| 34.440 | 0.371 | tNET | RR | 1 | u_buzzer/n233_s23/I3 |
| 34.700 | 0.260 | tINS | RR | 2 | u_buzzer/n233_s23/F |
| 35.071 | 0.371 | tNET | RR | 1 | u_buzzer/n233_s3/I1 |
| 35.582 | 0.511 | tINS | RR | 1 | u_buzzer/n233_s3/F |
| 35.953 | 0.371 | tNET | RR | 1 | u_buzzer/n233_s1/I1 |
| 36.464 | 0.511 | tINS | RR | 1 | u_buzzer/n233_s1/F |
| 36.835 | 0.371 | tNET | RR | 1 | u_buzzer/key_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | |||
| 40.000 | 0.000 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 40.371 | 0.371 | tCL | RR | 95 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0 |
| 40.743 | 0.371 | tNET | RR | 1 | u_buzzer/key_1_s0/CLK |
| 40.708 | -0.035 | tUnc | u_buzzer/key_1_s0 | ||
| 40.650 | -0.057 | tSu | 1 | u_buzzer/key_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
| Arrival Data Path Delay: | cell: 2.779, 45.606%; route: 2.970, 48.744%; tC2Q: 0.344, 5.650% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path 2
Path Summary:| Slack | 3.869 |
| Data Arrival Time | 36.782 |
| Data Required Time | 40.650 |
| From | u_gt9147_driver/position_28_s0 |
| To | u_buzzer/key_2_s0 |
| Launch Clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT1.default_gen_clk[R] |
| Latch Clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 30.000 | active clock edge time | |||
| 30.000 | 0.000 | Gowin_PLL/u_pll/PLL_inst/CLKOUT1.default_gen_clk | |||
| 30.371 | 0.371 | tCL | RR | 361 | Gowin_PLL/u_pll/PLL_inst/CLKOUT1 |
| 30.743 | 0.371 | tNET | RR | 1 | u_gt9147_driver/position_28_s0/CLK |
| 31.087 | 0.344 | tC2Q | RR | 1 | u_gt9147_driver/position_28_s0/Q |
| 31.458 | 0.371 | tNET | RR | 1 | u_buzzer/n230_s6/I0 |
| 31.979 | 0.521 | tINS | RR | 2 | u_buzzer/n230_s6/F |
| 32.350 | 0.371 | tNET | RR | 1 | u_buzzer/n230_s3/I3 |
| 32.610 | 0.260 | tINS | RR | 5 | u_buzzer/n230_s3/F |
| 32.981 | 0.371 | tNET | RR | 1 | u_buzzer/n234_s24/I2 |
| 33.438 | 0.457 | tINS | RR | 2 | u_buzzer/n234_s24/F |
| 33.809 | 0.371 | tNET | RR | 1 | u_buzzer/n234_s11/I3 |
| 34.069 | 0.260 | tINS | RR | 2 | u_buzzer/n234_s11/F |
| 34.440 | 0.371 | tNET | RR | 1 | u_buzzer/n233_s10/I3 |
| 34.700 | 0.260 | tINS | RR | 2 | u_buzzer/n233_s10/F |
| 35.071 | 0.371 | tNET | RR | 1 | u_buzzer/n232_s2/I2 |
| 35.528 | 0.457 | tINS | RR | 2 | u_buzzer/n232_s2/F |
| 35.900 | 0.371 | tNET | RR | 1 | u_buzzer/n232_s1/I1 |
| 36.410 | 0.511 | tINS | RR | 1 | u_buzzer/n232_s1/F |
| 36.781 | 0.371 | tNET | RR | 1 | u_buzzer/key_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | |||
| 40.000 | 0.000 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 40.371 | 0.371 | tCL | RR | 95 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0 |
| 40.743 | 0.371 | tNET | RR | 1 | u_buzzer/key_2_s0/CLK |
| 40.708 | -0.035 | tUnc | u_buzzer/key_2_s0 | ||
| 40.650 | -0.057 | tSu | 1 | u_buzzer/key_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
| Arrival Data Path Delay: | cell: 2.725, 45.119%; route: 2.970, 49.181%; tC2Q: 0.344, 5.700% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path 3
Path Summary:| Slack | 3.923 |
| Data Arrival Time | 36.728 |
| Data Required Time | 40.650 |
| From | u_gt9147_driver/position_28_s0 |
| To | u_buzzer/key_3_s0 |
| Launch Clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT1.default_gen_clk[R] |
| Latch Clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 30.000 | active clock edge time | |||
| 30.000 | 0.000 | Gowin_PLL/u_pll/PLL_inst/CLKOUT1.default_gen_clk | |||
| 30.371 | 0.371 | tCL | RR | 361 | Gowin_PLL/u_pll/PLL_inst/CLKOUT1 |
| 30.743 | 0.371 | tNET | RR | 1 | u_gt9147_driver/position_28_s0/CLK |
| 31.087 | 0.344 | tC2Q | RR | 1 | u_gt9147_driver/position_28_s0/Q |
| 31.458 | 0.371 | tNET | RR | 1 | u_buzzer/n230_s6/I0 |
| 31.979 | 0.521 | tINS | RR | 2 | u_buzzer/n230_s6/F |
| 32.350 | 0.371 | tNET | RR | 1 | u_buzzer/n230_s3/I3 |
| 32.610 | 0.260 | tINS | RR | 5 | u_buzzer/n230_s3/F |
| 32.981 | 0.371 | tNET | RR | 1 | u_buzzer/n234_s24/I2 |
| 33.438 | 0.457 | tINS | RR | 2 | u_buzzer/n234_s24/F |
| 33.809 | 0.371 | tNET | RR | 1 | u_buzzer/n234_s11/I3 |
| 34.069 | 0.260 | tINS | RR | 2 | u_buzzer/n234_s11/F |
| 34.440 | 0.371 | tNET | RR | 1 | u_buzzer/n233_s10/I3 |
| 34.700 | 0.260 | tINS | RR | 2 | u_buzzer/n233_s10/F |
| 35.071 | 0.371 | tNET | RR | 1 | u_buzzer/n232_s2/I2 |
| 35.528 | 0.457 | tINS | RR | 2 | u_buzzer/n232_s2/F |
| 35.900 | 0.371 | tNET | RR | 1 | u_buzzer/n231_s1/I2 |
| 36.356 | 0.457 | tINS | RR | 1 | u_buzzer/n231_s1/F |
| 36.728 | 0.371 | tNET | RR | 1 | u_buzzer/key_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | |||
| 40.000 | 0.000 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 40.371 | 0.371 | tCL | RR | 95 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0 |
| 40.743 | 0.371 | tNET | RR | 1 | u_buzzer/key_3_s0/CLK |
| 40.708 | -0.035 | tUnc | u_buzzer/key_3_s0 | ||
| 40.650 | -0.057 | tSu | 1 | u_buzzer/key_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
| Arrival Data Path Delay: | cell: 2.671, 44.624%; route: 2.970, 49.624%; tC2Q: 0.344, 5.752% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path 4
Path Summary:| Slack | 3.988 |
| Data Arrival Time | 36.662 |
| Data Required Time | 40.650 |
| From | u_gt9147_driver/position_18_s0 |
| To | u_buzzer/key_0_s0 |
| Launch Clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT1.default_gen_clk[R] |
| Latch Clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 30.000 | active clock edge time | |||
| 30.000 | 0.000 | Gowin_PLL/u_pll/PLL_inst/CLKOUT1.default_gen_clk | |||
| 30.371 | 0.371 | tCL | RR | 361 | Gowin_PLL/u_pll/PLL_inst/CLKOUT1 |
| 30.743 | 0.371 | tNET | RR | 1 | u_gt9147_driver/position_18_s0/CLK |
| 31.087 | 0.344 | tC2Q | RR | 15 | u_gt9147_driver/position_18_s0/Q |
| 31.458 | 0.371 | tNET | RR | 1 | u_buzzer/n233_s13/I0 |
| 31.979 | 0.521 | tINS | RR | 5 | u_buzzer/n233_s13/F |
| 32.350 | 0.371 | tNET | RR | 1 | u_buzzer/n234_s32/I1 |
| 32.861 | 0.511 | tINS | RR | 1 | u_buzzer/n234_s32/F |
| 33.232 | 0.371 | tNET | RR | 1 | u_buzzer/n234_s25/I1 |
| 33.743 | 0.511 | tINS | RR | 1 | u_buzzer/n234_s25/F |
| 34.114 | 0.371 | tNET | RR | 1 | u_buzzer/n234_s34/I0 |
| 34.635 | 0.521 | tINS | RR | 2 | u_buzzer/n234_s34/F |
| 35.006 | 0.371 | tNET | RR | 1 | u_buzzer/n234_s4/I2 |
| 35.463 | 0.457 | tINS | RR | 1 | u_buzzer/n234_s4/F |
| 35.834 | 0.371 | tNET | RR | 1 | u_buzzer/n234_s1/I2 |
| 36.291 | 0.457 | tINS | RR | 1 | u_buzzer/n234_s1/F |
| 36.662 | 0.371 | tNET | RR | 1 | u_buzzer/key_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | |||
| 40.000 | 0.000 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 40.371 | 0.371 | tCL | RR | 95 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0 |
| 40.743 | 0.371 | tNET | RR | 1 | u_buzzer/key_0_s0/CLK |
| 40.708 | -0.035 | tUnc | u_buzzer/key_0_s0 | ||
| 40.650 | -0.057 | tSu | 1 | u_buzzer/key_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
| Arrival Data Path Delay: | cell: 2.977, 50.285%; route: 2.599, 43.900%; tC2Q: 0.344, 5.815% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path 5
Path Summary:| Slack | 4.186 |
| Data Arrival Time | 26.464 |
| Data Required Time | 30.650 |
| From | u_gt9147_driver/u_HEX_top/HEX8/sel_r_0_s0 |
| To | u_gt9147_driver/u_HEX_top/HC595_Driver/r_data_8_s0 |
| Launch Clk | u_gt9147_driver/u_HEX_top/HEX8/clk_1K[R] |
| Latch Clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT1.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | |||
| 20.000 | 0.000 | u_gt9147_driver/u_HEX_top/HEX8/clk_1K | |||
| 20.000 | 0.000 | tCL | RR | 9 | u_gt9147_driver/u_HEX_top/HEX8/clk_1K_s1/Q |
| 20.371 | 0.371 | tNET | RR | 1 | u_gt9147_driver/u_HEX_top/HEX8/sel_r_0_s0/CLK |
| 20.715 | 0.344 | tC2Q | RR | 6 | u_gt9147_driver/u_HEX_top/HEX8/sel_r_0_s0/Q |
| 21.087 | 0.371 | tNET | RR | 1 | u_gt9147_driver/u_HEX_top/HEX8/n97_s1/I0 |
| 21.608 | 0.521 | tINS | RR | 4 | u_gt9147_driver/u_HEX_top/HEX8/n97_s1/F |
| 21.979 | 0.371 | tNET | RR | 1 | u_gt9147_driver/u_HEX_top/HEX8/n97_s0/I2 |
| 22.436 | 0.457 | tINS | RR | 6 | u_gt9147_driver/u_HEX_top/HEX8/n97_s0/F |
| 22.807 | 0.371 | tNET | RR | 1 | u_gt9147_driver/u_HEX_top/HEX8/data_tmp_1_s22/I3 |
| 23.067 | 0.260 | tINS | RR | 1 | u_gt9147_driver/u_HEX_top/HEX8/data_tmp_1_s22/F |
| 23.438 | 0.371 | tNET | RR | 1 | u_gt9147_driver/u_HEX_top/HEX8/data_tmp_1_s16/I3 |
| 23.698 | 0.260 | tINS | RR | 1 | u_gt9147_driver/u_HEX_top/HEX8/data_tmp_1_s16/F |
| 24.069 | 0.371 | tNET | RR | 1 | u_gt9147_driver/u_HEX_top/HEX8/data_tmp_1_s12/I3 |
| 24.329 | 0.260 | tINS | RR | 1 | u_gt9147_driver/u_HEX_top/HEX8/data_tmp_1_s12/F |
| 24.700 | 0.371 | tNET | RR | 1 | u_gt9147_driver/u_HEX_top/HEX8/data_tmp_1_s10/I1 |
| 25.211 | 0.511 | tINS | RR | 7 | u_gt9147_driver/u_HEX_top/HEX8/data_tmp_1_s10/F |
| 25.582 | 0.371 | tNET | RR | 1 | u_gt9147_driver/u_HEX_top/HEX8/seg_0_s16/I1 |
| 26.093 | 0.511 | tINS | RR | 1 | u_gt9147_driver/u_HEX_top/HEX8/seg_0_s16/F |
| 26.464 | 0.371 | tNET | RR | 1 | u_gt9147_driver/u_HEX_top/HC595_Driver/r_data_8_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 30.000 | active clock edge time | |||
| 30.000 | 0.000 | Gowin_PLL/u_pll/PLL_inst/CLKOUT1.default_gen_clk | |||
| 30.371 | 0.371 | tCL | RR | 361 | Gowin_PLL/u_pll/PLL_inst/CLKOUT1 |
| 30.743 | 0.371 | tNET | RR | 1 | u_gt9147_driver/u_HEX_top/HC595_Driver/r_data_8_s0/CLK |
| 30.708 | -0.035 | tUnc | u_gt9147_driver/u_HEX_top/HC595_Driver/r_data_8_s0 | ||
| 30.650 | -0.057 | tSu | 1 | u_gt9147_driver/u_HEX_top/HC595_Driver/r_data_8_s0 |
| Clock Skew: | 0.371 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
| Arrival Data Path Delay: | cell: 2.779, 45.606%; route: 2.970, 48.744%; tC2Q: 0.344, 5.650% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |