Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.02_SP2_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\ddr3_1_4code_hs.v D:\Gowin\Gowin_V1.9.12.02_SP2_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\DDR3_TOP.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02_SP2 (64-bit) |
| Part Number | GW5A-LV25UG324C2/I1 |
| Device | GW5A-25 |
| Device Version | B |
| Created Time | Thu Oct 29 11:54:02 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | DDR3_Memory_Interface_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.937s, Elapsed time = 0h 0m 1s, Peak memory usage = 111.527MB Running netlist conversion: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.105s, Peak memory usage = 111.527MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.518s, Peak memory usage = 111.527MB Optimizing Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.193s, Peak memory usage = 111.527MB Optimizing Phase 2: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.72s, Peak memory usage = 111.527MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.383s, Peak memory usage = 111.527MB Inferring Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 111.527MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 111.527MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 111.527MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.609s, Elapsed time = 0h 0m 0.599s, Peak memory usage = 111.527MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.246s, Peak memory usage = 111.527MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.145s, Peak memory usage = 111.527MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 124.980MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.53s, Peak memory usage = 124.980MB Generate output files: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.552s, Peak memory usage = 127.133MB |
| Total Time and Memory Usage | CPU time = 0h 0m 7s, Elapsed time = 0h 0m 8s, Peak memory usage = 127.133MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 371 |
| I/O Buf | 365 |
| IBUF | 182 |
| OBUF | 162 |
| TBUF | 2 |
| IOBUF | 16 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 3567 |
| DFFSE | 1 |
| DFFRE | 249 |
| DFFPE | 66 |
| DFFCE | 3251 |
| LUT | 1986 |
| LUT2 | 232 |
| LUT3 | 949 |
| LUT4 | 805 |
| ALU | 125 |
| ALU | 125 |
| INV | 22 |
| INV | 22 |
| IOLOGIC | 76 |
| IDES8_MEM | 16 |
| OSER8 | 24 |
| OSER8_MEM | 20 |
| IODELAY | 16 |
| BSRAM | 8 |
| SDPB | 4 |
| SDPX9B | 4 |
| CLOCK | 4 |
| CLKDIV | 1 |
| DQS | 2 |
| DDRDLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2133(2008 LUT, 125 ALU) / 23040 | 10% |
| Register | 3567 / 23685 | 16% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 3567 / 23685 | 16% |
| BSRAM | 8 / 56 | 15% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | memory_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
| 2 | clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I | ||
| 3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | memory_clk | 100.000(MHz) | 1549.218(MHz) | 1 | TOP |
| 2 | clk | 100.000(MHz) | 314.495(MHz) | 5 | TOP |
| 3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 240.500(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.116 |
| Data Arrival Time | 1.725 |
| Data Required Time | 4.842 |
| From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | memory_clk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.261 | 0.261 | tCL | RR | 3606 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.531 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK |
| 0.806 | 0.275 | tC2Q | RR | 12 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q |
| 1.076 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0 |
| 1.455 | 0.379 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
| 1.725 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 5.000 | active clock edge time | |||
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 64 | memory_clk_ibuf/O |
| 5.252 | 0.252 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 5.217 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 4.842 | -0.375 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.279 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
| Arrival Data Path Delay: | cell: 0.379, 31.726%; route: 0.540, 45.214%; tC2Q: 0.275, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
Path 2
Path Summary:| Slack | 3.116 |
| Data Arrival Time | 1.725 |
| Data Required Time | 4.842 |
| From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | memory_clk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.261 | 0.261 | tCL | RR | 3606 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.531 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK |
| 0.806 | 0.275 | tC2Q | RR | 12 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q |
| 1.076 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0 |
| 1.455 | 0.379 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
| 1.725 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 5.000 | active clock edge time | |||
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 64 | memory_clk_ibuf/O |
| 5.252 | 0.252 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 5.217 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 4.842 | -0.375 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.279 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
| Arrival Data Path Delay: | cell: 0.379, 31.726%; route: 0.540, 45.214%; tC2Q: 0.275, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
Path 3
Path Summary:| Slack | 6.820 |
| Data Arrival Time | 3.404 |
| Data Required Time | 10.224 |
| From | gw3_top/u_ddr_phy_top/ddr_sync/count_2_s0 |
| To | gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 0.270 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/count_2_s0/CLK |
| 0.545 | 0.275 | tC2Q | RR | 7 | gw3_top/u_ddr_phy_top/ddr_sync/count_2_s0/Q |
| 0.815 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_1_s13/I0 |
| 1.194 | 0.379 | tINS | RR | 4 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_1_s13/F |
| 1.464 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_0_s14/I0 |
| 1.843 | 0.379 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_0_s14/F |
| 2.113 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_0_s13/I0 |
| 2.492 | 0.379 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_0_s13/F |
| 2.762 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_0_s11/I1 |
| 3.134 | 0.372 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_0_s11/F |
| 3.404 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 10.270 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4/CLK |
| 10.224 | -0.046 | tSu | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
| Arrival Data Path Delay: | cell: 1.508, 48.133%; route: 1.350, 43.079%; tC2Q: 0.275, 8.788% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
Path 4
Path Summary:| Slack | 6.914 |
| Data Arrival Time | 3.310 |
| Data Required Time | 10.224 |
| From | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0 |
| To | gw3_top/u_ddr_phy_top/ddr_sync/count_1_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 0.270 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLK |
| 0.545 | 0.275 | tC2Q | RR | 6 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/Q |
| 0.815 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_1_s14/I0 |
| 1.194 | 0.379 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_1_s14/F |
| 1.464 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s14/I2 |
| 1.796 | 0.332 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s14/F |
| 2.066 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s4/I2 |
| 2.398 | 0.332 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s4/F |
| 2.668 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n297_s2/I1 |
| 3.040 | 0.372 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n297_s2/F |
| 3.310 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/count_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 10.270 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/count_1_s0/CLK |
| 10.224 | -0.046 | tSu | 1 | gw3_top/u_ddr_phy_top/ddr_sync/count_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
| Arrival Data Path Delay: | cell: 1.415, 46.536%; route: 1.350, 44.405%; tC2Q: 0.275, 9.059% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
Path 5
Path Summary:| Slack | 6.954 |
| Data Arrival Time | 3.271 |
| Data Required Time | 10.224 |
| From | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0 |
| To | gw3_top/u_ddr_phy_top/ddr_sync/count_2_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 0.270 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLK |
| 0.545 | 0.275 | tC2Q | RR | 6 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/Q |
| 0.815 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_1_s14/I0 |
| 1.194 | 0.379 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_1_s14/F |
| 1.464 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s14/I2 |
| 1.796 | 0.332 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s14/F |
| 2.066 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s4/I2 |
| 2.398 | 0.332 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s4/F |
| 2.668 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n296_s2/I2 |
| 3.001 | 0.332 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n296_s2/F |
| 3.271 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/count_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 10.270 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/count_2_s0/CLK |
| 10.224 | -0.046 | tSu | 1 | gw3_top/u_ddr_phy_top/ddr_sync/count_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
| Arrival Data Path Delay: | cell: 1.375, 45.831%; route: 1.350, 44.991%; tC2Q: 0.275, 9.178% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |