Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\DATA\AC601_GW5A25\mipi_dsi\tmp\ov5647_b_migration_20261102\runtime\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\ddr3_1_4code_hs.v D:\DATA\AC601_GW5A25\mipi_dsi\tmp\ov5647_b_migration_20261102\runtime\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\DDR3_TOP.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02_SP2 (64-bit) |
| Part Number | GW5A-LV25UG324C2/I1 |
| Device | GW5A-25 |
| Device Version | B |
| Created Time | Mon Nov 2 17:05:16 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | DDR3_Memory_Interface_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.875s, Elapsed time = 0h 0m 1s, Peak memory usage = 124.434MB Running netlist conversion: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 124.434MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.435s, Peak memory usage = 124.434MB Optimizing Phase 1: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.206s, Peak memory usage = 124.434MB Optimizing Phase 2: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.713s, Peak memory usage = 124.434MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.399s, Peak memory usage = 124.434MB Inferring Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 124.434MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 124.434MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 124.434MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.44s, Peak memory usage = 124.434MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.16s, Peak memory usage = 124.434MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.103s, Peak memory usage = 124.434MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 135.125MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.415s, Peak memory usage = 135.125MB Generate output files: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.393s, Peak memory usage = 135.125MB |
| Total Time and Memory Usage | CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 135.125MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 373 |
| I/O Buf | 367 |
| IBUF | 183 |
| OBUF | 163 |
| TBUF | 2 |
| IOBUF | 16 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 3602 |
| DFFSE | 1 |
| DFFRE | 257 |
| DFFPE | 67 |
| DFFCE | 3277 |
| LUT | 1973 |
| LUT2 | 279 |
| LUT3 | 924 |
| LUT4 | 770 |
| ALU | 126 |
| ALU | 126 |
| INV | 22 |
| INV | 22 |
| IOLOGIC | 77 |
| IDES8_MEM | 16 |
| OSER8 | 25 |
| OSER8_MEM | 20 |
| IODELAY | 16 |
| BSRAM | 8 |
| SDPB | 4 |
| SDPX9B | 4 |
| CLOCK | 4 |
| CLKDIV | 1 |
| DQS | 2 |
| DDRDLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2121(1995 LUT, 126 ALU) / 23040 | 10% |
| Register | 3602 / 23685 | 16% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 3602 / 23685 | 16% |
| BSRAM | 8 / 56 | 15% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | memory_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
| 2 | clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I | ||
| 3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | memory_clk | 100.000(MHz) | 1549.218(MHz) | 1 | TOP |
| 2 | clk | 100.000(MHz) | 293.945(MHz) | 6 | TOP |
| 3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 240.500(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.116 |
| Data Arrival Time | 1.725 |
| Data Required Time | 4.842 |
| From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | memory_clk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.261 | 0.261 | tCL | RR | 3642 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.531 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK |
| 0.806 | 0.275 | tC2Q | RR | 10 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q |
| 1.076 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0 |
| 1.455 | 0.379 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
| 1.725 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 5.000 | active clock edge time | |||
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 65 | memory_clk_ibuf/O |
| 5.252 | 0.252 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 5.217 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 4.842 | -0.375 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.279 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
| Arrival Data Path Delay: | cell: 0.379, 31.726%; route: 0.540, 45.214%; tC2Q: 0.275, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
Path 2
Path Summary:| Slack | 3.116 |
| Data Arrival Time | 1.725 |
| Data Required Time | 4.842 |
| From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | memory_clk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.261 | 0.261 | tCL | RR | 3642 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.531 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK |
| 0.806 | 0.275 | tC2Q | RR | 10 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q |
| 1.076 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0 |
| 1.455 | 0.379 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
| 1.725 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 5.000 | active clock edge time | |||
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 65 | memory_clk_ibuf/O |
| 5.252 | 0.252 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 5.217 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 4.842 | -0.375 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | -0.279 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
| Arrival Data Path Delay: | cell: 0.379, 31.726%; route: 0.540, 45.214%; tC2Q: 0.275, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
Path 3
Path Summary:| Slack | 6.598 |
| Data Arrival Time | 3.626 |
| Data Required Time | 10.224 |
| From | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0 |
| To | gw3_top/u_ddr_phy_top/ddr_sync/count_0_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 0.270 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLK |
| 0.545 | 0.275 | tC2Q | RR | 5 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/Q |
| 0.815 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s16/I0 |
| 1.194 | 0.379 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s16/F |
| 1.464 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s14/I2 |
| 1.796 | 0.332 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s14/F |
| 2.066 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s5/I3 |
| 2.255 | 0.189 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s5/F |
| 2.525 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s4/I3 |
| 2.714 | 0.189 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s4/F |
| 2.984 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s3/I1 |
| 3.356 | 0.372 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s3/F |
| 3.626 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/count_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 10.270 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/count_0_s0/CLK |
| 10.224 | -0.046 | tSu | 1 | gw3_top/u_ddr_phy_top/ddr_sync/count_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
| Arrival Data Path Delay: | cell: 1.461, 43.524%; route: 1.620, 48.270%; tC2Q: 0.275, 8.206% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
Path 4
Path Summary:| Slack | 6.634 |
| Data Arrival Time | 33.816 |
| Data Required Time | 40.450 |
| From | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0 |
| Launch Clk | clk[R] |
| Latch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 30.000 | active clock edge time | |||
| 30.000 | 0.000 | clk | |||
| 30.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 30.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 30.270 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK |
| 30.545 | 0.275 | tC2Q | RR | 2 | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q |
| 30.815 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s22/I3 |
| 31.004 | 0.189 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s22/F |
| 31.274 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s24/I1 |
| 31.646 | 0.372 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s24/F |
| 31.916 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s22/I0 |
| 32.295 | 0.379 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s22/F |
| 32.565 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I2 |
| 32.897 | 0.332 | tINS | RR | 15 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F |
| 33.167 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.READ_CALIBRATION_s19/I0 |
| 33.546 | 0.379 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.READ_CALIBRATION_s19/F |
| 33.816 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | |||
| 40.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 40.261 | 0.261 | tCL | RR | 3642 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 40.531 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0/CLK |
| 40.496 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0 | ||
| 40.450 | -0.046 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0 |
| Clock Skew: | 0.261 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
| Arrival Data Path Delay: | cell: 1.651, 46.549%; route: 1.620, 45.685%; tC2Q: 0.275, 7.766% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
Path 5
Path Summary:| Slack | 6.634 |
| Data Arrival Time | 33.816 |
| Data Required Time | 40.450 |
| From | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0 |
| Launch Clk | clk[R] |
| Latch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 30.000 | active clock edge time | |||
| 30.000 | 0.000 | clk | |||
| 30.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 30.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 30.270 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK |
| 30.545 | 0.275 | tC2Q | RR | 2 | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q |
| 30.815 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s22/I3 |
| 31.004 | 0.189 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s22/F |
| 31.274 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s24/I1 |
| 31.646 | 0.372 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s24/F |
| 31.916 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s22/I0 |
| 32.295 | 0.379 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s22/F |
| 32.565 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I2 |
| 32.897 | 0.332 | tINS | RR | 15 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F |
| 33.167 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_MODE_CLOSE1_WAIT_s19/I0 |
| 33.546 | 0.379 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_MODE_CLOSE1_WAIT_s19/F |
| 33.816 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | |||
| 40.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 40.261 | 0.261 | tCL | RR | 3642 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 40.531 | 0.270 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0/CLK |
| 40.496 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0 | ||
| 40.450 | -0.046 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0 |
| Clock Skew: | 0.261 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
| Arrival Data Path Delay: | cell: 1.651, 46.549%; route: 1.620, 45.685%; tC2Q: 0.275, 7.766% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |