Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12.02_SP2_x64\IDE\ipcore\MIPI_BYTE_TO_PIXEL\data\byte_to_pixel.v
D:\Gowin\Gowin_V1.9.12.02_SP2_x64\IDE\ipcore\MIPI_BYTE_TO_PIXEL\data\byte_to_pixel_wrap.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.02_SP2 (64-bit)
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version B
Created Time Mon Nov 2 17:05:27 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module MIPI_Byte_to_Pixel_Converter_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.228s, Peak memory usage = 107.852MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 108.023MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 108.480MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 108.566MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 108.727MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 109.090MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 109.215MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 109.305MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 109.391MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 109.398MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 109.398MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 109.398MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.399s, Peak memory usage = 142.336MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.094s, Peak memory usage = 142.492MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 142.492MB
Total Time and Memory Usage CPU time = 0h 0m 0.792s, Elapsed time = 0h 0m 0.801s, Peak memory usage = 142.492MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 55
I/O Buf 55
    IBUF 45
    OBUF 10
Register 207
    DFFSE 2
    DFFRE 52
    DFFPE 7
    DFFCE 146
LUT 137
    LUT2 23
    LUT3 36
    LUT4 78
ALU 20
    ALU 20
INV 6
    INV 6
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 163(143 LUT, 20 ALU) / 23040 <1%
Register 207 / 23685 <1%
  --Register as Latch 0 / 23685 0%
  --Register as FF 207 / 23685 <1%
BSRAM 1 / 56 2%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 I_BYTE_CLK Base 10.000 100.000 0.000 5.000 I_BYTE_CLK_ibuf/I
2 I_PIXEL_CLK Base 10.000 100.000 0.000 5.000 I_PIXEL_CLK_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_BYTE_CLK 100.000(MHz) 255.369(MHz) 7 TOP
2 I_PIXEL_CLK 100.000(MHz) 315.209(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.084
Data Arrival Time 4.140
Data Required Time 10.224
From u_b2p_inst/u_mid_fifo/rRPtrWsync_3_s0
To u_b2p_inst/u_mid_fifo/rFull_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.000 0.000 tINS RR 162 I_BYTE_CLK_ibuf/O
0.270 0.270 tNET RR 1 u_b2p_inst/u_mid_fifo/rRPtrWsync_3_s0/CLK
0.545 0.275 tC2Q RR 2 u_b2p_inst/u_mid_fifo/rRPtrWsync_3_s0/Q
0.815 0.270 tNET RR 1 u_b2p_inst/u_mid_fifo/wRPtrBinX_3_s0/I0
1.194 0.379 tINS RR 5 u_b2p_inst/u_mid_fifo/wRPtrBinX_3_s0/F
1.464 0.270 tNET RR 1 u_b2p_inst/u_mid_fifo/wRPtrBinX_2_s0/I1
1.836 0.372 tINS RR 1 u_b2p_inst/u_mid_fifo/wRPtrBinX_2_s0/F
2.106 0.270 tNET RR 2 u_b2p_inst/u_mid_fifo/n401_s0/I1
2.511 0.405 tINS RF 1 u_b2p_inst/u_mid_fifo/n401_s0/COUT
2.511 0.000 tNET FF 2 u_b2p_inst/u_mid_fifo/n402_s0/CIN
2.547 0.036 tINS FR 1 u_b2p_inst/u_mid_fifo/n402_s0/COUT
2.547 0.000 tNET RR 2 u_b2p_inst/u_mid_fifo/n403_s0/CIN
2.583 0.036 tINS RR 1 u_b2p_inst/u_mid_fifo/n403_s0/COUT
2.583 0.000 tNET RR 2 u_b2p_inst/u_mid_fifo/n404_s0/CIN
2.619 0.036 tINS RR 1 u_b2p_inst/u_mid_fifo/n404_s0/COUT
2.889 0.270 tNET RR 1 u_b2p_inst/u_mid_fifo/n418_s3/I0
3.268 0.379 tINS RR 1 u_b2p_inst/u_mid_fifo/n418_s3/F
3.538 0.270 tNET RR 1 u_b2p_inst/u_mid_fifo/n418_s0/I2
3.870 0.332 tINS RR 1 u_b2p_inst/u_mid_fifo/n418_s0/F
4.140 0.270 tNET RR 1 u_b2p_inst/u_mid_fifo/rFull_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.000 0.000 tINS RR 162 I_BYTE_CLK_ibuf/O
10.270 0.270 tNET RR 1 u_b2p_inst/u_mid_fifo/rFull_s0/CLK
10.224 -0.046 tSu 1 u_b2p_inst/u_mid_fifo/rFull_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay: cell: 1.975, 51.024%; route: 1.620, 41.860%; tC2Q: 0.275, 7.116%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 2

Path Summary:
Slack 6.775
Data Arrival Time 3.271
Data Required Time 10.046
From u_b2p_inst/wc_cnt_dec_9_s1
To u_b2p_inst/mid_offset_0_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.000 0.000 tINS RR 162 I_BYTE_CLK_ibuf/O
0.270 0.270 tNET RR 1 u_b2p_inst/wc_cnt_dec_9_s1/CLK
0.545 0.275 tC2Q RR 4 u_b2p_inst/wc_cnt_dec_9_s1/Q
0.815 0.270 tNET RR 1 u_b2p_inst/n1149_s3/I0
1.194 0.379 tINS RR 3 u_b2p_inst/n1149_s3/F
1.464 0.270 tNET RR 1 u_b2p_inst/mid_offset_3_s5/I2
1.796 0.332 tINS RR 1 u_b2p_inst/mid_offset_3_s5/F
2.066 0.270 tNET RR 1 u_b2p_inst/mid_offset_3_s4/I2
2.398 0.332 tINS RR 2 u_b2p_inst/mid_offset_3_s4/F
2.668 0.270 tNET RR 1 u_b2p_inst/mid_offset_1_s4/I2
3.001 0.332 tINS RR 2 u_b2p_inst/mid_offset_1_s4/F
3.271 0.270 tNET RR 1 u_b2p_inst/mid_offset_0_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.000 0.000 tINS RR 162 I_BYTE_CLK_ibuf/O
10.270 0.270 tNET RR 1 u_b2p_inst/mid_offset_0_s1/CLK
10.046 -0.224 tSu 1 u_b2p_inst/mid_offset_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay: cell: 1.375, 45.831%; route: 1.350, 44.991%; tC2Q: 0.275, 9.178%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 3

Path Summary:
Slack 6.775
Data Arrival Time 3.271
Data Required Time 10.046
From u_b2p_inst/wc_cnt_dec_9_s1
To u_b2p_inst/mid_offset_1_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.000 0.000 tINS RR 162 I_BYTE_CLK_ibuf/O
0.270 0.270 tNET RR 1 u_b2p_inst/wc_cnt_dec_9_s1/CLK
0.545 0.275 tC2Q RR 4 u_b2p_inst/wc_cnt_dec_9_s1/Q
0.815 0.270 tNET RR 1 u_b2p_inst/n1149_s3/I0
1.194 0.379 tINS RR 3 u_b2p_inst/n1149_s3/F
1.464 0.270 tNET RR 1 u_b2p_inst/mid_offset_3_s5/I2
1.796 0.332 tINS RR 1 u_b2p_inst/mid_offset_3_s5/F
2.066 0.270 tNET RR 1 u_b2p_inst/mid_offset_3_s4/I2
2.398 0.332 tINS RR 2 u_b2p_inst/mid_offset_3_s4/F
2.668 0.270 tNET RR 1 u_b2p_inst/mid_offset_1_s4/I2
3.001 0.332 tINS RR 2 u_b2p_inst/mid_offset_1_s4/F
3.271 0.270 tNET RR 1 u_b2p_inst/mid_offset_1_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.000 0.000 tINS RR 162 I_BYTE_CLK_ibuf/O
10.270 0.270 tNET RR 1 u_b2p_inst/mid_offset_1_s1/CLK
10.046 -0.224 tSu 1 u_b2p_inst/mid_offset_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay: cell: 1.375, 45.831%; route: 1.350, 44.991%; tC2Q: 0.275, 9.178%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 4

Path Summary:
Slack 6.775
Data Arrival Time 3.271
Data Required Time 10.046
From u_b2p_inst/wc_cnt_dec_9_s1
To u_b2p_inst/mid_offset_3_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.000 0.000 tINS RR 162 I_BYTE_CLK_ibuf/O
0.270 0.270 tNET RR 1 u_b2p_inst/wc_cnt_dec_9_s1/CLK
0.545 0.275 tC2Q RR 4 u_b2p_inst/wc_cnt_dec_9_s1/Q
0.815 0.270 tNET RR 1 u_b2p_inst/n1149_s3/I0
1.194 0.379 tINS RR 3 u_b2p_inst/n1149_s3/F
1.464 0.270 tNET RR 1 u_b2p_inst/mid_offset_3_s5/I2
1.796 0.332 tINS RR 1 u_b2p_inst/mid_offset_3_s5/F
2.066 0.270 tNET RR 1 u_b2p_inst/mid_offset_3_s4/I2
2.398 0.332 tINS RR 2 u_b2p_inst/mid_offset_3_s4/F
2.668 0.270 tNET RR 1 u_b2p_inst/mid_offset_3_s7/I2
3.001 0.332 tINS RR 1 u_b2p_inst/mid_offset_3_s7/F
3.271 0.270 tNET RR 1 u_b2p_inst/mid_offset_3_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.000 0.000 tINS RR 162 I_BYTE_CLK_ibuf/O
10.270 0.270 tNET RR 1 u_b2p_inst/mid_offset_3_s1/CLK
10.046 -0.224 tSu 1 u_b2p_inst/mid_offset_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay: cell: 1.375, 45.831%; route: 1.350, 44.991%; tC2Q: 0.275, 9.178%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 5

Path Summary:
Slack 6.820
Data Arrival Time 3.404
Data Required Time 10.224
From u_b2p_inst/wc_cnt_dec_1_s3
To u_b2p_inst/wc_cnt_dec_15_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.000 0.000 tINS RR 162 I_BYTE_CLK_ibuf/O
0.270 0.270 tNET RR 1 u_b2p_inst/wc_cnt_dec_1_s3/CLK
0.545 0.275 tC2Q RR 6 u_b2p_inst/wc_cnt_dec_1_s3/Q
0.815 0.270 tNET RR 1 u_b2p_inst/n1157_s1/I0
1.194 0.379 tINS RR 8 u_b2p_inst/n1157_s1/F
1.464 0.270 tNET RR 1 u_b2p_inst/n1149_s1/I1
1.836 0.372 tINS RR 3 u_b2p_inst/n1149_s1/F
2.106 0.270 tNET RR 1 u_b2p_inst/n1147_s3/I0
2.485 0.379 tINS RR 1 u_b2p_inst/n1147_s3/F
2.755 0.270 tNET RR 1 u_b2p_inst/n1147_s0/I0
3.134 0.379 tINS RR 1 u_b2p_inst/n1147_s0/F
3.404 0.270 tNET RR 1 u_b2p_inst/wc_cnt_dec_15_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.000 0.000 tINS RR 162 I_BYTE_CLK_ibuf/O
10.270 0.270 tNET RR 1 u_b2p_inst/wc_cnt_dec_15_s1/CLK
10.224 -0.046 tSu 1 u_b2p_inst/wc_cnt_dec_15_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay: cell: 1.508, 48.133%; route: 1.350, 43.079%; tC2Q: 0.275, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%