Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12.02_SP2_x64\IDE\ipcore\MIPI_DSI_CSI2_RX\data\dsi_csi2_rx_wrap.v
D:\Gowin\Gowin_V1.9.12.02_SP2_x64\IDE\ipcore\MIPI_DSI_CSI2_RX\data\dsi_csi2_rx.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.02_SP2 (64-bit)
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version B
Created Time Tue Nov 3 14:40:56 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module MIPI_DSI_CSI2_RX_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.145s, Peak memory usage = 69.859MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 69.859MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 69.859MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 69.859MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 69.859MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 69.859MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 69.859MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 69.859MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 69.859MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 69.859MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 69.859MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 69.859MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.667s, Peak memory usage = 93.441MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 93.441MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 93.441MB
Total Time and Memory Usage CPU time = 0h 0m 0.777s, Elapsed time = 0h 0m 0.926s, Peak memory usage = 93.441MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 79
I/O Buf 79
    IBUF 25
    OBUF 54
Register 175
    DFFSE 16
    DFFRE 72
    DFFCE 87
LUT 187
    LUT2 18
    LUT3 64
    LUT4 105
ALU 9
    ALU 9
INV 2
    INV 2

Resource Utilization Summary

Resource Usage Utilization
Logic 198(189 LUT, 9 ALU) / 23040 <1%
Register 175 / 23685 <1%
  --Register as Latch 0 / 23685 0%
  --Register as FF 175 / 23685 <1%
BSRAM 0 / 56 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 I_BYTE_CLK Base 10.000 100.000 0.000 5.000 I_BYTE_CLK_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_BYTE_CLK 100.000(MHz) 297.805(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.642
Data Arrival Time 3.404
Data Required Time 10.046
From u_dsi_csi2/rDataReg_17_s0
To u_dsi_csi2/rHeader_0_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.000 0.000 tINS RR 175 I_BYTE_CLK_ibuf/O
0.270 0.270 tNET RR 1 u_dsi_csi2/rDataReg_17_s0/CLK
0.545 0.275 tC2Q RR 5 u_dsi_csi2/rDataReg_17_s0/Q
0.815 0.270 tNET RR 1 u_dsi_csi2/wHeader_1_s1/I0
1.194 0.379 tINS RR 2 u_dsi_csi2/wHeader_1_s1/F
1.464 0.270 tNET RR 1 u_dsi_csi2/n967_s7/I0
1.843 0.379 tINS RR 2 u_dsi_csi2/n967_s7/F
2.113 0.270 tNET RR 1 u_dsi_csi2/n967_s3/I0
2.492 0.379 tINS RR 1 u_dsi_csi2/n967_s3/F
2.762 0.270 tNET RR 1 u_dsi_csi2/n967_s1/I1
3.134 0.372 tINS RR 32 u_dsi_csi2/n967_s1/F
3.404 0.270 tNET RR 1 u_dsi_csi2/rHeader_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.000 0.000 tINS RR 175 I_BYTE_CLK_ibuf/O
10.270 0.270 tNET RR 1 u_dsi_csi2/rHeader_0_s0/CLK
10.046 -0.224 tSu 1 u_dsi_csi2/rHeader_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay: cell: 1.508, 48.133%; route: 1.350, 43.079%; tC2Q: 0.275, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 2

Path Summary:
Slack 6.642
Data Arrival Time 3.404
Data Required Time 10.046
From u_dsi_csi2/rDataReg_17_s0
To u_dsi_csi2/rHeader_1_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.000 0.000 tINS RR 175 I_BYTE_CLK_ibuf/O
0.270 0.270 tNET RR 1 u_dsi_csi2/rDataReg_17_s0/CLK
0.545 0.275 tC2Q RR 5 u_dsi_csi2/rDataReg_17_s0/Q
0.815 0.270 tNET RR 1 u_dsi_csi2/wHeader_1_s1/I0
1.194 0.379 tINS RR 2 u_dsi_csi2/wHeader_1_s1/F
1.464 0.270 tNET RR 1 u_dsi_csi2/n967_s7/I0
1.843 0.379 tINS RR 2 u_dsi_csi2/n967_s7/F
2.113 0.270 tNET RR 1 u_dsi_csi2/n967_s3/I0
2.492 0.379 tINS RR 1 u_dsi_csi2/n967_s3/F
2.762 0.270 tNET RR 1 u_dsi_csi2/n967_s1/I1
3.134 0.372 tINS RR 32 u_dsi_csi2/n967_s1/F
3.404 0.270 tNET RR 1 u_dsi_csi2/rHeader_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.000 0.000 tINS RR 175 I_BYTE_CLK_ibuf/O
10.270 0.270 tNET RR 1 u_dsi_csi2/rHeader_1_s0/CLK
10.046 -0.224 tSu 1 u_dsi_csi2/rHeader_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay: cell: 1.508, 48.133%; route: 1.350, 43.079%; tC2Q: 0.275, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 3

Path Summary:
Slack 6.642
Data Arrival Time 3.404
Data Required Time 10.046
From u_dsi_csi2/rDataReg_17_s0
To u_dsi_csi2/rHeader_2_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.000 0.000 tINS RR 175 I_BYTE_CLK_ibuf/O
0.270 0.270 tNET RR 1 u_dsi_csi2/rDataReg_17_s0/CLK
0.545 0.275 tC2Q RR 5 u_dsi_csi2/rDataReg_17_s0/Q
0.815 0.270 tNET RR 1 u_dsi_csi2/wHeader_1_s1/I0
1.194 0.379 tINS RR 2 u_dsi_csi2/wHeader_1_s1/F
1.464 0.270 tNET RR 1 u_dsi_csi2/n967_s7/I0
1.843 0.379 tINS RR 2 u_dsi_csi2/n967_s7/F
2.113 0.270 tNET RR 1 u_dsi_csi2/n967_s3/I0
2.492 0.379 tINS RR 1 u_dsi_csi2/n967_s3/F
2.762 0.270 tNET RR 1 u_dsi_csi2/n967_s1/I1
3.134 0.372 tINS RR 32 u_dsi_csi2/n967_s1/F
3.404 0.270 tNET RR 1 u_dsi_csi2/rHeader_2_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.000 0.000 tINS RR 175 I_BYTE_CLK_ibuf/O
10.270 0.270 tNET RR 1 u_dsi_csi2/rHeader_2_s0/CLK
10.046 -0.224 tSu 1 u_dsi_csi2/rHeader_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay: cell: 1.508, 48.133%; route: 1.350, 43.079%; tC2Q: 0.275, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 4

Path Summary:
Slack 6.642
Data Arrival Time 3.404
Data Required Time 10.046
From u_dsi_csi2/rDataReg_17_s0
To u_dsi_csi2/rHeader_3_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.000 0.000 tINS RR 175 I_BYTE_CLK_ibuf/O
0.270 0.270 tNET RR 1 u_dsi_csi2/rDataReg_17_s0/CLK
0.545 0.275 tC2Q RR 5 u_dsi_csi2/rDataReg_17_s0/Q
0.815 0.270 tNET RR 1 u_dsi_csi2/wHeader_1_s1/I0
1.194 0.379 tINS RR 2 u_dsi_csi2/wHeader_1_s1/F
1.464 0.270 tNET RR 1 u_dsi_csi2/n967_s7/I0
1.843 0.379 tINS RR 2 u_dsi_csi2/n967_s7/F
2.113 0.270 tNET RR 1 u_dsi_csi2/n967_s3/I0
2.492 0.379 tINS RR 1 u_dsi_csi2/n967_s3/F
2.762 0.270 tNET RR 1 u_dsi_csi2/n967_s1/I1
3.134 0.372 tINS RR 32 u_dsi_csi2/n967_s1/F
3.404 0.270 tNET RR 1 u_dsi_csi2/rHeader_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.000 0.000 tINS RR 175 I_BYTE_CLK_ibuf/O
10.270 0.270 tNET RR 1 u_dsi_csi2/rHeader_3_s0/CLK
10.046 -0.224 tSu 1 u_dsi_csi2/rHeader_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay: cell: 1.508, 48.133%; route: 1.350, 43.079%; tC2Q: 0.275, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 5

Path Summary:
Slack 6.642
Data Arrival Time 3.404
Data Required Time 10.046
From u_dsi_csi2/rDataReg_17_s0
To u_dsi_csi2/rHeader_4_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.000 0.000 tINS RR 175 I_BYTE_CLK_ibuf/O
0.270 0.270 tNET RR 1 u_dsi_csi2/rDataReg_17_s0/CLK
0.545 0.275 tC2Q RR 5 u_dsi_csi2/rDataReg_17_s0/Q
0.815 0.270 tNET RR 1 u_dsi_csi2/wHeader_1_s1/I0
1.194 0.379 tINS RR 2 u_dsi_csi2/wHeader_1_s1/F
1.464 0.270 tNET RR 1 u_dsi_csi2/n967_s7/I0
1.843 0.379 tINS RR 2 u_dsi_csi2/n967_s7/F
2.113 0.270 tNET RR 1 u_dsi_csi2/n967_s3/I0
2.492 0.379 tINS RR 1 u_dsi_csi2/n967_s3/F
2.762 0.270 tNET RR 1 u_dsi_csi2/n967_s1/I1
3.134 0.372 tINS RR 32 u_dsi_csi2/n967_s1/F
3.404 0.270 tNET RR 1 u_dsi_csi2/rHeader_4_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.000 0.000 tINS RR 175 I_BYTE_CLK_ibuf/O
10.270 0.270 tNET RR 1 u_dsi_csi2/rHeader_4_s0/CLK
10.046 -0.224 tSu 1 u_dsi_csi2/rHeader_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay: cell: 1.508, 48.133%; route: 1.350, 43.079%; tC2Q: 0.275, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%