Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12.02_SP2_x64\IDE\ipcore\VFB\data\vfb_top.v
D:\Gowin\Gowin_V1.9.12.02_SP2_x64\IDE\ipcore\VFB\data\vfb_wrapper.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.02_SP2 (64-bit)
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version B
Created Time Mon Nov 2 17:05:32 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Video_Frame_Buffer_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.242s, Peak memory usage = 105.023MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 105.133MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 105.492MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 105.555MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 105.699MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 106.141MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 106.266MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 106.363MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 106.449MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 106.457MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 106.457MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 106.457MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 136.438MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.131s, Peak memory usage = 136.438MB
Generate output files:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 136.438MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 136.438MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 356
I/O Buf 355
    IBUF 158
    OBUF 197
Register 336
    DFFSE 8
    DFFRE 2
    DFFPE 32
    DFFCE 294
LUT 722
    LUT2 211
    LUT3 215
    LUT4 296
ALU 34
    ALU 34
INV 5
    INV 5
BSRAM 8
    SDPB 8

Resource Utilization Summary

Resource Usage Utilization
Logic 761(727 LUT, 34 ALU) / 23040 4%
Register 336 / 23685 2%
  --Register as Latch 0 / 23685 0%
  --Register as FF 336 / 23685 2%
BSRAM 8 / 56 15%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 I_vin0_clk Base 10.000 100.000 0.000 5.000 I_vin0_clk_ibuf/I
2 I_dma_clk Base 10.000 100.000 0.000 5.000 I_dma_clk_ibuf/I
3 I_vout0_clk Base 10.000 100.000 0.000 5.000 I_vout0_clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_vin0_clk 100.000(MHz) 267.223(MHz) 6 TOP
2 I_dma_clk 100.000(MHz) 206.603(MHz) 9 TOP
3 I_vout0_clk 100.000(MHz) 215.540(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.160
Data Arrival Time 5.064
Data Required Time 10.224
From vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_6_s1
To vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.000 0.000 tINS RR 230 I_dma_clk_ibuf/O
0.270 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_6_s1/CLK
0.545 0.275 tC2Q RR 4 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_6_s1/Q
0.815 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma0_wr_data_end_s/I0
1.194 0.379 tINS RR 24 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma0_wr_data_end_s/F
1.464 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3
1.653 0.189 tINS RR 8 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F
1.923 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3
2.112 0.189 tINS RR 8 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F
2.382 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s3/I1
2.754 0.372 tINS RR 4 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s3/F
3.024 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_5_s1/I0
3.403 0.379 tINS RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_5_s1/F
3.673 0.270 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n698_s0/I0
4.073 0.400 tINS RF 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n698_s0/COUT
4.073 0.000 tNET FF 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n699_s0/CIN
4.109 0.036 tINS FR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n699_s0/COUT
4.109 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n700_s0/CIN
4.145 0.036 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n700_s0/COUT
4.415 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/I0
4.794 0.379 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/F
5.064 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.000 0.000 tINS RR 230 I_dma_clk_ibuf/O
10.270 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/CLK
10.224 -0.046 tSu 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay: cell: 2.359, 49.202%; route: 2.160, 45.054%; tC2Q: 0.275, 5.744%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 2

Path Summary:
Slack 5.360
Data Arrival Time 4.864
Data Required Time 10.224
From vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_0_s0
To vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0
Launch Clk I_vout0_clk[R]
Latch Clk I_vout0_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 I_vout0_clk
0.000 0.000 tCL RR 1 I_vout0_clk_ibuf/I
0.000 0.000 tINS RR 58 I_vout0_clk_ibuf/O
0.270 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_0_s0/CLK
0.545 0.275 tC2Q RR 11 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_0_s0/Q
0.815 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_15_s6/I0
1.194 0.379 tINS RR 19 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_15_s6/F
1.464 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_3_s5/I2
1.796 0.332 tINS RR 4 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_3_s5/F
2.066 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s5/I0
2.445 0.379 tINS RR 3 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s5/F
2.715 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_2_s1/I0
3.094 0.379 tINS RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_2_s1/F
3.364 0.270 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n623_s0/I0
3.765 0.400 tINS RF 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n623_s0/COUT
3.765 0.000 tNET FF 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n624_s0/CIN
3.801 0.036 tINS FR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n624_s0/COUT
3.801 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n625_s0/CIN
3.837 0.036 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n625_s0/COUT
3.837 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n626_s0/CIN
3.873 0.036 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n626_s0/COUT
3.873 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n627_s0/CIN
3.909 0.036 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n627_s0/COUT
3.909 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n628_s0/CIN
3.945 0.036 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n628_s0/COUT
4.215 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/I0
4.594 0.379 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/F
4.864 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 I_vout0_clk
10.000 0.000 tCL RR 1 I_vout0_clk_ibuf/I
10.000 0.000 tINS RR 58 I_vout0_clk_ibuf/O
10.270 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/CLK
10.224 -0.046 tSu 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay: cell: 2.428, 52.861%; route: 1.890, 41.144%; tC2Q: 0.275, 5.995%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 3

Path Summary:
Slack 6.218
Data Arrival Time 4.006
Data Required Time 10.224
From vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0
To vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.000 0.000 tINS RR 230 I_dma_clk_ibuf/O
0.270 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLK
0.545 0.275 tC2Q RR 2 vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/Q
0.815 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s2/I0
1.194 0.379 tINS RR 142 vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s2/F
1.464 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_5_s1/I0
1.843 0.379 tINS RR 10 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_5_s1/F
2.113 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s4/I1
2.485 0.372 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s4/F
2.755 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s2/I0
3.134 0.379 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s2/F
3.404 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s0/I2
3.736 0.332 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s0/F
4.006 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.000 0.000 tINS RR 230 I_dma_clk_ibuf/O
10.270 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0/CLK
10.224 -0.046 tSu 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay: cell: 1.840, 49.265%; route: 1.620, 43.363%; tC2Q: 0.275, 7.372%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 4

Path Summary:
Slack 6.225
Data Arrival Time 3.999
Data Required Time 10.224
From vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1
To vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_25_s1
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.000 0.000 tINS RR 230 I_dma_clk_ibuf/O
0.270 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1/CLK
0.545 0.275 tC2Q RR 3 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1/Q
0.815 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n189_s3/I0
1.194 0.379 tINS RR 7 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n189_s3/F
1.464 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n180_s3/I1
1.836 0.372 tINS RR 4 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n180_s3/F
2.106 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n175_s3/I2
2.438 0.332 tINS RR 5 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n175_s3/F
2.708 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n172_s4/I0
3.087 0.379 tINS RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n172_s4/F
3.357 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n171_s2/I1
3.729 0.372 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n171_s2/F
3.999 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_25_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.000 0.000 tINS RR 230 I_dma_clk_ibuf/O
10.270 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_25_s1/CLK
10.224 -0.046 tSu 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_25_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay: cell: 1.833, 49.167%; route: 1.620, 43.447%; tC2Q: 0.275, 7.386%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 5

Path Summary:
Slack 6.225
Data Arrival Time 3.999
Data Required Time 10.224
From vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_6_s1
To vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_25_s1
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.000 0.000 tINS RR 230 I_dma_clk_ibuf/O
0.270 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_6_s1/CLK
0.545 0.275 tC2Q RR 3 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_6_s1/Q
0.815 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n315_s3/I0
1.194 0.379 tINS RR 7 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n315_s3/F
1.464 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n306_s3/I1
1.836 0.372 tINS RR 4 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n306_s3/F
2.106 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n301_s3/I2
2.438 0.332 tINS RR 5 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n301_s3/F
2.708 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n298_s4/I0
3.087 0.379 tINS RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n298_s4/F
3.357 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n297_s2/I1
3.729 0.372 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n297_s2/F
3.999 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_25_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.000 0.000 tINS RR 230 I_dma_clk_ibuf/O
10.270 0.270 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_25_s1/CLK
10.224 -0.046 tSu 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_25_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay: cell: 1.833, 49.167%; route: 1.620, 43.447%; tC2Q: 0.275, 7.386%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.270, 100.000%