| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| start_and_end_top|vga_select_module |
18 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| start_and_end_top|end_top|U4|altsyncram_component|auto_generated |
9 |
0 |
0 |
0 |
256 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| start_and_end_top|end_top|U4 |
9 |
0 |
0 |
0 |
256 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| start_and_end_top|end_top|U3 |
281 |
2 |
0 |
2 |
14 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| start_and_end_top|end_top|U2 |
2 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| start_and_end_top|end_top |
2 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| start_and_end_top|start_top|U4|altsyncram_component|auto_generated |
9 |
0 |
0 |
0 |
256 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| start_and_end_top|start_top|U4 |
9 |
0 |
0 |
0 |
256 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| start_and_end_top|start_top|U3 |
281 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| start_and_end_top|start_top|U2 |
2 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| start_and_end_top|start_top |
2 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| start_and_end_top |
10 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U7 |
6 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U6 |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U5 |
15 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U4 |
31 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3 |
14 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U2 |
8 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| pll_inst|altpll_component|auto_generated |
3 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| pll_inst |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |