| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| all_clk_creat|altpll_component|auto_generated |
3 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| all_clk_creat |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|wrfull_eq_comp |
26 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|rdempty_eq_comp |
26 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe16 |
15 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|ws_dgrp |
15 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|ws_bwp |
15 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|ws_brp |
15 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe13 |
15 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|rs_dgwp |
15 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|rs_bwp |
15 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|rs_brp |
15 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|fifo_ram |
45 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|ws_dgrp_gray2bin |
13 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|wrptr_g_gray2bin |
13 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|rs_dgwp_gray2bin |
13 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated|rdptr_g_gray2bin |
13 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo|dcfifo_component|auto_generated |
21 |
0 |
0 |
0 |
42 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_rd_fifo |
21 |
0 |
0 |
0 |
41 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|cntr_b |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp |
16 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp |
16 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe17 |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|ws_bwp |
11 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|ws_brp |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13 |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|rs_bwp |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|rs_brp |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|fifo_ram |
28 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp_gray2bin |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|wrptr_g_gray2bin |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo|dcfifo_mixed_widths_component|auto_generated |
13 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sd_wr_fifo |
13 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sdram_control|sdram_init |
2 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| sdram_control_top|sdram_control |
48 |
2 |
4 |
2 |
42 |
2 |
2 |
2 |
16 |
0 |
0 |
0 |
0 |
| sdram_control_top |
115 |
98 |
0 |
98 |
38 |
98 |
98 |
98 |
16 |
0 |
0 |
0 |
0 |
| tft_ctrl |
18 |
1 |
11 |
1 |
22 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| uart_byte_rx |
6 |
3 |
0 |
3 |
9 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |