# Reading D:/altera/13.0/modelsim_ase/tcl/vsim/pref.tcl 
# do data_acq_run_msim_rtl_verilog.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying D:\altera\13.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied D:\altera\13.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
# 
# vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl {E:/FPGA/week05/day03/rtl/uart_byte_rx.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module uart_byte_rx
# 
# Top level modules:
# 	uart_byte_rx
# vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj {E:/FPGA/week05/day03/prj/myisp.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module myisp
# 
# Top level modules:
# 	myisp
# vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl {E:/FPGA/week05/day03/rtl/tlv5618.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module tlv5618
# 
# Top level modules:
# 	tlv5618
# vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl {E:/FPGA/week05/day03/rtl/key_filter.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module key_filter
# 
# Top level modules:
# 	key_filter
# vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj/ip {E:/FPGA/week05/day03/prj/ip/myfifo.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module myfifo
# 
# Top level modules:
# 	myfifo
# vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl {E:/FPGA/week05/day03/rtl/adc_driver.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module adc_driver
# 
# Top level modules:
# 	adc_driver
# vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl {E:/FPGA/week05/day03/rtl/uart_byte_tx.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module uart_byte_tx
# 
# Top level modules:
# 	uart_byte_tx
# vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl {E:/FPGA/week05/day03/rtl/ctrl.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module ctrl
# 
# Top level modules:
# 	ctrl
# vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl {E:/FPGA/week05/day03/rtl/data_acq.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module data_acq
# 
# Top level modules:
# 	data_acq
# vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj {E:/FPGA/week05/day03/prj/acq_uart_cmd.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module acq_uart_cmd
# 
# Top level modules:
# 	acq_uart_cmd
# 
# vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj/../tb {E:/FPGA/week05/day03/prj/../tb/data_acq_tb.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module data_acq_tb
# 
# Top level modules:
# 	data_acq_tb
# vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj/../tb {E:/FPGA/week05/day03/prj/../tb/key_model.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module key_model
# 
# Top level modules:
# 	key_model
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  data_acq_tb
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps data_acq_tb 
# Loading work.data_acq_tb
# Loading work.data_acq
# Loading work.adc_driver
# Loading work.ctrl
# Loading work.key_filter
# Loading work.myfifo
# Loading altera_mf_ver.scfifo
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading work.uart_byte_tx
# Loading work.tlv5618
# Loading work.myisp
# Loading altera_mf_ver.altsource_probe
# Loading work.uart_byte_rx
# Loading work.acq_uart_cmd
# Loading work.key_model
# ** Warning: (vsim-3017) E:/FPGA/week05/day03/prj/../tb/data_acq_tb.v(54): [TFMPC] - Too few port connections. Expected 13, found 12.
# 
#         Region: /data_acq_tb/data_acq
# ** Warning: (vsim-3722) E:/FPGA/week05/day03/prj/../tb/data_acq_tb.v(54): [TFMPC] - Missing connection for port 'led'.
# 
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
add wave -position end  sim:/data_acq_tb/data_acq/ADC_START
add wave -position end  sim:/data_acq_tb/data_acq/START
add wave -position end  sim:/data_acq_tb/data_acq/ctrl/RE_DONE_CNT
run -all
restart
# ** Warning: (vsim-3017) E:/FPGA/week05/day03/prj/../tb/data_acq_tb.v(54): [TFMPC] - Too few port connections. Expected 13, found 12.
# 
#         Region: /data_acq_tb/data_acq
# ** Warning: (vsim-3722) E:/FPGA/week05/day03/prj/../tb/data_acq_tb.v(54): [TFMPC] - Missing connection for port 'led'.
# 
run -all
add wave -position end  sim:/data_acq_tb/data_acq/acq_uart_cmd/switch
add wave -position end  sim:/data_acq_tb/data_acq/acq_uart_cmd/led
add wave -position end  sim:/data_acq_tb/data_acq/acq_uart_cmd/acq_num
add wave -position end  sim:/data_acq_tb/data_acq/acq_uart_cmd/adc_din
add wave -position end  sim:/data_acq_tb/data_acq/acq_uart_cmd/data_str
restart
# ** Warning: (vsim-3017) E:/FPGA/week05/day03/prj/../tb/data_acq_tb.v(54): [TFMPC] - Too few port connections. Expected 13, found 12.
# 
#         Region: /data_acq_tb/data_acq
# ** Warning: (vsim-3722) E:/FPGA/week05/day03/prj/../tb/data_acq_tb.v(54): [TFMPC] - Missing connection for port 'led'.
# 
run -all
add wave -position end  sim:/data_acq_tb/tx_data
restart
# ** Warning: (vsim-3017) E:/FPGA/week05/day03/prj/../tb/data_acq_tb.v(54): [TFMPC] - Too few port connections. Expected 13, found 12.
# 
#         Region: /data_acq_tb/data_acq
# ** Warning: (vsim-3722) E:/FPGA/week05/day03/prj/../tb/data_acq_tb.v(54): [TFMPC] - Missing connection for port 'led'.
# 
run -all
add wave -position end  sim:/data_acq_tb/data_acq/ctrl/RE_DONE
restart
# ** Warning: (vsim-3017) E:/FPGA/week05/day03/prj/../tb/data_acq_tb.v(54): [TFMPC] - Too few port connections. Expected 13, found 12.
# 
#         Region: /data_acq_tb/data_acq
# ** Warning: (vsim-3722) E:/FPGA/week05/day03/prj/../tb/data_acq_tb.v(54): [TFMPC] - Missing connection for port 'led'.
# 
run -all
add wave -position end  sim:/data_acq_tb/data_acq/tx_data
restart
# ** Warning: (vsim-3017) E:/FPGA/week05/day03/prj/../tb/data_acq_tb.v(54): [TFMPC] - Too few port connections. Expected 13, found 12.
# 
#         Region: /data_acq_tb/data_acq
# ** Warning: (vsim-3722) E:/FPGA/week05/day03/prj/../tb/data_acq_tb.v(54): [TFMPC] - Missing connection for port 'led'.
# 
run -all
add wave -position 3  sim:/data_acq_tb/data_acq/acq_uart_cmd/switch_cnt
restart
# ** Warning: (vsim-3017) E:/FPGA/week05/day03/prj/../tb/data_acq_tb.v(54): [TFMPC] - Too few port connections. Expected 13, found 12.
# 
#         Region: /data_acq_tb/data_acq
# ** Warning: (vsim-3722) E:/FPGA/week05/day03/prj/../tb/data_acq_tb.v(54): [TFMPC] - Missing connection for port 'led'.
# 
run -all
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj -O0 E:/FPGA/week05/day03/prj/acq_uart_cmd.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module acq_uart_cmd
# 
# Top level modules:
# 	acq_uart_cmd
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/adc_driver.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module adc_driver
# 
# Top level modules:
# 	adc_driver
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/ctrl.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module ctrl
# 
# Top level modules:
# 	ctrl
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/data_acq.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module data_acq
# 
# Top level modules:
# 	data_acq
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj/../tb -O0 E:/FPGA/week05/day03/tb/data_acq_tb.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module data_acq_tb
# 
# Top level modules:
# 	data_acq_tb
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/key_filter.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module key_filter
# 
# Top level modules:
# 	key_filter
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj/../tb -O0 E:/FPGA/week05/day03/tb/key_model.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module key_model
# 
# Top level modules:
# 	key_model
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj/ip -O0 E:/FPGA/week05/day03/prj/ip/myfifo.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module myfifo
# 
# Top level modules:
# 	myfifo
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj -O0 E:/FPGA/week05/day03/prj/myisp.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module myisp
# 
# Top level modules:
# 	myisp
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/tlv5618.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module tlv5618
# 
# Top level modules:
# 	tlv5618
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/uart_byte_rx.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module uart_byte_rx
# 
# Top level modules:
# 	uart_byte_rx
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/uart_byte_tx.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module uart_byte_tx
# 
# Top level modules:
# 	uart_byte_tx
restart
# Loading work.data_acq_tb
# Loading work.data_acq
# Loading work.adc_driver
# Loading work.ctrl
# Loading work.key_filter
# Loading work.myfifo
# Loading work.uart_byte_tx
# Loading work.tlv5618
# Loading work.myisp
# Loading work.uart_byte_rx
# Loading work.acq_uart_cmd
# Loading work.key_model
# ** Warning: (vsim-3017) E:/FPGA/week05/day03/tb/data_acq_tb.v(54): [TFMPC] - Too few port connections. Expected 13, found 12.
# 
#         Region: /data_acq_tb/data_acq
# ** Warning: (vsim-3722) E:/FPGA/week05/day03/tb/data_acq_tb.v(54): [TFMPC] - Missing connection for port 'led'.
# 
run -all
# WARNING: No extended dataflow license exists
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj -O0 E:/FPGA/week05/day03/prj/acq_uart_cmd.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module acq_uart_cmd
# 
# Top level modules:
# 	acq_uart_cmd
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/adc_driver.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module adc_driver
# 
# Top level modules:
# 	adc_driver
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/ctrl.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module ctrl
# 
# Top level modules:
# 	ctrl
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/data_acq.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module data_acq
# 
# Top level modules:
# 	data_acq
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj/../tb -O0 E:/FPGA/week05/day03/tb/data_acq_tb.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module data_acq_tb
# 
# Top level modules:
# 	data_acq_tb
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/key_filter.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module key_filter
# 
# Top level modules:
# 	key_filter
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj/../tb -O0 E:/FPGA/week05/day03/tb/key_model.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module key_model
# 
# Top level modules:
# 	key_model
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj/ip -O0 E:/FPGA/week05/day03/prj/ip/myfifo.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module myfifo
# 
# Top level modules:
# 	myfifo
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj -O0 E:/FPGA/week05/day03/prj/myisp.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module myisp
# 
# Top level modules:
# 	myisp
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/tlv5618.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module tlv5618
# 
# Top level modules:
# 	tlv5618
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/uart_byte_rx.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module uart_byte_rx
# 
# Top level modules:
# 	uart_byte_rx
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/uart_byte_tx.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module uart_byte_tx
# 
# Top level modules:
# 	uart_byte_tx
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj -O0 E:/FPGA/week05/day03/prj/acq_uart_cmd.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module acq_uart_cmd
# 
# Top level modules:
# 	acq_uart_cmd
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/adc_driver.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module adc_driver
# 
# Top level modules:
# 	adc_driver
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/ctrl.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module ctrl
# 
# Top level modules:
# 	ctrl
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/data_acq.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module data_acq
# 
# Top level modules:
# 	data_acq
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj/../tb -O0 E:/FPGA/week05/day03/tb/data_acq_tb.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module data_acq_tb
# 
# Top level modules:
# 	data_acq_tb
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/key_filter.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module key_filter
# 
# Top level modules:
# 	key_filter
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj/../tb -O0 E:/FPGA/week05/day03/tb/key_model.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module key_model
# 
# Top level modules:
# 	key_model
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj/ip -O0 E:/FPGA/week05/day03/prj/ip/myfifo.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module myfifo
# 
# Top level modules:
# 	myfifo
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/prj -O0 E:/FPGA/week05/day03/prj/myisp.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module myisp
# 
# Top level modules:
# 	myisp
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/tlv5618.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module tlv5618
# 
# Top level modules:
# 	tlv5618
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/uart_byte_rx.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module uart_byte_rx
# 
# Top level modules:
# 	uart_byte_rx
vlog -vlog01compat -work work +incdir+E:/FPGA/week05/day03/rtl -O0 E:/FPGA/week05/day03/rtl/uart_byte_tx.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module uart_byte_tx
# 
# Top level modules:
# 	uart_byte_tx
restart
# Loading work.data_acq_tb
# Loading work.data_acq
# Loading work.adc_driver
# Loading work.ctrl
# Loading work.key_filter
# Loading work.myfifo
# Loading work.uart_byte_tx
# Loading work.tlv5618
# Loading work.myisp
# Loading work.uart_byte_rx
# Loading work.acq_uart_cmd
# Loading work.key_model
# ** Warning: (vsim-3017) E:/FPGA/week05/day03/tb/data_acq_tb.v(54): [TFMPC] - Too few port connections. Expected 13, found 12.
# 
#         Region: /data_acq_tb/data_acq
# ** Warning: (vsim-3722) E:/FPGA/week05/day03/tb/data_acq_tb.v(54): [TFMPC] - Missing connection for port 'led'.
# 
run -all
# Break key hit 
# Break in Module key_filter at E:/FPGA/week05/day03/rtl/key_filter.v line 30
