# Reading D:/altera/13.0/modelsim_ase/tcl/vsim/pref.tcl 
# do iic_eeprom_run_msim_rtl_verilog.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying D:\altera\13.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied D:\altera\13.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
# 
# vlog -vlog01compat -work work +incdir+D:/FPGA_workspace/lin_fang_hui/DIY_all/iic_eeprom/rtl {D:/FPGA_workspace/lin_fang_hui/DIY_all/iic_eeprom/rtl/cmd_analysis.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module cmd_analysis
# 
# Top level modules:
# 	cmd_analysis
# vlog -vlog01compat -work work +incdir+D:/FPGA_workspace/lin_fang_hui/DIY_all/iic_eeprom/prj/ip {D:/FPGA_workspace/lin_fang_hui/DIY_all/iic_eeprom/prj/ip/fifo_wr.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module fifo_wr
# 
# Top level modules:
# 	fifo_wr
# 
# vlog -vlog01compat -work work +incdir+D:/FPGA_workspace/lin_fang_hui/DIY_all/iic_eeprom/prj/../testbench {D:/FPGA_workspace/lin_fang_hui/DIY_all/iic_eeprom/prj/../testbench/tb_cmd_analysis.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module tb_cmd_analysis
# 
# Top level modules:
# 	tb_cmd_analysis
# vlog -vlog01compat -work work +incdir+D:/FPGA_workspace/lin_fang_hui/DIY_all/iic_eeprom/prj/../testbench {D:/FPGA_workspace/lin_fang_hui/DIY_all/iic_eeprom/prj/../testbench/24LC04B.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module M24LC04B
# 
# Top level modules:
# 	M24LC04B
# vlog -vlog01compat -work work +incdir+D:/FPGA_workspace/lin_fang_hui/DIY_all/iic_eeprom/prj/../testbench {D:/FPGA_workspace/lin_fang_hui/DIY_all/iic_eeprom/prj/../testbench/24LC64.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module M24LC64
# 
# Top level modules:
# 	M24LC64
# vlog -vlog01compat -work work +incdir+D:/FPGA_workspace/lin_fang_hui/DIY_all/iic_eeprom/prj/../rtl {D:/FPGA_workspace/lin_fang_hui/DIY_all/iic_eeprom/prj/../rtl/iic_ctrl.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module iic_ctrl
# 
# Top level modules:
# 	iic_ctrl
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  tb_cmd_analysis
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps tb_cmd_analysis 
# Loading work.tb_cmd_analysis
# Loading work.M24LC64
# Loading work.cmd_analysis
# Loading work.fifo_wr
# Loading altera_mf_ver.scfifo
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading work.iic_ctrl
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
# Break in Module tb_cmd_analysis at D:/FPGA_workspace/lin_fang_hui/DIY_all/iic_eeprom/prj/../testbench/tb_cmd_analysis.v line 198
# Simulation Breakpoint: Break in Module tb_cmd_analysis at D:/FPGA_workspace/lin_fang_hui/DIY_all/iic_eeprom/prj/../testbench/tb_cmd_analysis.v line 198
# MACRO ./iic_eeprom_run_msim_rtl_verilog.do PAUSED at line 21
