# Reading D:/modelism/modelsim_ase/tcl/vsim/pref.tcl
# ERROR: No extended dataflow license exists
# do Qiangdaqi_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim ALTERA vmap 10.4b Lib Mapping Utility 2015.05 May 27 2015
# vmap -modelsim_quiet work rtl_work 
# Modifying D:/modelism/modelsim_ase/win32aloem/modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+D:/zzlqutus/Qiangdaqi/rtl {D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v}
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 15:00:45 on May 11,2018
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/zzlqutus/Qiangdaqi/rtl" D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v 
# -- Compiling module Ctrl
# 
# Top level modules:
# 	Ctrl
# End time: 15:00:45 on May 11,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+D:/zzlqutus/Qiangdaqi/prj/../tb {D:/zzlqutus/Qiangdaqi/prj/../tb/ctrl_tb.v}
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 15:00:45 on May 11,2018
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/zzlqutus/Qiangdaqi/prj/../tb" D:/zzlqutus/Qiangdaqi/prj/../tb/ctrl_tb.v 
# -- Compiling module ctrl_tb
# 
# Top level modules:
# 	ctrl_tb
# End time: 15:00:45 on May 11,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  ctrl_tb
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=""+acc"" ctrl_tb 
# Start time: 15:00:47 on May 11,2018
# Loading work.ctrl_tb
# Loading work.Ctrl
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
# ** Note: $stop    : D:/zzlqutus/Qiangdaqi/prj/../tb/ctrl_tb.v(37)
#    Time: 46201 ns  Iteration: 0  Instance: /ctrl_tb
# Break in Module ctrl_tb at D:/zzlqutus/Qiangdaqi/prj/../tb/ctrl_tb.v line 37
vlog -vlog01compat -work work +incdir+D:/zzlqutus/Qiangdaqi/prj/../tb D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 15:03:54 on May 11,2018
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/zzlqutus/Qiangdaqi/prj/../tb" D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v 
# -- Compiling module ctrl_tb
# 
# Top level modules:
# 	ctrl_tb
# End time: 15:03:54 on May 11,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.ctrl_tb
run -all
# ** Note: $stop    : D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v(44)
#    Time: 46261 ns  Iteration: 0  Instance: /ctrl_tb
# Break in Module ctrl_tb at D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v line 44
run -all
add wave -position insertpoint  \
sim:/ctrl_tb/Ctrl_inst/delay_cnt \
sim:/ctrl_tb/Ctrl_inst/delay_done \
sim:/ctrl_tb/Ctrl_inst/time1_r
restart
run -all
# ** Note: $stop    : D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v(44)
#    Time: 46261 ns  Iteration: 0  Instance: /ctrl_tb
# Break in Module ctrl_tb at D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v line 44
restart
run -all
# ** Note: $stop    : D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v(44)
#    Time: 46261 ns  Iteration: 0  Instance: /ctrl_tb
# Break in Module ctrl_tb at D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v line 44
vlog -vlog01compat -work work +incdir+D:/zzlqutus/Qiangdaqi/rtl D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 15:06:07 on May 11,2018
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/zzlqutus/Qiangdaqi/rtl" D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v 
# -- Compiling module Ctrl
# 
# Top level modules:
# 	Ctrl
# End time: 15:06:07 on May 11,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.Ctrl
run -all
# ** Note: $stop    : D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v(44)
#    Time: 46261 ns  Iteration: 0  Instance: /ctrl_tb
# Break in Module ctrl_tb at D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v line 44
vlog -vlog01compat -work work +incdir+D:/zzlqutus/Qiangdaqi/rtl D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 15:11:12 on May 11,2018
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/zzlqutus/Qiangdaqi/rtl" D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v 
# -- Compiling module Ctrl
# 
# Top level modules:
# 	Ctrl
# End time: 15:11:12 on May 11,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work +incdir+D:/zzlqutus/Qiangdaqi/rtl D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 15:13:16 on May 11,2018
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/zzlqutus/Qiangdaqi/rtl" D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v 
# -- Compiling module Ctrl
# 
# Top level modules:
# 	Ctrl
# End time: 15:13:16 on May 11,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.Ctrl
run -all
# ** Note: $stop    : D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v(44)
#    Time: 46261 ns  Iteration: 0  Instance: /ctrl_tb
# Break in Module ctrl_tb at D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v line 44
vlog -vlog01compat -work work +incdir+D:/zzlqutus/Qiangdaqi/rtl D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 15:23:31 on May 11,2018
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/zzlqutus/Qiangdaqi/rtl" D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v 
# -- Compiling module Ctrl
# ** Error: D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v(41): (vlog-2730) Undefined variable: 'en0'.
# 
# ** Error: D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v(42): (vlog-2730) Undefined variable: 'en1'.
# 
# ** Error: (vlog-13069) D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v(57): near "2": syntax error, unexpected INTEGER NUMBER.
# 
# ** Error: (vlog-13069) D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v(64): near "default": syntax error, unexpected default.
# 
# End time: 15:23:31 on May 11,2018, Elapsed time: 0:00:00
# Errors: 4, Warnings: 0
# D:/modelism/modelsim_ase/win32aloem/vlog failed.
vlog -vlog01compat -work work +incdir+D:/zzlqutus/Qiangdaqi/rtl D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 15:23:44 on May 11,2018
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/zzlqutus/Qiangdaqi/rtl" D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v 
# -- Compiling module Ctrl
# ** Error: (vlog-13069) D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v(57): near "2": syntax error, unexpected INTEGER NUMBER.
# 
# ** Error: (vlog-13069) D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v(64): near "default": syntax error, unexpected default.
# 
# End time: 15:23:44 on May 11,2018, Elapsed time: 0:00:00
# Errors: 2, Warnings: 0
# D:/modelism/modelsim_ase/win32aloem/vlog failed.
vlog -vlog01compat -work work +incdir+D:/zzlqutus/Qiangdaqi/rtl D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 15:24:06 on May 11,2018
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/zzlqutus/Qiangdaqi/rtl" D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v 
# -- Compiling module Ctrl
# 
# Top level modules:
# 	Ctrl
# End time: 15:24:06 on May 11,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.Ctrl
run -all
# ** Note: $stop    : D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v(44)
#    Time: 46261 ns  Iteration: 0  Instance: /ctrl_tb
# Break in Module ctrl_tb at D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v line 44
run -all
add wave -position insertpoint  \
sim:/ctrl_tb/Ctrl_inst/en0 \
sim:/ctrl_tb/Ctrl_inst/en1
restart
run -all
# ** Note: $stop    : D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v(44)
#    Time: 46261 ns  Iteration: 0  Instance: /ctrl_tb
# Break in Module ctrl_tb at D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v line 44
vlog -vlog01compat -work work +incdir+D:/zzlqutus/Qiangdaqi/rtl D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 15:27:44 on May 11,2018
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/zzlqutus/Qiangdaqi/rtl" D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v 
# -- Compiling module Ctrl
# 
# Top level modules:
# 	Ctrl
# End time: 15:27:45 on May 11,2018, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
restart
# Loading work.Ctrl
run -all
# ** Note: $stop    : D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v(44)
#    Time: 46261 ns  Iteration: 0  Instance: /ctrl_tb
# Break in Module ctrl_tb at D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v line 44
vlog -vlog01compat -work work +incdir+D:/zzlqutus/Qiangdaqi/rtl D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 15:28:34 on May 11,2018
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/zzlqutus/Qiangdaqi/rtl" D:/zzlqutus/Qiangdaqi/rtl/Ctrl.v 
# -- Compiling module Ctrl
# 
# Top level modules:
# 	Ctrl
# End time: 15:28:34 on May 11,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.Ctrl
run -all
# ** Note: $stop    : D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v(44)
#    Time: 46261 ns  Iteration: 0  Instance: /ctrl_tb
# Break in Module ctrl_tb at D:/zzlqutus/Qiangdaqi/tb/ctrl_tb.v line 44
# End time: 19:11:37 on May 11,2018, Elapsed time: 4:10:50
# Errors: 8, Warnings: 0
