# Reading A:/app/modelsim/modelsim-win64-10.7-se/tcl/vsim/pref.tcl
# //  ModelSim SE-64 10.7 Dec  7 2017
# //
# //  Copyright 1991-2017 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  ModelSim SE-64 and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# OpenFile A:/XiST/XiST_project/fifo_test/sim/fifo_test.mpf
# Loading project fifo_test
vsim -L XiST -Lf XiST work.fifo_test -voptargs=+acc
# vsim -L XiST -Lf XiST work.fifo_test -voptargs="+acc" 
# Start time: 10:11:26 on Apr 22,2022
# ** Note: (vsim-8009) Loading existing optimized design _opt
# Loading work.fifo_test(fast)
# Loading XiST.xsGSR(fast)
# Loading XiST.xsPWR(fast)
# Loading work.FIFO(fast)
# Loading XiST.xsFIFO8KB(fast)
add wave -position insertpoint sim:/fifo_test/*
add wave -position insertpoint sim:/fifo_test/FIFO/*
restart
# ** Note: (vsim-8009) Loading existing optimized design _opt
# Loading work.fifo_test(fast)
# Loading XiST.xsGSR(fast)
# Loading XiST.xsPWR(fast)
# Loading work.FIFO(fast)
# Loading XiST.xsFIFO8KB(fast)
run -all
# ** Note: $stop    : A:/XiST/XiST_project/fifo_test/rtl/fifo_test.v(70)
#    Time: 30881 ns  Iteration: 0  Instance: /fifo_test
# Break in Module fifo_test at A:/XiST/XiST_project/fifo_test/rtl/fifo_test.v line 70
# End time: 14:05:38 on Apr 22,2022, Elapsed time: 3:54:12
# Errors: 0, Warnings: 0
