`timescale 1ns/1ns

module camera_param_get_tb;

	reg Clk;
	reg Rst_n;
	reg Pclk;
	reg Vsync;
	reg Href;
   reg [7:0]Data;
	 
	wire [7:0] Fps;
	wire [31:0]Fpclk;
	
	camera_param_get camera_param_get(
		Clk,
		Rst_n,
		Pclk,
		Vsync,
		
		Fps,
		Fpclk
	);

	initial Clk = 1;
   always#100 Clk = ~Clk;
	
	initial Pclk = 1;
   always#4 Pclk = ~Pclk;
    
    /*定义时序生成器输出图像的宽和高*/
    parameter WIDTH = 1200;
    parameter HIGHT = 720;
    
    integer i,j;
    
    initial begin
        Rst_n = 0;
        Vsync = 0;
        Href = 0;
        Data = 0;
        #805;
        Rst_n = 1;
        #400;
        repeat(15)begin
            Vsync = 1;
            #320;
            Vsync = 0;
            #800;
            for(i=0;i<HIGHT;i=i+1)begin
                for(j=0;j<WIDTH*2;j=j+1)begin
                    Href = 1;
                    Data = Data  + 1;
                    #80;
                end
                Href = 0;
                #800;
            end
        end
        $stop;  
    end


endmodule