Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2405991
date_generatedFri Jun 16 18:14:08 2023 os_platformWIN64
product_versionVivado v2018.3 (64-bit) project_idb6b0af7d21e24de9829a4177dbfcba9e
project_iteration9 random_id06deee3c3e5a52569307539f8d4e313c
registration_id06deee3c3e5a52569307539f8d4e313c route_designTRUE
target_devicexc7a35t target_familyartix7
target_packagefgg484 target_speed-2
tool_flowVivado

user_environment
cpu_name11th Gen Intel(R) Core(TM) i7-11700 @ 2.50GHz cpu_speed2496 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram16.000 GB total_processors1

vivado_usage
gui_handlers
abstractcombinedpanel_remove_selected_elements=1 addsrcwizard_specify_simulation_specific_hdl_files=1 basedialog_cancel=1 basedialog_ok=26
basedialog_yes=1 basereporttab_rerun=1 cmdmsgdialog_ok=3 constraintschooserpanel_add_files=1
constraintschooserpanel_create_file=1 constraintschooserpanel_file_table=1 coretreetablepanel_core_tree_table=6 createconstraintsfilepanel_file_name=1
createsrcfiledialog_file_name=1 filesetpanel_file_set_panel_tree=41 flownavigatortreepanel_flow_navigator_tree=22 fpgachooser_family=1
fpgachooser_fpga_table=1 fpgachooser_package=1 fpgachooser_speed=1 gettingstartedview_create_new_project=1
hardwaretreepanel_hardware_tree_table=16 hjfilechooserhelpers_jump_to_recent_project_directory=3 ipstatussectionpanel_upgrade_selected=1 mainwintoolbarmgr_select_or_save_window_layout=1
msgview_clear_messages_resulting_from_user_executed=4 msgview_critical_warnings=2 pacommandnames_add_sources=4 pacommandnames_auto_connect_target=7
pacommandnames_auto_update_hier=4 pacommandnames_program_fpga=8 pacommandnames_run_bitgen=12 pacommandnames_save_design=2
pacommandnames_schematic=2 pacommandnames_set_as_top=1 pacommandnames_simulation_relaunch=12 pacommandnames_simulation_run_behavioral=2
paviews_code=6 paviews_device=1 programdebugtab_open_target=1 programfpgadialog_program=8
programfpgadialog_specify_bitstream_file=1 projectnamechooser_choose_project_location=1 projectnamechooser_create_project_subdirectory=1 projectnamechooser_project_name=1
projecttab_reload=3 rdicommands_settings=1 rdiviews_waveform_viewer=217 reportipstatusinfodialog_report_ip_status=1
settingsdialog_project_tree=1 signalsview_expand_all=2 signalsview_group_by_interface_and_bus=3 signaltablepanel_signal_table=7
signaltreepanel_signal_tree_table=16 simpleoutputproductdialog_generate_output_products_immediately=4 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=5 srcchooserpanel_create_file=1
srcchoosertable_src_chooser_table=1 srcmenu_ip_hierarchy=4 stalerundialog_open_design=1 syntheticastatemonitor_cancel=1
taskbanner_close=11 timingconstraintswizard_goto_constraints_summary_page=1 waveformnametree_waveform_name_tree=10 waveformview_add_marker=2
java_command_handlers
addsources=4 autoconnecttarget=7 coreview=1 customizecore=2
launchprogramfpga=8 newproject=1 openhardwaremanager=7 openrecenttarget=6
recustomizecore=2 reportipstatus=1 runbitgen=13 runschematic=2
runsynthesis=1 savedesign=2 settopnode=1 showview=2
simulationbreak=14 simulationrelaunch=12 simulationrestart=14 simulationrun=2
simulationrunall=14 timingconstraintswizard=2 toolssettings=1 upgradeip=1
viewlayoutcmd=1 viewtasksynthesis=1
other_data
guimode=3
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=4 export_simulation_ies=4
export_simulation_modelsim=4 export_simulation_questa=4 export_simulation_riviera=4 export_simulation_vcs=4
export_simulation_xsim=4 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=26 simulator_language=Mixed srcsetcount=3 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=3 totalsynthesisruns=3

unisim_transformation
post_unisim_transformation
bufg=3 fdce=24 fdpe=1 gnd=2
ibuf=2 lut1=2 lut2=7 lut3=5
lut4=6 lut5=9 lut6=26 mmcme2_adv=1
obufds=5 oserdese2=5 vcc=3
pre_unisim_transformation
bufg=3 fdce=24 fdpe=1 gnd=2
ibuf=2 lut1=2 lut2=7 lut3=5
lut4=6 lut5=9 lut6=26 mmcme2_adv=1
obufds=5 oserdese2=5 vcc=3

ip_statistics
clk_wiz_v6_0_2_0_0/1
clkin1_period=20.000 clkin2_period=10.0 clock_mgr_type=NA component_name=clk_wiz_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=2 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") clocks=0.002998 confidence_level_clock_activity=High
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Medium
confidence_level_overall=Medium customer=TBD customer_class=TBD devstatic=0.071248
die=xc7a35tfgg484-2 dsp_output_toggle=12.500000 dynamic=0.316686 effective_thetaja=2.8
enable_probability=0.990000 family=artix7 ff_toggle=12.500000 flow_state=routed
heatsink=medium (Medium Profile) i/o=0.186923 input_toggle=12.500000 junction_temp=26.1 (C)
logic=0.000053 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 mmcm=0.126675 netlist_net_matched=NA off-chip_power=0.000000
on-chip_power=0.387934 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000
package=fgg484 pct_clock_constrained=0.000000 pct_inputs_defined=50 platform=nt64
process=typical ram_enable=50.000000 ram_write=50.000000 read_saif=False
set/reset_probability=0.000000 signal_rate=False signals=0.000037 simulation_file=None
speedgrade=-2 static_prob=False temp_grade=commercial thetajb=9.1 (C/W)
thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=2.8
user_junc_temp=26.1 (C) user_thetajb=9.1 (C/W) user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.069919
vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000
vccaux_static_current=0.012637 vccaux_total_current=0.082556 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000
vccbram_static_current=0.000166 vccbram_total_current=0.000166 vccbram_voltage=1.000000 vccint_dynamic_current=0.005642
vccint_static_current=0.009836 vccint_total_current=0.015477 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.074076
vcco25_static_current=0.001000 vcco25_total_current=0.075076 vcco25_voltage=2.500000 vcco33_dynamic_current=0.000000
vcco33_static_current=0.000000 vcco33_total_current=0.000000 vcco33_voltage=3.300000 version=2018.3

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=3 bufgctrl_util_percentage=9.38
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=20.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=1 lvcmos33=1 lvds_25=1
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=3 fdce_functional_category=Flop & Latch fdce_used=24
fdpe_functional_category=Flop & Latch fdpe_used=1 ibuf_functional_category=IO ibuf_used=2
lut1_functional_category=LUT lut1_used=1 lut2_functional_category=LUT lut2_used=7
lut3_functional_category=LUT lut3_used=5 lut4_functional_category=LUT lut4_used=6
lut5_functional_category=LUT lut5_used=9 lut6_functional_category=LUT lut6_used=26
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 obufds_functional_category=IO obufds_used=5
oserdese2_functional_category=IO oserdese2_used=5
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=42 lut_as_logic_util_percentage=0.20
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=25 register_as_flip_flop_util_percentage=0.06
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=42 slice_luts_util_percentage=0.20
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=25 slice_registers_util_percentage=0.06
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=42 lut_as_logic_util_percentage=0.20 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=0 lut_in_front_of_the_register_is_used_fixed=0 lut_in_front_of_the_register_is_used_used=1
register_driven_from_outside_the_slice_fixed=1 register_driven_from_outside_the_slice_used=1 register_driven_from_within_the_slice_fixed=1 register_driven_from_within_the_slice_used=24
slice_available=8150 slice_fixed=0 slice_registers_available=41600 slice_registers_fixed=0
slice_registers_used=25 slice_registers_util_percentage=0.06 slice_used=13 slice_util_percentage=0.16
slicel_fixed=0 slicel_used=9 slicem_fixed=0 slicem_used=4
unique_control_sets_available=8150 unique_control_sets_fixed=8150 unique_control_sets_used=2 unique_control_sets_util_percentage=0.02
using_o5_and_o6_fixed=0.02 using_o5_and_o6_used=12 using_o5_output_only_fixed=12 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=30
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35tfgg484-2
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=xlvds_lcd -verilog_define=default::[not_specified]
usage
elapsed=00:00:14s hls_ip=0 memory_gain=506.012MB memory_peak=797.523MB

xsim
command_line_options
-sim_mode=behavioral -sim_type=default::