2018.2:
 * Version 5.1 (Rev. 12)
 * General: Properly tied off the undriven input ports

2018.1:
 * Version 5.1 (Rev. 11)
 * Bug Fix: Added an input buffer for tristate_output input port

2017.4:
 * Version 5.1 (Rev. 10)
 * General: ASPARTAN7 device support added

2017.3:
 * Version 5.1 (Rev. 9)
 * No changes

2017.2:
 * Version 5.1 (Rev. 9)
 * No changes

2017.1:
 * Version 5.1 (Rev. 9)
 * Bug Fix: Fixed the generation of ref_clk and delay_locked ports in IPI when IDELAYCTRL is deselected

2016.4:
 * Version 5.1 (Rev. 8)
 * No changes

2016.3:
 * Version 5.1 (Rev. 8)
 * Feature Enhancement: Added option in GUI to set the high performance mode for IODELAY
 * Other: Spartan7 device support added

2016.2:
 * Version 5.1 (Rev. 7)
 * No changes

2016.1:
 * Version 5.1 (Rev. 7)
 * Added option in GUI (Forward divide clock) to forward divided clock or serial clock

2015.4.2:
 * Version 5.1 (Rev. 6)
 * No changes

2015.4.1:
 * Version 5.1 (Rev. 6)
 * No changes

2015.4:
 * Version 5.1 (Rev. 6)
 * No changes

2015.3:
 * Version 5.1 (Rev. 6)
 * Added option for IODELAYCTRL and BUFG
 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

2015.2.1:
 * Version 5.1 (Rev. 5)
 * No changes

2015.2:
 * Version 5.1 (Rev. 5)
 * No changes

2015.1:
 * Version 5.1 (Rev. 5)
 * Updated the example design XDC to resolve the DRC warnings, no functional changes

2014.4.1:
 * Version 5.1 (Rev. 4)
 * No changes

2014.4:
 * Version 5.1 (Rev. 4)
 * Internal device family change, no functional changes

2014.3:
 * Version 5.1 (Rev. 3)
 * Updated example design to make use of only one external clock for bidirectional data configuration

2014.2:
 * Version 5.1 (Rev. 2)
 * Repackaged to improve internal automation, no functional changes
 * Updated example design for MMCME2 COMPENSATION = BUF_IN

2014.1:
 * Version 5.1 (Rev. 1)
 * Repackaged to improve internal automation, no functional changes
 * Updated Clock Signaling enablement in GUI for non Custom Interface Templates

2013.4:
 * Version 5.1
 * No changes

2013.3:
 * Version 5.1
 * Added ability to use Clock Enable port of ISERDES or OSERDES
 * Added GUI option to configure clock type and IO standard for forwarded clock port
 * Added tool tips to GUI
 * Added support for Cadence IES and Synopsys VCS simulators
 * Reduced warnings in synthesis and simulation
 * Added support for IP Integrator

2013.2:
 * Version 5.0 (Rev. 1)
 * Repackaged to enable internal version management, no functional changes
 * Updated Life-Cycle status of devices

2013.1:
 * Version 5.0
 * Lower case ports for Verilog
 * Added device specific IOSTANDARD support

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