# Reading D:/altera/13.0/modelsim_ae/tcl/vsim/pref.tcl 
# ERROR: No extended dataflow license exists
# do tlv5618_run_msim_rtl_verilog.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying D:\altera\13.0\modelsim_ae\win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied D:\altera\13.0\modelsim_ae\win32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
# 
# vlog -vlog01compat -work work +incdir+D:/fpga/ac620/demo_release/book_prj/chapter5/class24_DACtlv5618/prj/ip {D:/fpga/ac620/demo_release/book_prj/chapter5/class24_DACtlv5618/prj/ip/ISSP.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module ISSP
# 
# Top level modules:
# 	ISSP
# vlog -vlog01compat -work work +incdir+D:/fpga/ac620/demo_release/book_prj/chapter5/class24_DACtlv5618/rtl {D:/fpga/ac620/demo_release/book_prj/chapter5/class24_DACtlv5618/rtl/tlv5618.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module tlv5618
# 
# Top level modules:
# 	tlv5618
# vlog -vlog01compat -work work +incdir+D:/fpga/ac620/demo_release/book_prj/chapter5/class24_DACtlv5618/rtl {D:/fpga/ac620/demo_release/book_prj/chapter5/class24_DACtlv5618/rtl/DAC_test.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module DAC_test
# 
# Top level modules:
# 	DAC_test
# 
# vlog -vlog01compat -work work +incdir+D:/fpga/ac620/demo_release/book_prj/chapter5/class24_DACtlv5618/prj/../testbench {D:/fpga/ac620/demo_release/book_prj/chapter5/class24_DACtlv5618/prj/../testbench/tlv5618_tb.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module tlv5618_tb
# 
# Top level modules:
# 	tlv5618_tb
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  tlv5618_tb
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps tlv5618_tb 
# //  ModelSim ALTERA 10.1d Nov  2 2012 
# //
# //  Copyright 1991-2012 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading work.tlv5618_tb
# Loading work.tlv5618
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
# Break in Module tlv5618_tb at D:/fpga/ac620/demo_release/book_prj/chapter5/class24_DACtlv5618/prj/../testbench/tlv5618_tb.v line 72
# Simulation Breakpoint: Break in Module tlv5618_tb at D:/fpga/ac620/demo_release/book_prj/chapter5/class24_DACtlv5618/prj/../testbench/tlv5618_tb.v line 72
# MACRO ./tlv5618_run_msim_rtl_verilog.do PAUSED at line 19
