2018.3:
 * Version 12.0 (Rev. 12)
 * No changes

2018.2:
 * Version 12.0 (Rev. 12)
 * No changes

2018.1:
 * Version 12.0 (Rev. 12)
 * Revision change in one or more subcores

2017.4:
 * Version 12.0 (Rev. 11)
 * No changes

2017.3:
 * Version 12.0 (Rev. 11)
 * Revision change in one or more subcores

2017.2:
 * Version 12.0 (Rev. 10)
 * No changes

2017.1:
 * Version 12.0 (Rev. 10)
 * No changes

2016.4:
 * Version 12.0 (Rev. 10)
 * No changes

2016.3:
 * Version 12.0 (Rev. 10)
 * General: Support for Spartan7 devices
 * Revision change in one or more subcores

2016.2:
 * Version 12.0 (Rev. 9)
 * No changes

2016.1:
 * Version 12.0 (Rev. 9)
 * Fixed GUI COE file handling
 * Revision change in one or more subcores

2015.4.2:
 * Version 12.0 (Rev. 8)
 * No changes

2015.4.1:
 * Version 12.0 (Rev. 8)
 * No changes

2015.4:
 * Version 12.0 (Rev. 8)
 * Revision change in one or more subcores

2015.3:
 * Version 12.0 (Rev. 7)
 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
 * Updated COE-to-MIF code to support IP Core Container flow
 * Revision change in one or more subcores

2015.2.1:
 * Version 12.0 (Rev. 6)
 * No changes

2015.2:
 * Version 12.0 (Rev. 6)
 * No changes

2015.1:
 * Version 12.0 (Rev. 6)
 * Addition of Beta support for future devices
 * Supported devices and production status are now determined automatically, to simplify support for future devices

2014.4.1:
 * Version 12.0 (Rev. 5)
 * No changes

2014.4:
 * Version 12.0 (Rev. 5)
 * Internal GUI update, no functional changes.
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf

2014.3:
 * Version 12.0 (Rev. 4)
 * No changes

2014.2:
 * Version 12.0 (Rev. 4)
 * No changes

2014.1:
 * Version 12.0 (Rev. 4)
 * Internal device family name change, no functional changes
 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done
 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)
 * Support for Virtex Ultrascale devices at Pre-Production Status

2013.4:
 * Version 12.0 (Rev. 3)
 * Missing tooltips added to GUI
 * GUI error on change of radix fixed.
 * Support for Kintex Ultrascale devices at Pre-Production Status

2013.3:
 * Version 12.0 (Rev. 2)
 * Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
 * Internal standardization in source file delivery, does not change behavior
 * Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
 * Added default constraints for out of context flow
 * Added support for IP Integrator
 * Added support for Cadence IES and Synopsys VCS simulators

2013.2:
 * Version 12.0 (Rev. 1)
 * Support for Series 7 devices at Production status
 * Updated clock and bus interface associations for IP Integrator support
 * GUI performance improvements
 * Removing support for Defense Grade Low Power Artix7

2013.1:
 * Version 12.0
 * Native Vivado Release
 * Changed all port names to upper case
 * There have been no functional changes to this IP.  The version number has changed to support unique versioning in Vivado starting with 2013.1.

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