Clock Regions-Block Scope:
+--------------------------------------------------------------------------+
| (X0,Y*): (Xmin,Xmax,Ymin,Ymax)     | (X1,Y*): (Xmin,Xmax,Ymin,Ymax)     
+--------------------------------------------------------------------------+
| (X0,Y2): (0,39,60,89)              | (X1,Y2): (40,75,60,89)             
| (X0,Y1): (0,39,30,59)              | (X1,Y1): (40,75,30,59)             
| (X0,Y0): (0,39,0,29)               | (X1,Y0): (40,75,0,29)              
+--------------------------------------------------------------------------+

Clock Regions-Clock Primitives:
+--------------------------------------------------------------------------------------------------------------------------------------+
| Clock Region Name     | CLK PAD     | PLL PAD     | RCKB     | IOCKGATE     | IOCKDIV     | CLMA     | CLMS     | DRM     | APM     
+--------------------------------------------------------------------------------------------------------------------------------------+
| (X0,Y0)               | 4           | 6           | 4        | 2            | 2           | 520      | 180      | 12      | 0       
| (X0,Y1)               | 4           | 6           | 4        | 2            | 2           | 610      | 210      | 12      | 0       
| (X0,Y2)               | 4           | 6           | 4        | 2            | 2           | 524      | 180      | 6       | 0       
| (X1,Y0)               | 4           | 6           | 4        | 2            | 2           | 450      | 150      | 6       | 10      
| (X1,Y1)               | 4           | 6           | 4        | 2            | 2           | 540      | 180      | 6       | 10      
| (X1,Y2)               | 4           | 6           | 4        | 2            | 2           | 630      | 210      | 6       | 10      
+--------------------------------------------------------------------------------------------------------------------------------------+

Global Clock Buffer Constraint Details:
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Source  Name            | Source Pin     | Source-Buffer Net     | Buffer Input Pin     | Buffer  Name             | Buffer Output Pin     | Buffer-Load Net     | Clock Region Of Buffer Site     | Buffer Site     | IO Load Clock Region     | Non-IO Load Clock Region     | Clock Loads     | Non-Clock Loads     
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| pll/u_pll_e1/goppll     | CLKOUT0        | pixelclk              | CLK                  | clkbufg_1/gopclkbufg     | CLKOUT                | ntclkbufg_1         |  ---                            |  ---            |  ---                     |  ---                         | 59              | 0                   
| pll/u_pll_e1/goppll     | CLKOUT1        | pixelclk5x            | CLK                  | clkbufg_0/gopclkbufg     | CLKOUT                | ntclkbufg_0         |  ---                            |  ---            | (72,74,8,18)             |  ---                         | 45              | 0                   
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

Global Clock Source Constraint Details:
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Source Name             | Source Pin     | Source-Load Net     | Clock Region Of Source Site     | Source Site     | Clock Buffer Loads     | Non-Clock Buffer Loads     
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| pll/u_pll_e1/goppll     | CLKOUT0        | pixelclk            | (X0,Y2)                         | PLL_82_319      | 1                      | 0                          
| pll/u_pll_e1/goppll     | CLKOUT1        | pixelclk5x          | (X0,Y2)                         | PLL_82_319      | 1                      | 0                          
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

Device Cell Placement Summary for Global Clock Buffer:
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Source  Name            | Source  Pin     | Source-Buffer Net     | Buffer Input Pin     | Buffer  Name             | Buffer Output Pin     | Buffer-Load Net     | Buffer Site     | IO Load Clock Region     | Non-IO Load Clock Region     | Clock Loads     | Non-Clock Loads     
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| pll/u_pll_e1/goppll     | CLKOUT1         | pixelclk5x            | CLK                  | clkbufg_0/gopclkbufg     | CLKOUT                | ntclkbufg_0         | USCM_74_105     | (72,74,8,18)             | (60,63,10,18)                | 45              | 0                   
| pll/u_pll_e1/goppll     | CLKOUT0         | pixelclk              | CLK                  | clkbufg_1/gopclkbufg     | CLKOUT                | ntclkbufg_1         | USCM_74_104     |  ---                     | (50,63,14,38)                | 59              | 0                   
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

Device Cell Placement Summary for Global Clock Source:
+------------------------------------------------------------------------------------------------------------------------------------------+
| Source Name             | Source  Pin     | Source-Load Net     | Source Site     | Clock Buffer Loads     | Non-Clock Buffer Loads     
+------------------------------------------------------------------------------------------------------------------------------------------+
| pll/u_pll_e1/goppll     | CLKOUT1         | pixelclk5x          | PLL_82_319      | 1                      | 0                          
| pll/u_pll_e1/goppll     | CLKOUT0         | pixelclk            | PLL_82_319      | 1                      | 0                          
+------------------------------------------------------------------------------------------------------------------------------------------+

