Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\acm9238_ddr3_rgmii.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\ad9238_12bit_to_16bit.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\cmd_rx.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\ddr3_ctrl_2port\ddr3_ctrl_2port.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\ddr3_ctrl_2port\fifo_ddr3_adapter.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\ddr3_memory_interface\ddr3_memory_interface.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\ddr_pll\ddr_pll.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\eth_cmd.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\eth_pll\eth_pll.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\eth_send_ctrl.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\eth_udp_gmii\crc32_d8.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\eth_udp_gmii\eth_udp_rx_gmii.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\eth_udp_gmii\eth_udp_tx_gmii.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\eth_udp_gmii\ip_checksum.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\fifo_rx\fifo_rx.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\fifo_tx\fifo_tx.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\gmii_rgmii_gmii\gmii_to_rgmii.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\gmii_rgmii_gmii\rgmii_to_gmii.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\gowin_ddr\gowin_ddr.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\gowin_pll\gowin_pll.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\rd_data_fifo\rd_data_fifo.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\speed_ctrl.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\state_ctrl.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\wr_data_fifo\wr_data_fifo.v H:\0_gaoyun_p\1.9.9Beta_6\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v H:\0_gaoyun_p\1.9.9Beta_6\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v H:\0_gaoyun_p\1.9.9Beta_6\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v H:\0_gaoyun_p\1.9.9Beta_6\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v H:\0_gaoyun_p\1.9.9Beta_6\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v H:\0_gaoyun_p\1.9.9Beta_6\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\gw_jtag.v H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Version | V1.9.9 Beta-6 |
| Part Number | GW5A-LV25UG324ES |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Wed Feb 28 15:34:12 2024 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | acm9238_ddr3_rgmii |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 399.113MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.245s, Peak memory usage = 399.113MB Optimizing Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.163s, Peak memory usage = 399.113MB Optimizing Phase 2: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.347s, Peak memory usage = 399.113MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.092s, Peak memory usage = 399.113MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 399.113MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 399.113MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 399.113MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.449s, Peak memory usage = 399.113MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.118s, Peak memory usage = 399.113MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 399.113MB Tech-Mapping Phase 3: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 399.113MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.358s, Peak memory usage = 399.113MB Generate output files: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.516s, Peak memory usage = 399.113MB |
| Total Time and Memory Usage | CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 399.113MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 98 |
| I/O Buf | 95 |
| IBUF | 35 |
| OBUF | 39 |
| TBUF | 2 |
| IOBUF | 16 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 4660 |
| DFFSE | 1 |
| DFFRE | 777 |
| DFFPE | 153 |
| DFFCE | 3729 |
| LUT | 4717 |
| LUT2 | 661 |
| LUT3 | 1887 |
| LUT4 | 2169 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 524 |
| ALU | 524 |
| SSRAM | 12 |
| RAM16S4 | 12 |
| INV | 55 |
| INV | 55 |
| IOLOGIC | 87 |
| IDDR | 5 |
| ODDR | 6 |
| IDES8_MEM | 16 |
| OSER8 | 24 |
| OSER8_MEM | 20 |
| IODELAY | 16 |
| BSRAM | 23 |
| SDPB | 15 |
| SDPX9B | 8 |
| CLOCK | 7 |
| CLKDIV | 1 |
| DQS | 2 |
| DDRDLL | 1 |
| DHCE | 1 |
| PLLA | 2 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 5376(4780 LUT, 524 ALU, 12 RAM16) / 23040 | 24% |
| Register | 4660 / 23685 | 20% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 4660 / 23685 | 20% |
| BSRAM | 23 / 56 | 42% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk50m | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk50m_ibuf/I | ||
| rgmii_rx_clk_i | Base | 8.000 | 125.0 | 0.000 | 4.000 | rgmii_rx_clk_i_ibuf/I | ||
| fifo_rx/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | fifo_rx/fifo_inst/n4_s2/O | ||
| fifo_rx/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | fifo_rx/fifo_inst/n9_s2/O | ||
| ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n4_s2/O | ||
| ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n9_s2/O | ||
| ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n4_s2/O | ||
| ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n9_s2/O | ||
| ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/n1784_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/n1784_s2/O | ||
| fifo_tx/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | fifo_tx/fifo_inst/n4_s2/O | ||
| fifo_tx/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | fifo_tx/fifo_inst/n9_s2/O | ||
| gw_gao_inst_0/u_icon_top/n19_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | gw_gao_inst_0/u_icon_top/n19_s2/O | ||
| Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | clk50m_ibuf/I | clk50m | Gowin_PLL/PLLA_inst/CLKOUT0 |
| Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 5.000 | 200.0 | 0.000 | 2.500 | clk50m_ibuf/I | clk50m | Gowin_PLL/PLLA_inst/CLKOUT1 |
| eth_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 8.000 | 125.0 | 0.000 | 4.000 | rgmii_rx_clk_i_ibuf/I | rgmii_rx_clk_i | eth_pll/PLLA_inst/CLKOUT0 |
| ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | Gowin_PLL/PLLA_inst/CLKOUT1 | Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | fifo_rx/fifo_inst/n4_6 | 100.0(MHz) | 1577.9(MHz) | 1 | TOP |
| 2 | fifo_rx/fifo_inst/n9_6 | 100.0(MHz) | 1577.9(MHz) | 1 | TOP |
| 3 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n4_6 | 100.0(MHz) | 1577.9(MHz) | 1 | TOP |
| 4 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n9_6 | 100.0(MHz) | 1577.9(MHz) | 1 | TOP |
| 5 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n4_6 | 100.0(MHz) | 1577.9(MHz) | 1 | TOP |
| 6 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n9_6 | 100.0(MHz) | 1577.9(MHz) | 1 | TOP |
| 7 | fifo_tx/fifo_inst/n4_6 | 100.0(MHz) | 1577.9(MHz) | 1 | TOP |
| 8 | fifo_tx/fifo_inst/n9_6 | 100.0(MHz) | 1577.9(MHz) | 1 | TOP |
| 9 | gw_gao_inst_0/u_icon_top/n19_6 | 100.0(MHz) | 1577.9(MHz) | 1 | TOP |
| 10 | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | 50.0(MHz) | 157.9(MHz) | 10 | TOP |
| 11 | Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk | 200.0(MHz) | 1489.2(MHz) | 1 | TOP |
| 12 | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk | 125.0(MHz) | 132.4(MHz) | 12 | TOP |
| 13 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 50.0(MHz) | 142.4(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 0.446 |
| Data Arrival Time | 8.509 |
| Data Required Time | 8.955 |
| From | eth_udp_rx_gmii/ip_checksum/suma_0_s0 |
| To | eth_udp_rx_gmii/ip_header_check_ok_s0 |
| Launch Clk | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.831 | 0.831 | tCL | RR | 747 | eth_pll/PLLA_inst/CLKOUT0 |
| 1.019 | 0.188 | tNET | RR | 1 | eth_udp_rx_gmii/ip_checksum/suma_0_s0/CLK |
| 1.401 | 0.382 | tC2Q | RR | 1 | eth_udp_rx_gmii/ip_checksum/suma_0_s0/Q |
| 1.589 | 0.188 | tNET | RR | 2 | eth_udp_rx_gmii/ip_checksum/sumb_0_s/I1 |
| 2.151 | 0.563 | tINS | RF | 1 | eth_udp_rx_gmii/ip_checksum/sumb_0_s/COUT |
| 2.151 | 0.000 | tNET | FF | 2 | eth_udp_rx_gmii/ip_checksum/sumb_1_s/CIN |
| 2.201 | 0.050 | tINS | FR | 1 | eth_udp_rx_gmii/ip_checksum/sumb_1_s/COUT |
| 2.201 | 0.000 | tNET | RR | 2 | eth_udp_rx_gmii/ip_checksum/sumb_2_s/CIN |
| 2.251 | 0.050 | tINS | RR | 1 | eth_udp_rx_gmii/ip_checksum/sumb_2_s/COUT |
| 2.251 | 0.000 | tNET | RR | 2 | eth_udp_rx_gmii/ip_checksum/sumb_3_s/CIN |
| 2.301 | 0.050 | tINS | RR | 1 | eth_udp_rx_gmii/ip_checksum/sumb_3_s/COUT |
| 2.301 | 0.000 | tNET | RR | 2 | eth_udp_rx_gmii/ip_checksum/sumb_4_s/CIN |
| 2.351 | 0.050 | tINS | RR | 1 | eth_udp_rx_gmii/ip_checksum/sumb_4_s/COUT |
| 2.351 | 0.000 | tNET | RR | 2 | eth_udp_rx_gmii/ip_checksum/sumb_5_s/CIN |
| 2.401 | 0.050 | tINS | RR | 1 | eth_udp_rx_gmii/ip_checksum/sumb_5_s/COUT |
| 2.401 | 0.000 | tNET | RR | 2 | eth_udp_rx_gmii/ip_checksum/sumb_6_s/CIN |
| 2.451 | 0.050 | tINS | RR | 1 | eth_udp_rx_gmii/ip_checksum/sumb_6_s/COUT |
| 2.451 | 0.000 | tNET | RR | 2 | eth_udp_rx_gmii/ip_checksum/sumb_7_s/CIN |
| 2.501 | 0.050 | tINS | RR | 1 | eth_udp_rx_gmii/ip_checksum/sumb_7_s/COUT |
| 2.501 | 0.000 | tNET | RR | 2 | eth_udp_rx_gmii/ip_checksum/sumb_8_s/CIN |
| 2.551 | 0.050 | tINS | RR | 1 | eth_udp_rx_gmii/ip_checksum/sumb_8_s/COUT |
| 2.551 | 0.000 | tNET | RR | 2 | eth_udp_rx_gmii/ip_checksum/sumb_9_s/CIN |
| 2.601 | 0.050 | tINS | RR | 1 | eth_udp_rx_gmii/ip_checksum/sumb_9_s/COUT |
| 2.601 | 0.000 | tNET | RR | 2 | eth_udp_rx_gmii/ip_checksum/sumb_10_s/CIN |
| 2.651 | 0.050 | tINS | RR | 1 | eth_udp_rx_gmii/ip_checksum/sumb_10_s/COUT |
| 2.651 | 0.000 | tNET | RR | 2 | eth_udp_rx_gmii/ip_checksum/sumb_11_s/CIN |
| 2.701 | 0.050 | tINS | RR | 1 | eth_udp_rx_gmii/ip_checksum/sumb_11_s/COUT |
| 2.701 | 0.000 | tNET | RR | 2 | eth_udp_rx_gmii/ip_checksum/sumb_12_s/CIN |
| 2.751 | 0.050 | tINS | RR | 1 | eth_udp_rx_gmii/ip_checksum/sumb_12_s/COUT |
| 2.751 | 0.000 | tNET | RR | 2 | eth_udp_rx_gmii/ip_checksum/sumb_13_s/CIN |
| 2.801 | 0.050 | tINS | RR | 1 | eth_udp_rx_gmii/ip_checksum/sumb_13_s/COUT |
| 2.801 | 0.000 | tNET | RR | 2 | eth_udp_rx_gmii/ip_checksum/sumb_14_s/CIN |
| 2.851 | 0.050 | tINS | RR | 1 | eth_udp_rx_gmii/ip_checksum/sumb_14_s/COUT |
| 2.851 | 0.000 | tNET | RR | 2 | eth_udp_rx_gmii/ip_checksum/sumb_15_s/CIN |
| 2.901 | 0.050 | tINS | RR | 3 | eth_udp_rx_gmii/ip_checksum/sumb_15_s/COUT |
| 3.089 | 0.188 | tNET | RR | 1 | eth_udp_rx_gmii/n1388_s29/I0 |
| 3.615 | 0.526 | tINS | RR | 3 | eth_udp_rx_gmii/n1388_s29/F |
| 3.803 | 0.188 | tNET | RR | 1 | eth_udp_rx_gmii/n1388_s17/I2 |
| 4.264 | 0.461 | tINS | RR | 3 | eth_udp_rx_gmii/n1388_s17/F |
| 4.451 | 0.188 | tNET | RR | 1 | eth_udp_rx_gmii/n1388_s24/I2 |
| 4.913 | 0.461 | tINS | RR | 2 | eth_udp_rx_gmii/n1388_s24/F |
| 5.100 | 0.188 | tNET | RR | 1 | eth_udp_rx_gmii/n1388_s20/I2 |
| 5.561 | 0.461 | tINS | RR | 3 | eth_udp_rx_gmii/n1388_s20/F |
| 5.749 | 0.188 | tNET | RR | 1 | eth_udp_rx_gmii/n1388_s12/I2 |
| 6.210 | 0.461 | tINS | RR | 1 | eth_udp_rx_gmii/n1388_s12/F |
| 6.398 | 0.188 | tNET | RR | 1 | eth_udp_rx_gmii/n1388_s6/I1 |
| 6.914 | 0.516 | tINS | RR | 1 | eth_udp_rx_gmii/n1388_s6/F |
| 7.101 | 0.188 | tNET | RR | 1 | eth_udp_rx_gmii/n1388_s2/I1 |
| 7.618 | 0.516 | tINS | RR | 1 | eth_udp_rx_gmii/n1388_s2/F |
| 7.805 | 0.188 | tNET | RR | 1 | eth_udp_rx_gmii/n1388_s0/I1 |
| 8.321 | 0.516 | tINS | RR | 1 | eth_udp_rx_gmii/n1388_s0/F |
| 8.509 | 0.188 | tNET | RR | 1 | eth_udp_rx_gmii/ip_header_check_ok_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 8.000 | 0.000 | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 8.832 | 0.831 | tCL | RR | 747 | eth_pll/PLLA_inst/CLKOUT0 |
| 9.019 | 0.188 | tNET | RR | 1 | eth_udp_rx_gmii/ip_header_check_ok_s0/CLK |
| 8.955 | -0.064 | tSu | 1 | eth_udp_rx_gmii/ip_header_check_ok_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 8.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.188, 100.000% |
| Arrival Data Path Delay: | cell: 5.233, 69.860%; route: 1.875, 25.033%; tC2Q: 0.382, 5.107% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.188, 100.000% |
Path 2
Path Summary:| Slack | 0.819 |
| Data Arrival Time | 8.136 |
| Data Required Time | 8.955 |
| From | eth_udp_tx_gmii/ip_checksum/suma_1_s0 |
| To | eth_udp_tx_gmii/tx_data_3_s0 |
| Launch Clk | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.831 | 0.831 | tCL | RR | 747 | eth_pll/PLLA_inst/CLKOUT0 |
| 1.019 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/ip_checksum/suma_1_s0/CLK |
| 1.401 | 0.382 | tC2Q | RR | 1 | eth_udp_tx_gmii/ip_checksum/suma_1_s0/Q |
| 1.589 | 0.188 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_1_s/I1 |
| 2.151 | 0.563 | tINS | RF | 1 | eth_udp_tx_gmii/ip_checksum/sumb_1_s/COUT |
| 2.151 | 0.000 | tNET | FF | 2 | eth_udp_tx_gmii/ip_checksum/sumb_2_s/CIN |
| 2.201 | 0.050 | tINS | FR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_2_s/COUT |
| 2.201 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_3_s/CIN |
| 2.251 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_3_s/COUT |
| 2.251 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_4_s/CIN |
| 2.301 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_4_s/COUT |
| 2.301 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_5_s/CIN |
| 2.351 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_5_s/COUT |
| 2.351 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_6_s/CIN |
| 2.401 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_6_s/COUT |
| 2.401 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_7_s/CIN |
| 2.451 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_7_s/COUT |
| 2.451 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_8_s/CIN |
| 2.501 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_8_s/COUT |
| 2.501 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_9_s/CIN |
| 2.551 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_9_s/COUT |
| 2.551 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_10_s/CIN |
| 2.601 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_10_s/COUT |
| 2.601 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_11_s/CIN |
| 2.651 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_11_s/COUT |
| 2.651 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_12_s/CIN |
| 2.701 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_12_s/COUT |
| 2.701 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_13_s/CIN |
| 2.751 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_13_s/COUT |
| 2.751 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_14_s/CIN |
| 2.801 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_14_s/COUT |
| 2.801 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_15_s/CIN |
| 2.851 | 0.050 | tINS | RR | 4 | eth_udp_tx_gmii/ip_checksum/sumb_15_s/COUT |
| 3.039 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n936_s18/I0 |
| 3.565 | 0.526 | tINS | RR | 4 | eth_udp_tx_gmii/n936_s18/F |
| 3.753 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n932_s25/I3 |
| 4.015 | 0.262 | tINS | RR | 4 | eth_udp_tx_gmii/n932_s25/F |
| 4.203 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n944_s15/I3 |
| 4.465 | 0.262 | tINS | RR | 3 | eth_udp_tx_gmii/n944_s15/F |
| 4.653 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n940_s16/I2 |
| 5.114 | 0.461 | tINS | RR | 1 | eth_udp_tx_gmii/n940_s16/F |
| 5.301 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n940_s13/I0 |
| 5.828 | 0.526 | tINS | RR | 1 | eth_udp_tx_gmii/n940_s13/F |
| 6.015 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n940_s10/I0 |
| 6.541 | 0.526 | tINS | RR | 1 | eth_udp_tx_gmii/n940_s10/F |
| 6.729 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n940_s7/I1 |
| 7.245 | 0.516 | tINS | RR | 1 | eth_udp_tx_gmii/n940_s7/F |
| 7.433 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n940_s6/I1 |
| 7.949 | 0.516 | tINS | RR | 1 | eth_udp_tx_gmii/n940_s6/F |
| 8.136 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/tx_data_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 8.000 | 0.000 | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 8.832 | 0.831 | tCL | RR | 747 | eth_pll/PLLA_inst/CLKOUT0 |
| 9.019 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/tx_data_3_s0/CLK |
| 8.955 | -0.064 | tSu | 1 | eth_udp_tx_gmii/tx_data_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 8.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.188, 100.000% |
| Arrival Data Path Delay: | cell: 4.860, 68.282%; route: 1.875, 26.344%; tC2Q: 0.382, 5.374% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.188, 100.000% |
Path 3
Path Summary:| Slack | 0.829 |
| Data Arrival Time | 8.126 |
| Data Required Time | 8.955 |
| From | eth_udp_tx_gmii/ip_checksum/suma_1_s0 |
| To | eth_udp_tx_gmii/tx_data_4_s0 |
| Launch Clk | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.831 | 0.831 | tCL | RR | 747 | eth_pll/PLLA_inst/CLKOUT0 |
| 1.019 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/ip_checksum/suma_1_s0/CLK |
| 1.401 | 0.382 | tC2Q | RR | 1 | eth_udp_tx_gmii/ip_checksum/suma_1_s0/Q |
| 1.589 | 0.188 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_1_s/I1 |
| 2.151 | 0.563 | tINS | RF | 1 | eth_udp_tx_gmii/ip_checksum/sumb_1_s/COUT |
| 2.151 | 0.000 | tNET | FF | 2 | eth_udp_tx_gmii/ip_checksum/sumb_2_s/CIN |
| 2.201 | 0.050 | tINS | FR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_2_s/COUT |
| 2.201 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_3_s/CIN |
| 2.251 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_3_s/COUT |
| 2.251 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_4_s/CIN |
| 2.301 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_4_s/COUT |
| 2.301 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_5_s/CIN |
| 2.351 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_5_s/COUT |
| 2.351 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_6_s/CIN |
| 2.401 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_6_s/COUT |
| 2.401 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_7_s/CIN |
| 2.451 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_7_s/COUT |
| 2.451 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_8_s/CIN |
| 2.501 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_8_s/COUT |
| 2.501 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_9_s/CIN |
| 2.551 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_9_s/COUT |
| 2.551 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_10_s/CIN |
| 2.601 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_10_s/COUT |
| 2.601 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_11_s/CIN |
| 2.651 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_11_s/COUT |
| 2.651 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_12_s/CIN |
| 2.701 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_12_s/COUT |
| 2.701 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_13_s/CIN |
| 2.751 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_13_s/COUT |
| 2.751 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_14_s/CIN |
| 2.801 | 0.050 | tINS | RR | 1 | eth_udp_tx_gmii/ip_checksum/sumb_14_s/COUT |
| 2.801 | 0.000 | tNET | RR | 2 | eth_udp_tx_gmii/ip_checksum/sumb_15_s/CIN |
| 2.851 | 0.050 | tINS | RR | 4 | eth_udp_tx_gmii/ip_checksum/sumb_15_s/COUT |
| 3.039 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n936_s18/I0 |
| 3.565 | 0.526 | tINS | RR | 4 | eth_udp_tx_gmii/n936_s18/F |
| 3.753 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n932_s25/I3 |
| 4.015 | 0.262 | tINS | RR | 4 | eth_udp_tx_gmii/n932_s25/F |
| 4.203 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n932_s18/I1 |
| 4.719 | 0.516 | tINS | RR | 2 | eth_udp_tx_gmii/n932_s18/F |
| 4.906 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n942_s15/I3 |
| 5.169 | 0.262 | tINS | RR | 3 | eth_udp_tx_gmii/n942_s15/F |
| 5.356 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n938_s17/I2 |
| 5.818 | 0.461 | tINS | RR | 1 | eth_udp_tx_gmii/n938_s17/F |
| 6.005 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n938_s12/I1 |
| 6.521 | 0.516 | tINS | RR | 1 | eth_udp_tx_gmii/n938_s12/F |
| 6.709 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n938_s8/I1 |
| 7.225 | 0.516 | tINS | RR | 1 | eth_udp_tx_gmii/n938_s8/F |
| 7.413 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/n938_s7/I0 |
| 7.939 | 0.526 | tINS | RR | 1 | eth_udp_tx_gmii/n938_s7/F |
| 8.126 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/tx_data_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 8.000 | 0.000 | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 8.832 | 0.831 | tCL | RR | 747 | eth_pll/PLLA_inst/CLKOUT0 |
| 9.019 | 0.188 | tNET | RR | 1 | eth_udp_tx_gmii/tx_data_4_s0/CLK |
| 8.955 | -0.064 | tSu | 1 | eth_udp_tx_gmii/tx_data_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 8.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.188, 100.000% |
| Arrival Data Path Delay: | cell: 4.850, 68.237%; route: 1.875, 26.381%; tC2Q: 0.382, 5.382% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.188, 100.000% |
Path 4
Path Summary:| Slack | 0.863 |
| Data Arrival Time | 19.384 |
| Data Required Time | 20.248 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0 |
| Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk[R] |
| Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 15.000 | 0.000 | Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk | |||
| 15.832 | 0.831 | tCL | RR | 1 | Gowin_PLL/PLLA_inst/CLKOUT1 |
| 16.019 | 0.188 | tNET | RR | 3 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 16.201 | 0.182 | tINS | RR | 64 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT |
| 16.389 | 0.188 | tNET | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN |
| 16.795 | 0.406 | tINS | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0] |
| 16.982 | 0.188 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/I1 |
| 17.545 | 0.563 | tINS | RF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/COUT |
| 17.545 | 0.000 | tNET | FF | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/CIN |
| 17.594 | 0.050 | tINS | FR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/COUT |
| 17.594 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/CIN |
| 17.645 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT |
| 17.645 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN |
| 17.694 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT |
| 17.694 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN |
| 17.744 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT |
| 17.744 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN |
| 17.795 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT |
| 17.795 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN |
| 17.844 | 0.050 | tINS | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT |
| 18.032 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1 |
| 18.548 | 0.516 | tINS | RR | 9 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F |
| 18.736 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/I2 |
| 19.197 | 0.461 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/F |
| 19.384 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 20.159 | 0.159 | tCL | RR | 3292 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 20.346 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/CLK |
| 20.311 | -0.035 | tUnc | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0 | ||
| 20.248 | -0.064 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0 |
| Clock Skew: | -0.855 |
| Setup Relationship: | 5.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.182, 49.256%; route: 0.188, 50.744% |
| Arrival Data Path Delay: | cell: 2.246, 70.551%; route: 0.750, 23.559%; tC2Q: 0.188, 5.890% |
| Required Clock Path Delay: | cell: 0.182, 49.256%; route: 0.188, 50.744% |
Path 5
Path Summary:| Slack | 0.863 |
| Data Arrival Time | 19.384 |
| Data Required Time | 20.248 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0 |
| Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk[R] |
| Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 15.000 | 0.000 | Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk | |||
| 15.832 | 0.831 | tCL | RR | 1 | Gowin_PLL/PLLA_inst/CLKOUT1 |
| 16.019 | 0.188 | tNET | RR | 3 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 16.201 | 0.182 | tINS | RR | 64 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT |
| 16.389 | 0.188 | tNET | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN |
| 16.795 | 0.406 | tINS | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0] |
| 16.982 | 0.188 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/I1 |
| 17.545 | 0.563 | tINS | RF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/COUT |
| 17.545 | 0.000 | tNET | FF | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/CIN |
| 17.594 | 0.050 | tINS | FR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/COUT |
| 17.594 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/CIN |
| 17.645 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT |
| 17.645 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN |
| 17.694 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT |
| 17.694 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN |
| 17.744 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT |
| 17.744 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN |
| 17.795 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT |
| 17.795 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN |
| 17.844 | 0.050 | tINS | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT |
| 18.032 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1 |
| 18.548 | 0.516 | tINS | RR | 9 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F |
| 18.736 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/I2 |
| 19.197 | 0.461 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/F |
| 19.384 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 20.159 | 0.159 | tCL | RR | 3292 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 20.346 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/CLK |
| 20.311 | -0.035 | tUnc | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0 | ||
| 20.248 | -0.064 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0 |
| Clock Skew: | -0.855 |
| Setup Relationship: | 5.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.182, 49.256%; route: 0.188, 50.744% |
| Arrival Data Path Delay: | cell: 2.246, 70.551%; route: 0.750, 23.559%; tC2Q: 0.188, 5.890% |
| Required Clock Path Delay: | cell: 0.182, 49.256%; route: 0.188, 50.744% |