Timing Messages

Report Title	Timing Analysis Report
Design File	H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\impl\gwsynthesis\acm9238_ddr3_rgmii.vg
Physical Constraints File	H:\01_gaoyun\01_gao_project\64_acm9238_ddr3_rgmii\src\acm9238_ddr3_rgmii.cst
Timing Constraint File	---
Version	V1.9.9 Beta-6
Part Number	GW5A-LV25UG324ES
Device	GW5A-25
Device Version	A
Created Time	Wed Feb 28 15:34:38 2024
Legal Announcement	Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.85V -40C ES
Hold Delay Model	Fast 0.95V 100C ES
Numbers of Paths Analyzed	22704
Numbers of Endpoints Analyzed	16200
Numbers of Falling Endpoints	70
Numbers of Setup Violated Endpoints	14
Numbers of Hold Violated Endpoints	4

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk50m	Base	20.000	50.000	0.000	10.000			clk50m_ibuf/I
rgmii_rx_clk_i	Base	8.000	125.000	0.000	4.000			rgmii_rx_clk_i_ibuf/I
tck_pad_i	Base	50.000	20.000	0.000	25.000			gw_gao_inst_0/tck_ibuf/I
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk	Generated	20.000	50.000	0.000	10.000	clk50m_ibuf/I	clk50m	Gowin_PLL/PLLA_inst/CLKOUT0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	Generated	5.000	200.000	0.000	2.500	clk50m_ibuf/I	clk50m	Gowin_PLL/PLLA_inst/CLKOUT1
eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	Generated	8.000	125.000	0.000	4.000	rgmii_rx_clk_i_ibuf/I	rgmii_rx_clk_i	eth_pll/PLLA_inst/CLKOUT0
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	Generated	20.000	50.000	0.000	10.000	Gowin_PLL/PLLA_inst/CLKOUT1	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	tck_pad_i	20.000(MHz)	125.539(MHz)	7	TOP
2	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk	50.000(MHz)	84.383(MHz)	9	TOP
3	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	200.000(MHz)	2016.128(MHz)	1	TOP
4	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	125.000(MHz)	124.800(MHz)	8	TOP
5	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	50.000(MHz)	80.748(MHz)	10	TOP

No timing paths to get frequency of clk50m!

No timing paths to get frequency of rgmii_rx_clk_i!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk50m	Setup	0.000	0
clk50m	Hold	0.000	0
rgmii_rx_clk_i	Setup	0.000	0
rgmii_rx_clk_i	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk	Setup	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk	Hold	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	Setup	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	Hold	0.000	0
eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	Setup	-0.026	2
eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	Hold	0.000	0
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	Setup	0.000	0
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-1.745	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.677	7.323
2	-1.645	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.677	7.223
3	-1.580	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.677	7.158
4	-1.498	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.677	7.075
5	-1.498	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.677	7.075
6	-1.463	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/stop_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CEN	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	0.913	2.834
7	-1.219	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.674	6.794
8	-1.191	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.705	6.797
9	-1.146	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.695	6.743
10	-1.093	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.705	6.705
11	-0.571	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.243	2.795
12	-0.401	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.690	5.993
13	-0.013	Number_d1_16_s0/Q	eth_send_ctrl/pkt_length_1_s1/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	-0.002	7.951
14	-0.013	Number_d1_16_s0/Q	eth_send_ctrl/pkt_length_5_s1/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	-0.002	7.951
15	0.071	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.241	2.151
16	0.169	eth_udp_tx_gmii/ip_checksum/suma_2_s0/Q	eth_udp_tx_gmii/tx_data_7_s0/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	-0.036	7.802
17	0.170	Number_d1_16_s0/Q	eth_send_ctrl/pkt_length_2_s1/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	0.007	7.759
18	0.175	eth_udp_tx_gmii/ip_checksum/suma_2_s0/Q	eth_udp_tx_gmii/tx_data_6_s0/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	-0.026	7.787
19	0.255	Number_d1_16_s0/Q	eth_send_ctrl/pkt_length_1_s1/CE	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	-0.002	7.436
20	0.255	Number_d1_16_s0/Q	eth_send_ctrl/pkt_length_5_s1/CE	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	-0.002	7.436
21	0.274	Number_d1_16_s0/Q	eth_send_ctrl/state_0_s0/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	0.048	7.615
22	0.296	eth_udp_rx_gmii/ip_checksum/suma_4_s0/Q	eth_udp_rx_gmii/ip_header_check_ok_s0/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	-0.009	7.650
23	0.300	Number_d1_16_s0/Q	eth_send_ctrl/pkt_length_2_s1/CE	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	0.007	7.381
24	0.318	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_5_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.681	5.264
25	0.476	eth_udp_tx_gmii/curr_state.TX_DATA_s1/Q	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CEB	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	-0.013	7.450

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-0.540	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/Q	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	tck_pad_i:[R]	0.000	-1.553	1.025
2	0.049	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_11_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[11]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.001	0.296
3	0.073	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[2]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.016	0.306
4	0.077	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_29_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[29]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.023	0.304
5	0.077	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_28_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[28]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.023	0.304
6	0.077	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_26_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[26]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.023	0.304
7	0.077	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_24_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[24]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.023	0.304
8	0.078	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_18_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[18]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.021	0.306
9	0.078	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_4_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[4]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.021	0.306
10	0.106	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_17_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[17]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.001	0.354
11	0.106	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_15_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.001	0.354
12	0.161	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_30_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[30]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.013	0.397
13	0.162	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_36_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.011	0.400
14	0.171	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_27_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[27]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.023	0.397
15	0.171	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_25_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[25]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.023	0.397
16	0.180	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_59_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[23]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.012	0.416
17	0.180	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_55_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[19]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.012	0.416
18	0.184	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[20]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.016	0.416
19	0.184	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[19]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.016	0.416
20	0.184	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[17]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.016	0.416
21	0.184	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.016	0.416
22	0.186	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_1_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[1]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.019	0.416
23	0.188	ad9238_12bit_to_16bit/ad_out_11_s1/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s/DI[3]	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	0.000	0.019	0.419
24	0.190	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_23_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[23]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.023	0.416
25	0.191	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_22_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.016	0.424

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.022	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.214	2.169
2	0.022	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.214	2.169
3	0.358	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.214	2.169
4	0.358	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.214	2.169
5	0.358	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.214	2.169
6	0.358	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.214	2.169
7	0.298	fifo_tx/fifo_inst/reset_r_1_s0/Q	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/RESET	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	4.000	-0.026	3.290
8	0.358	fifo_tx/fifo_inst/reset_r_1_s0/Q	fifo_tx/fifo_inst/Small.rq1_wptr_0_s5/CLEAR	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	4.000	0.004	3.290
9	0.358	fifo_tx/fifo_inst/reset_r_1_s0/Q	fifo_tx/fifo_inst/rbin_num_2_s0/CLEAR	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	4.000	0.016	3.278
10	0.358	fifo_tx/fifo_inst/reset_r_1_s0/Q	fifo_tx/fifo_inst/rbin_num_6_s0/CLEAR	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	4.000	0.010	3.284
11	0.358	fifo_tx/fifo_inst/reset_r_1_s0/Q	fifo_tx/fifo_inst/rbin_num_7_s0/CLEAR	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	4.000	0.010	3.284
12	0.358	fifo_tx/fifo_inst/reset_r_1_s0/Q	fifo_tx/fifo_inst/rbin_num_9_s0/CLEAR	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	4.000	0.010	3.284
13	0.358	fifo_tx/fifo_inst/reset_r_1_s0/Q	fifo_tx/fifo_inst/rbin_num_10_s0/CLEAR	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	4.000	0.010	3.284
14	0.358	fifo_tx/fifo_inst/reset_r_1_s0/Q	fifo_tx/fifo_inst/rbin_num_11_s0/CLEAR	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	4.000	0.004	3.290
15	2.518	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.211	2.169
16	2.518	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.211	2.169
17	2.854	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.211	2.169
18	2.854	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.211	2.169
19	2.854	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.211	2.169
20	2.854	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.211	2.169
21	17.300	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	-0.002	2.169
22	17.300	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	-0.002	2.169
23	17.645	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	-0.002	2.169
24	17.645	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	-0.002	2.169
25	17.645	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	-0.002	2.169

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-0.948	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[F]	tck_pad_i:[R]	0.000	-1.558	0.456
2	-0.818	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[F]	tck_pad_i:[R]	0.000	-1.553	0.581
3	-0.818	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[F]	tck_pad_i:[R]	0.000	-1.553	0.581
4	0.451	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.550	1.188
5	0.451	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.550	1.188
6	0.540	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.461	1.188
7	0.540	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.461	1.188
8	0.540	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.461	1.188
9	0.540	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.461	1.188
10	0.819	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.182	1.188
11	0.819	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.182	1.188
12	0.819	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.182	1.188
13	0.819	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.182	1.188
14	0.819	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.182	1.188
15	0.819	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.182	1.188
16	0.998	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	-0.003	1.188
17	0.998	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	-0.003	1.188
18	1.003	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.002	1.188
19	1.003	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.002	1.188
20	1.008	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.007	1.188
21	2.919	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-0.584	1.188
22	2.919	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-0.584	1.188
23	3.019	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-0.484	1.188
24	3.019	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-0.484	1.188
25	3.019	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-0.484	1.188

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.499	3.499	1.000	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s
2	2.499	3.499	1.000	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s
3	2.501	3.501	1.000	High Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s
4	2.501	3.501	1.000	High Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s
5	3.243	3.493	0.250	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	eth_udp_rx_gmii/reg_gmii_rxd_2_s0
6	3.243	3.493	0.250	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	eth_udp_rx_gmii/rx_ip_ttl_7_s0
7	3.243	3.493	0.250	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	eth_udp_rx_gmii/cnt_data_0_s0
8	3.243	3.493	0.250	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	eth_udp_rx_gmii/rx_ip_ttl_4_s0
9	3.243	3.493	0.250	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	eth_udp_rx_gmii/cnt_udp_header_1_s0
10	3.243	3.493	0.250	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	eth_udp_rx_gmii/cnt_udp_header_0_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-1.745
Data Arrival Time	23.187
Data Required Time	21.442
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.786	0.922	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
17.192	0.406	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
20.285	3.092	tNET	RR	2	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.777	0.493	tINS	RR	1	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.777	0.000	tNET	RR	2	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.827	0.050	tINS	RR	1	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.827	0.000	tNET	RR	2	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.877	0.050	tINS	RR	1	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.877	0.000	tNET	RR	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.927	0.050	tINS	RF	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
21.181	0.254	tNET	FF	1	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
21.702	0.521	tINS	FR	9	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
22.726	1.024	tNET	RR	1	R5C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n215_s0/I2
23.187	0.461	tINS	RR	1	R5C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n215_s0/F
23.187	0.000	tNET	RR	1	R5C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.541	0.886	tNET	RR	1	R5C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0/CLK
21.506	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0
21.442	-0.064	tSu		1	R5C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0

Path Statistics:

Clock Skew	0.677
Setup Relationship	5.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 2.031, 27.735%; route: 4.370, 59.676%; tC2Q: 0.922, 12.589%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.886, 100.000%

Path2

Path Summary:

Slack	-1.645
Data Arrival Time	23.087
Data Required Time	21.442
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.786	0.922	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
17.192	0.406	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
20.285	3.092	tNET	RR	2	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.777	0.493	tINS	RR	1	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.777	0.000	tNET	RR	2	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.827	0.050	tINS	RR	1	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.827	0.000	tNET	RR	2	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.877	0.050	tINS	RR	1	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.877	0.000	tNET	RR	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.927	0.050	tINS	RF	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
21.181	0.254	tNET	FF	1	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
21.702	0.521	tINS	FR	9	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
22.561	0.859	tNET	RR	1	R5C47[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/I2
23.087	0.526	tINS	RR	1	R5C47[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/F
23.087	0.000	tNET	RR	1	R5C47[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.541	0.886	tNET	RR	1	R5C47[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/CLK
21.506	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0
21.442	-0.064	tSu		1	R5C47[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0

Path Statistics:

Clock Skew	0.677
Setup Relationship	5.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 2.096, 29.019%; route: 4.205, 58.218%; tC2Q: 0.922, 12.763%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.886, 100.000%

Path3

Path Summary:

Slack	-1.580
Data Arrival Time	23.022
Data Required Time	21.442
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.786	0.922	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
17.192	0.406	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
20.285	3.092	tNET	RR	2	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.777	0.493	tINS	RR	1	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.777	0.000	tNET	RR	2	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.827	0.050	tINS	RR	1	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.827	0.000	tNET	RR	2	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.877	0.050	tINS	RR	1	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.877	0.000	tNET	RR	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.927	0.050	tINS	RF	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
21.181	0.254	tNET	FF	1	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
21.702	0.521	tINS	FR	9	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
22.561	0.859	tNET	RR	1	R5C47[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n218_s0/I2
23.022	0.461	tINS	RR	1	R5C47[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n218_s0/F
23.022	0.000	tNET	RR	1	R5C47[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.541	0.886	tNET	RR	1	R5C47[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/CLK
21.506	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0
21.442	-0.064	tSu		1	R5C47[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0

Path Statistics:

Clock Skew	0.677
Setup Relationship	5.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 2.031, 28.374%; route: 4.205, 58.746%; tC2Q: 0.922, 12.879%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.886, 100.000%

Path4

Path Summary:

Slack	-1.498
Data Arrival Time	22.939
Data Required Time	21.442
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.786	0.922	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
17.192	0.406	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
20.285	3.092	tNET	RR	2	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.777	0.493	tINS	RR	1	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.777	0.000	tNET	RR	2	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.827	0.050	tINS	RR	1	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.827	0.000	tNET	RR	2	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.877	0.050	tINS	RR	1	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.877	0.000	tNET	RR	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.927	0.050	tINS	RF	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
21.181	0.254	tNET	FF	1	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
21.702	0.521	tINS	FR	9	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
22.423	0.721	tNET	RR	1	R5C47[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n217_s0/I2
22.939	0.516	tINS	RR	1	R5C47[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n217_s0/F
22.939	0.000	tNET	RR	1	R5C47[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.541	0.886	tNET	RR	1	R5C47[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/CLK
21.506	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0
21.442	-0.064	tSu		1	R5C47[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0

Path Statistics:

Clock Skew	0.677
Setup Relationship	5.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 2.086, 29.483%; route: 4.068, 57.488%; tC2Q: 0.922, 13.029%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.886, 100.000%

Path5

Path Summary:

Slack	-1.498
Data Arrival Time	22.939
Data Required Time	21.442
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.786	0.922	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
17.192	0.406	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
20.285	3.092	tNET	RR	2	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.777	0.493	tINS	RR	1	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.777	0.000	tNET	RR	2	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.827	0.050	tINS	RR	1	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.827	0.000	tNET	RR	2	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.877	0.050	tINS	RR	1	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.877	0.000	tNET	RR	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.927	0.050	tINS	RF	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
21.181	0.254	tNET	FF	1	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
21.702	0.521	tINS	FR	9	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
22.423	0.721	tNET	RR	1	R5C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n216_s0/I2
22.939	0.516	tINS	RR	1	R5C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n216_s0/F
22.939	0.000	tNET	RR	1	R5C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.541	0.886	tNET	RR	1	R5C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/CLK
21.506	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0
21.442	-0.064	tSu		1	R5C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0

Path Statistics:

Clock Skew	0.677
Setup Relationship	5.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 2.086, 29.483%; route: 4.068, 57.488%; tC2Q: 0.922, 13.029%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.886, 100.000%

Path6

Path Summary:

Slack	-1.463
Data Arrival Time	4.428
Data Required Time	2.965
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/stop_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.595	0.913	tNET	RR	1	R2C47[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/stop_reg_2_s0/CLK
1.977	0.382	tC2Q	RR	1	R2C47[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/stop_reg_2_s0/Q
4.428	2.451	tNET	RR	1	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CEN

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.182	0.682	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.182	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.147	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen
2.965	-0.182	tSu		1	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen

Path Statistics:

Clock Skew	-0.913
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.451, 86.502%; tC2Q: 0.382, 13.498%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack	-1.219
Data Arrival Time	22.658
Data Required Time	21.439
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.786	0.922	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
17.192	0.406	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
20.285	3.092	tNET	RR	2	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.777	0.493	tINS	RR	1	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.777	0.000	tNET	RR	2	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.827	0.050	tINS	RR	1	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.827	0.000	tNET	RR	2	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.877	0.050	tINS	RR	1	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.877	0.000	tNET	RR	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.927	0.050	tINS	RF	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
21.181	0.254	tNET	FF	1	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
21.702	0.521	tINS	FR	9	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
22.658	0.956	tNET	RR	1	R6C47[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.538	0.884	tNET	RR	1	R6C47[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0/CLK
21.503	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0
21.439	-0.064	tSu		1	R6C47[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0

Path Statistics:

Clock Skew	0.674
Setup Relationship	5.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.570, 23.105%; route: 4.302, 63.327%; tC2Q: 0.922, 13.569%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.884, 100.000%

Path8

Path Summary:

Slack	-1.191
Data Arrival Time	22.661
Data Required Time	21.470
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.786	0.922	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
17.192	0.406	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
20.285	3.092	tNET	RR	2	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.777	0.493	tINS	RR	1	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.777	0.000	tNET	RR	2	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.827	0.050	tINS	RR	1	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.827	0.000	tNET	RR	2	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.877	0.050	tINS	RR	1	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.877	0.000	tNET	RR	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.927	0.050	tINS	RF	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
21.181	0.254	tNET	FF	1	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
21.702	0.521	tINS	FR	9	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
22.144	0.442	tNET	RR	1	R5C46[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/I2
22.661	0.516	tINS	RR	1	R5C46[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/F
22.661	0.000	tNET	RR	1	R5C46[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.569	0.914	tNET	RR	1	R5C46[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/CLK
21.534	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0
21.470	-0.064	tSu		1	R5C46[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0

Path Statistics:

Clock Skew	0.705
Setup Relationship	5.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 2.086, 30.692%; route: 3.789, 55.745%; tC2Q: 0.922, 13.564%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.914, 100.000%

Path9

Path Summary:

Slack	-1.146
Data Arrival Time	22.607
Data Required Time	21.461
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.786	0.922	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
17.192	0.406	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[4]
21.052	3.860	tNET	RR	2	R5C46[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n208_s/I0
21.608	0.556	tINS	RF	1	R5C46[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n208_s/COUT
21.608	0.000	tNET	FF	2	R5C46[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n207_s/CIN
21.658	0.050	tINS	FR	1	R5C46[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n207_s/COUT
21.658	0.000	tNET	RR	2	R5C46[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n206_s/CIN
21.708	0.050	tINS	RR	1	R5C46[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n206_s/COUT
21.708	0.000	tNET	RR	2	R5C46[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n205_s/CIN
21.952	0.244	tINS	RR	1	R5C46[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n205_s/SUM
22.110	0.157	tNET	RR	1	R5C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n213_s0/I1
22.607	0.498	tINS	RR	1	R5C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n213_s0/F
22.607	0.000	tNET	RR	1	R5C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.559	0.905	tNET	RR	1	R5C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0/CLK
21.524	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0
21.461	-0.064	tSu		1	R5C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0

Path Statistics:

Clock Skew	0.695
Setup Relationship	5.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.803, 26.747%; route: 4.017, 59.581%; tC2Q: 0.922, 13.672%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.905, 100.000%

Path10

Path Summary:

Slack	-1.093
Data Arrival Time	22.569
Data Required Time	21.476
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.786	0.922	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
17.192	0.406	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
20.285	3.092	tNET	RR	2	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.777	0.493	tINS	RR	1	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.777	0.000	tNET	RR	2	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.827	0.050	tINS	RR	1	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.827	0.000	tNET	RR	2	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.877	0.050	tINS	RR	1	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.877	0.000	tNET	RR	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.927	0.050	tINS	RF	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
21.181	0.254	tNET	FF	1	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
21.702	0.521	tINS	FR	9	R6C45[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
22.279	0.577	tNET	RR	1	R5C46[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n214_s0/I2
22.569	0.290	tINS	RF	1	R5C46[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n214_s0/F
22.569	0.000	tNET	FF	1	R5C46[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.569	0.914	tNET	RR	1	R5C46[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0/CLK
21.534	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0
21.476	-0.058	tSu		1	R5C46[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0

Path Statistics:

Clock Skew	0.705
Setup Relationship	5.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.860, 27.735%; route: 3.924, 58.516%; tC2Q: 0.922, 13.748%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.914, 100.000%

Path11

Path Summary:

Slack	-0.571
Data Arrival Time	4.323
Data Required Time	3.753
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.528	0.874	tNET	RR	1	R8C55[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK
1.911	0.382	tC2Q	RR	11	R8C55[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q
2.497	0.586	tNET	RR	1	R7C58[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0
3.013	0.516	tINS	RR	1	R7C58[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F
4.323	1.310	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.182	0.682	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.182	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368	0.186	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.272	0.904	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
4.237	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
3.753	-0.484	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.243
Setup Relationship	2.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.874, 100.000%
Arrival Data Path Delay	cell: 0.516, 18.470%; route: 1.896, 67.844%; tC2Q: 0.382, 13.685%
Required Clock Path Delay	cell: 0.186, 17.068%; route: 0.904, 82.932%

Path12

Path Summary:

Slack	-0.401
Data Arrival Time	21.857
Data Required Time	21.456
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.786	0.922	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
17.192	0.406	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
20.285	3.092	tNET	RR	2	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.777	0.493	tINS	RR	1	R6C44[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.777	0.000	tNET	RR	2	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.827	0.050	tINS	RR	1	R6C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.827	0.000	tNET	RR	2	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.877	0.050	tINS	RR	1	R6C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.877	0.000	tNET	RR	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.927	0.050	tINS	RR	2	R6C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
21.331	0.404	tNET	RR	1	R7C45[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s2/I2
21.857	0.526	tINS	RR	1	R7C45[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s2/F
21.857	0.000	tNET	RR	1	R7C45[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.554	0.900	tNET	RR	1	R7C45[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0/CLK
21.519	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0
21.456	-0.064	tSu		1	R7C45[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0

Path Statistics:

Clock Skew	0.690
Setup Relationship	5.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.575, 26.277%; route: 3.496, 58.340%; tC2Q: 0.922, 15.383%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.900, 100.000%

Path13

Path Summary:

Slack	-0.013
Data Arrival Time	9.517
Data Required Time	9.504
From	Number_d1_16_s0
To	eth_send_ctrl/pkt_length_1_s1
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.566	0.883	tNET	RR	1	R8C24[2][B]	Number_d1_16_s0/CLK
1.948	0.382	tC2Q	RR	2	R8C24[2][B]	Number_d1_16_s0/Q
2.838	0.890	tNET	RR	1	R11C23[3][B]	eth_send_ctrl/pkt_length_15_s18/I2
3.336	0.498	tINS	RR	1	R11C23[3][B]	eth_send_ctrl/pkt_length_15_s18/F
4.068	0.733	tNET	RR	1	R8C23[3][A]	eth_send_ctrl/pkt_length_15_s17/I3
4.483	0.415	tINS	RR	1	R8C23[3][A]	eth_send_ctrl/pkt_length_15_s17/F
4.986	0.502	tNET	RR	1	R9C27[2][B]	eth_send_ctrl/pkt_length_15_s13/I3
5.502	0.516	tINS	RR	1	R9C27[2][B]	eth_send_ctrl/pkt_length_15_s13/F
6.201	0.699	tNET	RR	1	R12C27[3][A]	eth_send_ctrl/pkt_length_15_s8/I3
6.698	0.498	tINS	RR	2	R12C27[3][A]	eth_send_ctrl/pkt_length_15_s8/F
7.048	0.350	tNET	RR	1	R12C24[1][B]	eth_send_ctrl/n402_s18/I3
7.574	0.526	tINS	RR	2	R12C24[1][B]	eth_send_ctrl/n402_s18/F
7.579	0.005	tNET	RR	1	R12C24[3][B]	eth_send_ctrl/n402_s16/I1
8.101	0.521	tINS	RR	6	R12C24[3][B]	eth_send_ctrl/n402_s16/F
9.001	0.900	tNET	RR	1	R9C25[0][A]	eth_send_ctrl/n418_s14/I3
9.517	0.516	tINS	RR	1	R9C25[0][A]	eth_send_ctrl/n418_s14/F
9.517	0.000	tNET	RR	1	R9C25[0][A]	eth_send_ctrl/pkt_length_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.568	0.886	tNET	RR	1	R9C25[0][A]	eth_send_ctrl/pkt_length_1_s1/CLK
9.504	-0.064	tSu		1	R9C25[0][A]	eth_send_ctrl/pkt_length_1_s1

Path Statistics:

Clock Skew	0.002
Setup Relationship	8.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.883, 100.000%
Arrival Data Path Delay	cell: 3.490, 43.892%; route: 4.079, 51.297%; tC2Q: 0.382, 4.811%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.886, 100.000%

Path14

Path Summary:

Slack	-0.013
Data Arrival Time	9.517
Data Required Time	9.504
From	Number_d1_16_s0
To	eth_send_ctrl/pkt_length_5_s1
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.566	0.883	tNET	RR	1	R8C24[2][B]	Number_d1_16_s0/CLK
1.948	0.382	tC2Q	RR	2	R8C24[2][B]	Number_d1_16_s0/Q
2.838	0.890	tNET	RR	1	R11C23[3][B]	eth_send_ctrl/pkt_length_15_s18/I2
3.336	0.498	tINS	RR	1	R11C23[3][B]	eth_send_ctrl/pkt_length_15_s18/F
4.068	0.733	tNET	RR	1	R8C23[3][A]	eth_send_ctrl/pkt_length_15_s17/I3
4.483	0.415	tINS	RR	1	R8C23[3][A]	eth_send_ctrl/pkt_length_15_s17/F
4.986	0.502	tNET	RR	1	R9C27[2][B]	eth_send_ctrl/pkt_length_15_s13/I3
5.502	0.516	tINS	RR	1	R9C27[2][B]	eth_send_ctrl/pkt_length_15_s13/F
6.201	0.699	tNET	RR	1	R12C27[3][A]	eth_send_ctrl/pkt_length_15_s8/I3
6.698	0.498	tINS	RR	2	R12C27[3][A]	eth_send_ctrl/pkt_length_15_s8/F
7.048	0.350	tNET	RR	1	R12C24[1][B]	eth_send_ctrl/n402_s18/I3
7.574	0.526	tINS	RR	2	R12C24[1][B]	eth_send_ctrl/n402_s18/F
7.579	0.005	tNET	RR	1	R12C24[3][B]	eth_send_ctrl/n402_s16/I1
8.101	0.521	tINS	RR	6	R12C24[3][B]	eth_send_ctrl/n402_s16/F
9.001	0.900	tNET	RR	1	R9C25[0][B]	eth_send_ctrl/n410_s14/I3
9.517	0.516	tINS	RR	1	R9C25[0][B]	eth_send_ctrl/n410_s14/F
9.517	0.000	tNET	RR	1	R9C25[0][B]	eth_send_ctrl/pkt_length_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.568	0.886	tNET	RR	1	R9C25[0][B]	eth_send_ctrl/pkt_length_5_s1/CLK
9.504	-0.064	tSu		1	R9C25[0][B]	eth_send_ctrl/pkt_length_5_s1

Path Statistics:

Clock Skew	0.002
Setup Relationship	8.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.883, 100.000%
Arrival Data Path Delay	cell: 3.490, 43.892%; route: 4.079, 51.297%; tC2Q: 0.382, 4.811%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.886, 100.000%

Path15

Path Summary:

Slack	0.071
Data Arrival Time	3.682
Data Required Time	3.753
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.531	0.876	tNET	RR	1	R9C54[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/CLK
1.913	0.382	tC2Q	RR	2	R9C54[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/Q
2.541	0.627	tNET	RR	1	R7C58[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I1
3.062	0.521	tINS	RR	1	R7C58[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F
3.682	0.620	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.182	0.682	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.182	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368	0.186	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.272	0.904	tNET	FF	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
4.237	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
3.753	-0.484	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.241
Setup Relationship	2.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.521, 24.230%; route: 1.247, 57.990%; tC2Q: 0.382, 17.780%
Required Clock Path Delay	cell: 0.186, 17.068%; route: 0.904, 82.932%

Path16

Path Summary:

Slack	0.169
Data Arrival Time	9.359
Data Required Time	9.528
From	eth_udp_tx_gmii/ip_checksum/suma_2_s0
To	eth_udp_tx_gmii/tx_data_7_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.556	0.874	tNET	RR	1	R16C25[2][B]	eth_udp_tx_gmii/ip_checksum/suma_2_s0/CLK
1.939	0.382	tC2Q	RR	1	R16C25[2][B]	eth_udp_tx_gmii/ip_checksum/suma_2_s0/Q
2.266	0.327	tNET	RR	2	R16C23[0][B]	eth_udp_tx_gmii/ip_checksum/sumb_2_s/I1
2.759	0.493	tINS	RR	1	R16C23[0][B]	eth_udp_tx_gmii/ip_checksum/sumb_2_s/COUT
2.759	0.000	tNET	RR	2	R16C23[1][A]	eth_udp_tx_gmii/ip_checksum/sumb_3_s/CIN
2.809	0.050	tINS	RR	1	R16C23[1][A]	eth_udp_tx_gmii/ip_checksum/sumb_3_s/COUT
2.809	0.000	tNET	RR	2	R16C23[1][B]	eth_udp_tx_gmii/ip_checksum/sumb_4_s/CIN
2.859	0.050	tINS	RR	1	R16C23[1][B]	eth_udp_tx_gmii/ip_checksum/sumb_4_s/COUT
2.859	0.000	tNET	RR	2	R16C23[2][A]	eth_udp_tx_gmii/ip_checksum/sumb_5_s/CIN
2.909	0.050	tINS	RR	1	R16C23[2][A]	eth_udp_tx_gmii/ip_checksum/sumb_5_s/COUT
2.909	0.000	tNET	RR	2	R16C23[2][B]	eth_udp_tx_gmii/ip_checksum/sumb_6_s/CIN
2.959	0.050	tINS	RR	1	R16C23[2][B]	eth_udp_tx_gmii/ip_checksum/sumb_6_s/COUT
2.959	0.000	tNET	RR	2	R16C24[0][A]	eth_udp_tx_gmii/ip_checksum/sumb_7_s/CIN
3.009	0.050	tINS	RR	1	R16C24[0][A]	eth_udp_tx_gmii/ip_checksum/sumb_7_s/COUT
3.009	0.000	tNET	RR	2	R16C24[0][B]	eth_udp_tx_gmii/ip_checksum/sumb_8_s/CIN
3.059	0.050	tINS	RR	1	R16C24[0][B]	eth_udp_tx_gmii/ip_checksum/sumb_8_s/COUT
3.059	0.000	tNET	RR	2	R16C24[1][A]	eth_udp_tx_gmii/ip_checksum/sumb_9_s/CIN
3.109	0.050	tINS	RR	1	R16C24[1][A]	eth_udp_tx_gmii/ip_checksum/sumb_9_s/COUT
3.109	0.000	tNET	RR	2	R16C24[1][B]	eth_udp_tx_gmii/ip_checksum/sumb_10_s/CIN
3.159	0.050	tINS	RR	1	R16C24[1][B]	eth_udp_tx_gmii/ip_checksum/sumb_10_s/COUT
3.159	0.000	tNET	RR	2	R16C24[2][A]	eth_udp_tx_gmii/ip_checksum/sumb_11_s/CIN
3.209	0.050	tINS	RR	1	R16C24[2][A]	eth_udp_tx_gmii/ip_checksum/sumb_11_s/COUT
3.209	0.000	tNET	RR	2	R16C24[2][B]	eth_udp_tx_gmii/ip_checksum/sumb_12_s/CIN
3.259	0.050	tINS	RR	1	R16C24[2][B]	eth_udp_tx_gmii/ip_checksum/sumb_12_s/COUT
3.259	0.000	tNET	RR	2	R16C25[0][A]	eth_udp_tx_gmii/ip_checksum/sumb_13_s/CIN
3.309	0.050	tINS	RR	1	R16C25[0][A]	eth_udp_tx_gmii/ip_checksum/sumb_13_s/COUT
3.309	0.000	tNET	RR	2	R16C25[0][B]	eth_udp_tx_gmii/ip_checksum/sumb_14_s/CIN
3.359	0.050	tINS	RR	1	R16C25[0][B]	eth_udp_tx_gmii/ip_checksum/sumb_14_s/COUT
3.359	0.000	tNET	RR	2	R16C25[1][A]	eth_udp_tx_gmii/ip_checksum/sumb_15_s/CIN
3.409	0.050	tINS	RR	4	R16C25[1][A]	eth_udp_tx_gmii/ip_checksum/sumb_15_s/COUT
3.818	0.409	tNET	RR	1	R16C26[3][B]	eth_udp_tx_gmii/n936_s18/I0
4.233	0.415	tINS	RR	4	R16C26[3][B]	eth_udp_tx_gmii/n936_s18/F
4.588	0.355	tNET	RR	1	R17C25[3][A]	eth_udp_tx_gmii/n932_s25/I3
5.085	0.498	tINS	RR	4	R17C25[3][A]	eth_udp_tx_gmii/n932_s25/F
5.245	0.160	tNET	RR	1	R17C24[1][B]	eth_udp_tx_gmii/n944_s15/I3
5.771	0.526	tINS	RR	3	R17C24[1][B]	eth_udp_tx_gmii/n944_s15/F
5.911	0.140	tNET	RR	1	R17C24[1][A]	eth_udp_tx_gmii/n932_s24/I3
6.174	0.262	tINS	RR	2	R17C24[1][A]	eth_udp_tx_gmii/n932_s24/F
7.200	1.026	tNET	RR	1	R20C25[3][B]	eth_udp_tx_gmii/n932_s17/I1
7.721	0.521	tINS	RR	1	R20C25[3][B]	eth_udp_tx_gmii/n932_s17/F
7.879	0.157	tNET	RR	1	R21C25[2][B]	eth_udp_tx_gmii/n932_s11/I0
8.395	0.516	tINS	RR	1	R21C25[2][B]	eth_udp_tx_gmii/n932_s11/F
8.398	0.003	tNET	RR	1	R21C25[3][A]	eth_udp_tx_gmii/n932_s9/I0
8.895	0.498	tINS	RR	1	R21C25[3][A]	eth_udp_tx_gmii/n932_s9/F
8.898	0.003	tNET	RR	1	R21C25[0][A]	eth_udp_tx_gmii/n932_s7/I2
9.359	0.461	tINS	RR	1	R21C25[0][A]	eth_udp_tx_gmii/n932_s7/F
9.359	0.000	tNET	RR	1	R21C25[0][A]	eth_udp_tx_gmii/tx_data_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.592	0.910	tNET	RR	1	R21C25[0][A]	eth_udp_tx_gmii/tx_data_7_s0/CLK
9.528	-0.064	tSu		1	R21C25[0][A]	eth_udp_tx_gmii/tx_data_7_s0

Path Statistics:

Clock Skew	0.036
Setup Relationship	8.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.874, 100.000%
Arrival Data Path Delay	cell: 4.840, 62.031%; route: 2.580, 33.066%; tC2Q: 0.382, 4.902%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.910, 100.000%

Path17

Path Summary:

Slack	0.170
Data Arrival Time	9.324
Data Required Time	9.495
From	Number_d1_16_s0
To	eth_send_ctrl/pkt_length_2_s1
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.566	0.883	tNET	RR	1	R8C24[2][B]	Number_d1_16_s0/CLK
1.948	0.382	tC2Q	RR	2	R8C24[2][B]	Number_d1_16_s0/Q
2.838	0.890	tNET	RR	1	R11C23[3][B]	eth_send_ctrl/pkt_length_15_s18/I2
3.336	0.498	tINS	RR	1	R11C23[3][B]	eth_send_ctrl/pkt_length_15_s18/F
4.068	0.733	tNET	RR	1	R8C23[3][A]	eth_send_ctrl/pkt_length_15_s17/I3
4.483	0.415	tINS	RR	1	R8C23[3][A]	eth_send_ctrl/pkt_length_15_s17/F
4.986	0.502	tNET	RR	1	R9C27[2][B]	eth_send_ctrl/pkt_length_15_s13/I3
5.502	0.516	tINS	RR	1	R9C27[2][B]	eth_send_ctrl/pkt_length_15_s13/F
6.201	0.699	tNET	RR	1	R12C27[3][A]	eth_send_ctrl/pkt_length_15_s8/I3
6.698	0.498	tINS	RR	2	R12C27[3][A]	eth_send_ctrl/pkt_length_15_s8/F
7.048	0.350	tNET	RR	1	R12C24[1][B]	eth_send_ctrl/n402_s18/I3
7.574	0.526	tINS	RR	2	R12C24[1][B]	eth_send_ctrl/n402_s18/F
7.579	0.005	tNET	RR	1	R12C24[3][B]	eth_send_ctrl/n402_s16/I1
8.101	0.521	tINS	RR	6	R12C24[3][B]	eth_send_ctrl/n402_s16/F
8.808	0.708	tNET	RR	1	R9C24[0][B]	eth_send_ctrl/n416_s14/I3
9.324	0.516	tINS	RR	1	R9C24[0][B]	eth_send_ctrl/n416_s14/F
9.324	0.000	tNET	RR	1	R9C24[0][B]	eth_send_ctrl/pkt_length_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.558	0.876	tNET	RR	1	R9C24[0][B]	eth_send_ctrl/pkt_length_2_s1/CLK
9.495	-0.064	tSu		1	R9C24[0][B]	eth_send_ctrl/pkt_length_2_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	8.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.883, 100.000%
Arrival Data Path Delay	cell: 3.490, 44.981%; route: 3.886, 50.089%; tC2Q: 0.382, 4.930%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%

Path18

Path Summary:

Slack	0.175
Data Arrival Time	9.344
Data Required Time	9.519
From	eth_udp_tx_gmii/ip_checksum/suma_2_s0
To	eth_udp_tx_gmii/tx_data_6_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.556	0.874	tNET	RR	1	R16C25[2][B]	eth_udp_tx_gmii/ip_checksum/suma_2_s0/CLK
1.939	0.382	tC2Q	RR	1	R16C25[2][B]	eth_udp_tx_gmii/ip_checksum/suma_2_s0/Q
2.266	0.327	tNET	RR	2	R16C23[0][B]	eth_udp_tx_gmii/ip_checksum/sumb_2_s/I1
2.759	0.493	tINS	RR	1	R16C23[0][B]	eth_udp_tx_gmii/ip_checksum/sumb_2_s/COUT
2.759	0.000	tNET	RR	2	R16C23[1][A]	eth_udp_tx_gmii/ip_checksum/sumb_3_s/CIN
2.809	0.050	tINS	RR	1	R16C23[1][A]	eth_udp_tx_gmii/ip_checksum/sumb_3_s/COUT
2.809	0.000	tNET	RR	2	R16C23[1][B]	eth_udp_tx_gmii/ip_checksum/sumb_4_s/CIN
2.859	0.050	tINS	RR	1	R16C23[1][B]	eth_udp_tx_gmii/ip_checksum/sumb_4_s/COUT
2.859	0.000	tNET	RR	2	R16C23[2][A]	eth_udp_tx_gmii/ip_checksum/sumb_5_s/CIN
2.909	0.050	tINS	RR	1	R16C23[2][A]	eth_udp_tx_gmii/ip_checksum/sumb_5_s/COUT
2.909	0.000	tNET	RR	2	R16C23[2][B]	eth_udp_tx_gmii/ip_checksum/sumb_6_s/CIN
2.959	0.050	tINS	RR	1	R16C23[2][B]	eth_udp_tx_gmii/ip_checksum/sumb_6_s/COUT
2.959	0.000	tNET	RR	2	R16C24[0][A]	eth_udp_tx_gmii/ip_checksum/sumb_7_s/CIN
3.009	0.050	tINS	RR	1	R16C24[0][A]	eth_udp_tx_gmii/ip_checksum/sumb_7_s/COUT
3.009	0.000	tNET	RR	2	R16C24[0][B]	eth_udp_tx_gmii/ip_checksum/sumb_8_s/CIN
3.059	0.050	tINS	RR	1	R16C24[0][B]	eth_udp_tx_gmii/ip_checksum/sumb_8_s/COUT
3.059	0.000	tNET	RR	2	R16C24[1][A]	eth_udp_tx_gmii/ip_checksum/sumb_9_s/CIN
3.109	0.050	tINS	RR	1	R16C24[1][A]	eth_udp_tx_gmii/ip_checksum/sumb_9_s/COUT
3.109	0.000	tNET	RR	2	R16C24[1][B]	eth_udp_tx_gmii/ip_checksum/sumb_10_s/CIN
3.159	0.050	tINS	RR	1	R16C24[1][B]	eth_udp_tx_gmii/ip_checksum/sumb_10_s/COUT
3.159	0.000	tNET	RR	2	R16C24[2][A]	eth_udp_tx_gmii/ip_checksum/sumb_11_s/CIN
3.209	0.050	tINS	RR	1	R16C24[2][A]	eth_udp_tx_gmii/ip_checksum/sumb_11_s/COUT
3.209	0.000	tNET	RR	2	R16C24[2][B]	eth_udp_tx_gmii/ip_checksum/sumb_12_s/CIN
3.259	0.050	tINS	RR	1	R16C24[2][B]	eth_udp_tx_gmii/ip_checksum/sumb_12_s/COUT
3.259	0.000	tNET	RR	2	R16C25[0][A]	eth_udp_tx_gmii/ip_checksum/sumb_13_s/CIN
3.309	0.050	tINS	RR	1	R16C25[0][A]	eth_udp_tx_gmii/ip_checksum/sumb_13_s/COUT
3.309	0.000	tNET	RR	2	R16C25[0][B]	eth_udp_tx_gmii/ip_checksum/sumb_14_s/CIN
3.359	0.050	tINS	RR	1	R16C25[0][B]	eth_udp_tx_gmii/ip_checksum/sumb_14_s/COUT
3.359	0.000	tNET	RR	2	R16C25[1][A]	eth_udp_tx_gmii/ip_checksum/sumb_15_s/CIN
3.409	0.050	tINS	RR	4	R16C25[1][A]	eth_udp_tx_gmii/ip_checksum/sumb_15_s/COUT
3.818	0.409	tNET	RR	1	R16C26[3][B]	eth_udp_tx_gmii/n936_s18/I0
4.233	0.415	tINS	RR	4	R16C26[3][B]	eth_udp_tx_gmii/n936_s18/F
4.588	0.355	tNET	RR	1	R17C25[3][A]	eth_udp_tx_gmii/n932_s25/I3
5.085	0.498	tINS	RR	4	R17C25[3][A]	eth_udp_tx_gmii/n932_s25/F
5.245	0.160	tNET	RR	1	R17C24[1][B]	eth_udp_tx_gmii/n944_s15/I3
5.771	0.526	tINS	RR	3	R17C24[1][B]	eth_udp_tx_gmii/n944_s15/F
5.911	0.140	tNET	RR	1	R17C24[1][A]	eth_udp_tx_gmii/n932_s24/I3
6.174	0.262	tINS	RR	2	R17C24[1][A]	eth_udp_tx_gmii/n932_s24/F
7.064	0.890	tNET	RR	1	R20C25[1][A]	eth_udp_tx_gmii/n934_s17/I1
7.326	0.262	tINS	RR	1	R20C25[1][A]	eth_udp_tx_gmii/n934_s17/F
7.864	0.537	tNET	RR	1	R21C28[2][B]	eth_udp_tx_gmii/n934_s14/I1
8.380	0.516	tINS	RR	1	R21C28[2][B]	eth_udp_tx_gmii/n934_s14/F
8.383	0.003	tNET	RR	1	R21C28[3][A]	eth_udp_tx_gmii/n934_s9/I1
8.880	0.498	tINS	RR	1	R21C28[3][A]	eth_udp_tx_gmii/n934_s9/F
8.883	0.003	tNET	RR	1	R21C28[0][A]	eth_udp_tx_gmii/n934_s7/I2
9.344	0.461	tINS	RR	1	R21C28[0][A]	eth_udp_tx_gmii/n934_s7/F
9.344	0.000	tNET	RR	1	R21C28[0][A]	eth_udp_tx_gmii/tx_data_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.583	0.901	tNET	RR	1	R21C28[0][A]	eth_udp_tx_gmii/tx_data_6_s0/CLK
9.519	-0.064	tSu		1	R21C28[0][A]	eth_udp_tx_gmii/tx_data_6_s0

Path Statistics:

Clock Skew	0.026
Setup Relationship	8.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.874, 100.000%
Arrival Data Path Delay	cell: 4.581, 58.828%; route: 2.824, 36.260%; tC2Q: 0.382, 4.912%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.901, 100.000%

Path19

Path Summary:

Slack	0.255
Data Arrival Time	9.002
Data Required Time	9.257
From	Number_d1_16_s0
To	eth_send_ctrl/pkt_length_1_s1
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.566	0.883	tNET	RR	1	R8C24[2][B]	Number_d1_16_s0/CLK
1.948	0.382	tC2Q	RR	2	R8C24[2][B]	Number_d1_16_s0/Q
2.838	0.890	tNET	RR	1	R11C23[3][B]	eth_send_ctrl/pkt_length_15_s18/I2
3.336	0.498	tINS	RR	1	R11C23[3][B]	eth_send_ctrl/pkt_length_15_s18/F
4.068	0.733	tNET	RR	1	R8C23[3][A]	eth_send_ctrl/pkt_length_15_s17/I3
4.483	0.415	tINS	RR	1	R8C23[3][A]	eth_send_ctrl/pkt_length_15_s17/F
4.986	0.502	tNET	RR	1	R9C27[2][B]	eth_send_ctrl/pkt_length_15_s13/I3
5.502	0.516	tINS	RR	1	R9C27[2][B]	eth_send_ctrl/pkt_length_15_s13/F
6.201	0.699	tNET	RR	1	R12C27[3][A]	eth_send_ctrl/pkt_length_15_s8/I3
6.698	0.498	tINS	RR	2	R12C27[3][A]	eth_send_ctrl/pkt_length_15_s8/F
7.083	0.385	tNET	RR	1	R12C24[3][A]	eth_send_ctrl/pkt_length_15_s5/I0
7.581	0.498	tINS	RR	2	R12C24[3][A]	eth_send_ctrl/pkt_length_15_s5/F
7.741	0.160	tNET	RR	1	R11C24[3][B]	eth_send_ctrl/pkt_length_15_s3/I1
8.262	0.521	tINS	RR	11	R11C24[3][B]	eth_send_ctrl/pkt_length_15_s3/F
9.002	0.740	tNET	RR	1	R9C25[0][A]	eth_send_ctrl/pkt_length_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.568	0.886	tNET	RR	1	R9C25[0][A]	eth_send_ctrl/pkt_length_1_s1/CLK
9.257	-0.311	tSu		1	R9C25[0][A]	eth_send_ctrl/pkt_length_1_s1

Path Statistics:

Clock Skew	0.002
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.883, 100.000%
Arrival Data Path Delay	cell: 2.945, 39.603%; route: 4.109, 55.253%; tC2Q: 0.382, 5.144%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.886, 100.000%

Path20

Path Summary:

Slack	0.255
Data Arrival Time	9.002
Data Required Time	9.257
From	Number_d1_16_s0
To	eth_send_ctrl/pkt_length_5_s1
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.566	0.883	tNET	RR	1	R8C24[2][B]	Number_d1_16_s0/CLK
1.948	0.382	tC2Q	RR	2	R8C24[2][B]	Number_d1_16_s0/Q
2.838	0.890	tNET	RR	1	R11C23[3][B]	eth_send_ctrl/pkt_length_15_s18/I2
3.336	0.498	tINS	RR	1	R11C23[3][B]	eth_send_ctrl/pkt_length_15_s18/F
4.068	0.733	tNET	RR	1	R8C23[3][A]	eth_send_ctrl/pkt_length_15_s17/I3
4.483	0.415	tINS	RR	1	R8C23[3][A]	eth_send_ctrl/pkt_length_15_s17/F
4.986	0.502	tNET	RR	1	R9C27[2][B]	eth_send_ctrl/pkt_length_15_s13/I3
5.502	0.516	tINS	RR	1	R9C27[2][B]	eth_send_ctrl/pkt_length_15_s13/F
6.201	0.699	tNET	RR	1	R12C27[3][A]	eth_send_ctrl/pkt_length_15_s8/I3
6.698	0.498	tINS	RR	2	R12C27[3][A]	eth_send_ctrl/pkt_length_15_s8/F
7.083	0.385	tNET	RR	1	R12C24[3][A]	eth_send_ctrl/pkt_length_15_s5/I0
7.581	0.498	tINS	RR	2	R12C24[3][A]	eth_send_ctrl/pkt_length_15_s5/F
7.741	0.160	tNET	RR	1	R11C24[3][B]	eth_send_ctrl/pkt_length_15_s3/I1
8.262	0.521	tINS	RR	11	R11C24[3][B]	eth_send_ctrl/pkt_length_15_s3/F
9.002	0.740	tNET	RR	1	R9C25[0][B]	eth_send_ctrl/pkt_length_5_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.568	0.886	tNET	RR	1	R9C25[0][B]	eth_send_ctrl/pkt_length_5_s1/CLK
9.257	-0.311	tSu		1	R9C25[0][B]	eth_send_ctrl/pkt_length_5_s1

Path Statistics:

Clock Skew	0.002
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.883, 100.000%
Arrival Data Path Delay	cell: 2.945, 39.603%; route: 4.109, 55.253%; tC2Q: 0.382, 5.144%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.886, 100.000%

Path21

Path Summary:

Slack	0.274
Data Arrival Time	9.181
Data Required Time	9.454
From	Number_d1_16_s0
To	eth_send_ctrl/state_0_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.566	0.883	tNET	RR	1	R8C24[2][B]	Number_d1_16_s0/CLK
1.948	0.382	tC2Q	RR	2	R8C24[2][B]	Number_d1_16_s0/Q
2.838	0.890	tNET	RR	1	R11C23[3][B]	eth_send_ctrl/pkt_length_15_s18/I2
3.336	0.498	tINS	RR	1	R11C23[3][B]	eth_send_ctrl/pkt_length_15_s18/F
4.068	0.733	tNET	RR	1	R8C23[3][A]	eth_send_ctrl/pkt_length_15_s17/I3
4.483	0.415	tINS	RR	1	R8C23[3][A]	eth_send_ctrl/pkt_length_15_s17/F
4.986	0.502	tNET	RR	1	R9C27[2][B]	eth_send_ctrl/pkt_length_15_s13/I3
5.502	0.516	tINS	RR	1	R9C27[2][B]	eth_send_ctrl/pkt_length_15_s13/F
6.201	0.699	tNET	RR	1	R12C27[3][A]	eth_send_ctrl/pkt_length_15_s8/I3
6.698	0.498	tINS	RR	2	R12C27[3][A]	eth_send_ctrl/pkt_length_15_s8/F
7.083	0.385	tNET	RR	1	R12C24[3][A]	eth_send_ctrl/pkt_length_15_s5/I0
7.581	0.498	tINS	RR	2	R12C24[3][A]	eth_send_ctrl/pkt_length_15_s5/F
7.741	0.160	tNET	RR	1	R11C24[3][B]	eth_send_ctrl/pkt_length_15_s3/I1
8.262	0.521	tINS	RR	11	R11C24[3][B]	eth_send_ctrl/pkt_length_15_s3/F
8.654	0.392	tNET	RR	1	R12C23[0][A]	eth_send_ctrl/n427_s9/I2
9.181	0.526	tINS	RR	1	R12C23[0][A]	eth_send_ctrl/n427_s9/F
9.181	0.000	tNET	RR	1	R12C23[0][A]	eth_send_ctrl/state_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.518	0.836	tNET	RR	1	R12C23[0][A]	eth_send_ctrl/state_0_s0/CLK
9.454	-0.064	tSu		1	R12C23[0][A]	eth_send_ctrl/state_0_s0

Path Statistics:

Clock Skew	-0.048
Setup Relationship	8.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.883, 100.000%
Arrival Data Path Delay	cell: 3.471, 45.584%; route: 3.761, 49.393%; tC2Q: 0.382, 5.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.836, 100.000%

Path22

Path Summary:

Slack	0.296
Data Arrival Time	9.225
Data Required Time	9.521
From	eth_udp_rx_gmii/ip_checksum/suma_4_s0
To	eth_udp_rx_gmii/ip_header_check_ok_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.575	0.893	tNET	RR	1	R6C34[2][A]	eth_udp_rx_gmii/ip_checksum/suma_4_s0/CLK
1.958	0.382	tC2Q	RR	1	R6C34[2][A]	eth_udp_rx_gmii/ip_checksum/suma_4_s0/Q
2.603	0.645	tNET	RR	2	R6C38[0][B]	eth_udp_rx_gmii/ip_checksum/sumb_4_s/I1
3.095	0.493	tINS	RR	1	R6C38[0][B]	eth_udp_rx_gmii/ip_checksum/sumb_4_s/COUT
3.095	0.000	tNET	RR	2	R6C38[1][A]	eth_udp_rx_gmii/ip_checksum/sumb_5_s/CIN
3.145	0.050	tINS	RR	1	R6C38[1][A]	eth_udp_rx_gmii/ip_checksum/sumb_5_s/COUT
3.145	0.000	tNET	RR	2	R6C38[1][B]	eth_udp_rx_gmii/ip_checksum/sumb_6_s/CIN
3.195	0.050	tINS	RR	1	R6C38[1][B]	eth_udp_rx_gmii/ip_checksum/sumb_6_s/COUT
3.195	0.000	tNET	RR	2	R6C38[2][A]	eth_udp_rx_gmii/ip_checksum/sumb_7_s/CIN
3.245	0.050	tINS	RR	1	R6C38[2][A]	eth_udp_rx_gmii/ip_checksum/sumb_7_s/COUT
3.245	0.000	tNET	RR	2	R6C38[2][B]	eth_udp_rx_gmii/ip_checksum/sumb_8_s/CIN
3.295	0.050	tINS	RR	1	R6C38[2][B]	eth_udp_rx_gmii/ip_checksum/sumb_8_s/COUT
3.295	0.000	tNET	RR	2	R6C39[0][A]	eth_udp_rx_gmii/ip_checksum/sumb_9_s/CIN
3.345	0.050	tINS	RR	1	R6C39[0][A]	eth_udp_rx_gmii/ip_checksum/sumb_9_s/COUT
3.345	0.000	tNET	RR	2	R6C39[0][B]	eth_udp_rx_gmii/ip_checksum/sumb_10_s/CIN
3.395	0.050	tINS	RR	1	R6C39[0][B]	eth_udp_rx_gmii/ip_checksum/sumb_10_s/COUT
3.395	0.000	tNET	RR	2	R6C39[1][A]	eth_udp_rx_gmii/ip_checksum/sumb_11_s/CIN
3.445	0.050	tINS	RR	1	R6C39[1][A]	eth_udp_rx_gmii/ip_checksum/sumb_11_s/COUT
3.445	0.000	tNET	RR	2	R6C39[1][B]	eth_udp_rx_gmii/ip_checksum/sumb_12_s/CIN
3.495	0.050	tINS	RR	1	R6C39[1][B]	eth_udp_rx_gmii/ip_checksum/sumb_12_s/COUT
3.495	0.000	tNET	RR	2	R6C39[2][A]	eth_udp_rx_gmii/ip_checksum/sumb_13_s/CIN
3.545	0.050	tINS	RR	1	R6C39[2][A]	eth_udp_rx_gmii/ip_checksum/sumb_13_s/COUT
3.545	0.000	tNET	RR	2	R6C39[2][B]	eth_udp_rx_gmii/ip_checksum/sumb_14_s/CIN
3.595	0.050	tINS	RR	1	R6C39[2][B]	eth_udp_rx_gmii/ip_checksum/sumb_14_s/COUT
3.595	0.000	tNET	RR	2	R6C40[0][A]	eth_udp_rx_gmii/ip_checksum/sumb_15_s/CIN
3.645	0.050	tINS	RF	3	R6C40[0][A]	eth_udp_rx_gmii/ip_checksum/sumb_15_s/COUT
3.899	0.254	tNET	FF	1	R6C40[2][A]	eth_udp_rx_gmii/n1388_s29/I0
4.415	0.516	tINS	FR	3	R6C40[2][A]	eth_udp_rx_gmii/n1388_s29/F
4.575	0.160	tNET	RR	1	R5C40[3][B]	eth_udp_rx_gmii/n1388_s17/I2
5.073	0.498	tINS	RR	3	R5C40[3][B]	eth_udp_rx_gmii/n1388_s17/F
5.423	0.350	tNET	RR	1	R6C39[3][B]	eth_udp_rx_gmii/n1388_s24/I2
5.944	0.521	tINS	RR	2	R6C39[3][B]	eth_udp_rx_gmii/n1388_s24/F
6.104	0.160	tNET	RR	1	R6C40[3][B]	eth_udp_rx_gmii/n1388_s20/I2
6.519	0.415	tINS	RR	3	R6C40[3][B]	eth_udp_rx_gmii/n1388_s20/F
6.871	0.352	tNET	RR	1	R7C41[3][B]	eth_udp_rx_gmii/n1388_s14/I2
7.369	0.498	tINS	RR	1	R7C41[3][B]	eth_udp_rx_gmii/n1388_s14/F
7.371	0.003	tNET	RR	1	R7C41[0][A]	eth_udp_rx_gmii/n1388_s7/I1
7.898	0.526	tINS	RR	1	R7C41[0][A]	eth_udp_rx_gmii/n1388_s7/F
8.055	0.157	tNET	RR	1	R6C41[2][A]	eth_udp_rx_gmii/n1388_s2/I2
8.571	0.516	tINS	RR	1	R6C41[2][A]	eth_udp_rx_gmii/n1388_s2/F
8.709	0.137	tNET	RR	1	R6C41[0][A]	eth_udp_rx_gmii/n1388_s0/I1
9.225	0.516	tINS	RR	1	R6C41[0][A]	eth_udp_rx_gmii/n1388_s0/F
9.225	0.000	tNET	RR	1	R6C41[0][A]	eth_udp_rx_gmii/ip_header_check_ok_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.585	0.902	tNET	RR	1	R6C41[0][A]	eth_udp_rx_gmii/ip_header_check_ok_s0/CLK
9.521	-0.064	tSu		1	R6C41[0][A]	eth_udp_rx_gmii/ip_header_check_ok_s0

Path Statistics:

Clock Skew	0.009
Setup Relationship	8.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.893, 100.000%
Arrival Data Path Delay	cell: 5.049, 65.997%; route: 2.219, 29.003%; tC2Q: 0.382, 5.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.902, 100.000%

Path23

Path Summary:

Slack	0.300
Data Arrival Time	8.947
Data Required Time	9.247
From	Number_d1_16_s0
To	eth_send_ctrl/pkt_length_2_s1
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.566	0.883	tNET	RR	1	R8C24[2][B]	Number_d1_16_s0/CLK
1.948	0.382	tC2Q	RR	2	R8C24[2][B]	Number_d1_16_s0/Q
2.838	0.890	tNET	RR	1	R11C23[3][B]	eth_send_ctrl/pkt_length_15_s18/I2
3.336	0.498	tINS	RR	1	R11C23[3][B]	eth_send_ctrl/pkt_length_15_s18/F
4.068	0.733	tNET	RR	1	R8C23[3][A]	eth_send_ctrl/pkt_length_15_s17/I3
4.483	0.415	tINS	RR	1	R8C23[3][A]	eth_send_ctrl/pkt_length_15_s17/F
4.986	0.502	tNET	RR	1	R9C27[2][B]	eth_send_ctrl/pkt_length_15_s13/I3
5.502	0.516	tINS	RR	1	R9C27[2][B]	eth_send_ctrl/pkt_length_15_s13/F
6.201	0.699	tNET	RR	1	R12C27[3][A]	eth_send_ctrl/pkt_length_15_s8/I3
6.698	0.498	tINS	RR	2	R12C27[3][A]	eth_send_ctrl/pkt_length_15_s8/F
7.083	0.385	tNET	RR	1	R12C24[3][A]	eth_send_ctrl/pkt_length_15_s5/I0
7.581	0.498	tINS	RR	2	R12C24[3][A]	eth_send_ctrl/pkt_length_15_s5/F
7.741	0.160	tNET	RR	1	R11C24[3][B]	eth_send_ctrl/pkt_length_15_s3/I1
8.262	0.521	tINS	RR	11	R11C24[3][B]	eth_send_ctrl/pkt_length_15_s3/F
8.947	0.685	tNET	RR	1	R9C24[0][B]	eth_send_ctrl/pkt_length_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.558	0.876	tNET	RR	1	R9C24[0][B]	eth_send_ctrl/pkt_length_2_s1/CLK
9.247	-0.311	tSu		1	R9C24[0][B]	eth_send_ctrl/pkt_length_2_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.883, 100.000%
Arrival Data Path Delay	cell: 2.945, 39.898%; route: 4.054, 54.920%; tC2Q: 0.382, 5.182%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%

Path24

Path Summary:

Slack	0.318
Data Arrival Time	21.128
Data Required Time	21.446
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_5_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.786	0.922	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
17.192	0.406	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[5]
21.128	3.936	tNET	RR	1	R7C48[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.545	0.891	tNET	RR	1	R7C48[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_5_s0/CLK
21.510	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_5_s0
21.446	-0.064	tSu		1	R7C48[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_5_s0

Path Statistics:

Clock Skew	0.681
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.406, 7.713%; route: 3.936, 74.775%; tC2Q: 0.922, 17.512%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.891, 100.000%

Path25

Path Summary:

Slack	0.476
Data Arrival Time	8.997
Data Required Time	9.474
From	eth_udp_tx_gmii/curr_state.TX_DATA_s1
To	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.547	0.865	tNET	RR	1	R16C22[2][A]	eth_udp_tx_gmii/curr_state.TX_DATA_s1/CLK
1.930	0.382	tC2Q	RR	34	R16C22[2][A]	eth_udp_tx_gmii/curr_state.TX_DATA_s1/Q
2.638	0.709	tNET	RR	1	R17C32[3][B]	fifo_tx/fifo_inst/rbin_num_next_2_s6/I1
3.160	0.521	tINS	RR	7	R17C32[3][B]	fifo_tx/fifo_inst/rbin_num_next_2_s6/F
3.665	0.505	tNET	RR	1	R13C31[2][A]	fifo_tx/fifo_inst/rbin_num_next_5_s6/I3
4.126	0.461	tINS	RR	8	R13C31[2][A]	fifo_tx/fifo_inst/rbin_num_next_5_s6/F
4.486	0.360	tNET	RR	1	R11C30[1][B]	fifo_tx/fifo_inst/Small.rgraynext_6_s2/I1
4.947	0.461	tINS	RR	3	R11C30[1][B]	fifo_tx/fifo_inst/Small.rgraynext_6_s2/F
5.090	0.142	tNET	RR	1	R11C30[1][A]	fifo_tx/fifo_inst/Small.rgraynext_6_s0/I2
5.551	0.461	tINS	RR	2	R11C30[1][A]	fifo_tx/fifo_inst/Small.rgraynext_6_s0/F
6.155	0.604	tNET	RR	2	R15C31[0][A]	fifo_tx/fifo_inst/n289_s0/I0
6.711	0.556	tINS	RF	1	R15C31[0][A]	fifo_tx/fifo_inst/n289_s0/COUT
6.711	0.000	tNET	FF	2	R15C31[0][B]	fifo_tx/fifo_inst/n290_s0/CIN
6.761	0.050	tINS	FR	1	R15C31[0][B]	fifo_tx/fifo_inst/n290_s0/COUT
6.761	0.000	tNET	RR	2	R15C31[1][A]	fifo_tx/fifo_inst/n291_s0/CIN
6.811	0.050	tINS	RR	1	R15C31[1][A]	fifo_tx/fifo_inst/n291_s0/COUT
6.811	0.000	tNET	RR	2	R15C31[1][B]	fifo_tx/fifo_inst/n292_s0/CIN
6.861	0.050	tINS	RR	1	R15C31[1][B]	fifo_tx/fifo_inst/n292_s0/COUT
6.861	0.000	tNET	RR	2	R15C31[2][A]	fifo_tx/fifo_inst/n293_s0/CIN
6.911	0.050	tINS	RR	2	R15C31[2][A]	fifo_tx/fifo_inst/n293_s0/COUT
7.505	0.594	tNET	RR	1	R17C32[3][A]	fifo_tx/fifo_inst/n36_s1/I2
8.002	0.498	tINS	RR	1	R17C32[3][A]	fifo_tx/fifo_inst/n36_s1/F
8.997	0.995	tNET	RR	1	BSRAM_R10[9]	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CEB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.561	0.878	tNET	RR	1	BSRAM_R10[9]	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CLKB
9.474	-0.087	tSu		1	BSRAM_R10[9]	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s

Path Statistics:

Clock Skew	0.013
Setup Relationship	8.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.865, 100.000%
Arrival Data Path Delay	cell: 3.159, 42.399%; route: 3.909, 52.466%; tC2Q: 0.382, 5.134%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.878, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.540
Data Arrival Time	102.054
Data Required Time	102.593
From	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
To	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
100.000	100.000					active clock edge time
100.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
100.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
101.029	0.374	tNET	RR	1	R35C21[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
101.209	0.180	tC2Q	RR	3	R35C21[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/Q
101.452	0.244	tNET	RR	1	R33C22[2][A]	gw_gao_inst_0/u_la0_top/n1151_s1/I0
101.635	0.183	tINS	RR	1	R33C22[2][A]	gw_gao_inst_0/u_la0_top/n1151_s1/F
102.054	0.419	tNET	RR	1	R32C23[0][B]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
100.000	100.000					active clock edge time
100.000	0.000					tck_pad_i
100.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
100.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
100.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
101.351	0.675	tINS	RR	199	-	gw_gao_inst_0/u_gw_jtag/tck_o
102.582	1.231	tNET	RR	1	R32C23[0][B]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK
102.617	0.035	tUnc				gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0
102.594	-0.024	tHld		1	R32C23[0][B]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0

Path Statistics:

Clock Skew	1.553
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.374, 100.000%
Arrival Data Path Delay	cell: 0.183, 17.805%; route: 0.662, 64.634%; tC2Q: 0.180, 17.561%
Required Clock Path Delay	cell: 1.351, 52.319%; route: 1.231, 47.681%

Path2

Path Summary:

Slack	0.049
Data Arrival Time	1.321
Data Required Time	1.272
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_11_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.024	0.370	tNET	RR	1	R27C51[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_11_s0/CLK
1.204	0.180	tC2Q	RR	1	R27C51[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_11_s0/Q
1.321	0.116	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.023	0.369	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA
1.272	0.249	tHld		1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.370, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path3

Path Summary:

Slack	0.073
Data Arrival Time	1.345
Data Required Time	1.272
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.039	0.385	tNET	RR	1	R24C51[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_2_s0/CLK
1.219	0.180	tC2Q	RR	1	R24C51[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_2_s0/Q
1.345	0.126	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.023	0.369	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA
1.272	0.249	tHld		1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.016
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.385, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path4

Path Summary:

Slack	0.077
Data Arrival Time	1.344
Data Required Time	1.267
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_29_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.041	0.386	tNET	RR	1	R8C73[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_29_s0/CLK
1.221	0.180	tC2Q	RR	1	R8C73[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_29_s0/Q
1.344	0.124	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[29]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.018	0.364	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.267	0.249	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.023
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.386, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.364, 100.000%

Path5

Path Summary:

Slack	0.077
Data Arrival Time	1.344
Data Required Time	1.267
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_28_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.041	0.386	tNET	RR	1	R8C73[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_28_s0/CLK
1.221	0.180	tC2Q	RR	1	R8C73[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_28_s0/Q
1.344	0.124	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[28]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.018	0.364	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.267	0.249	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.023
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.386, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.364, 100.000%

Path6

Path Summary:

Slack	0.077
Data Arrival Time	1.344
Data Required Time	1.267
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_26_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.041	0.386	tNET	RR	1	R8C73[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_26_s0/CLK
1.221	0.180	tC2Q	RR	1	R8C73[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_26_s0/Q
1.344	0.124	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[26]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.018	0.364	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.267	0.249	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.023
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.386, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.364, 100.000%

Path7

Path Summary:

Slack	0.077
Data Arrival Time	1.344
Data Required Time	1.267
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_24_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.041	0.386	tNET	RR	1	R8C73[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_24_s0/CLK
1.221	0.180	tC2Q	RR	1	R8C73[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_24_s0/Q
1.344	0.124	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[24]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.018	0.364	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.267	0.249	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.023
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.386, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.364, 100.000%

Path8

Path Summary:

Slack	0.078
Data Arrival Time	1.350
Data Required Time	1.272
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_18_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.044	0.390	tNET	RR	1	R24C52[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_18_s0/CLK
1.224	0.180	tC2Q	RR	1	R24C52[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_18_s0/Q
1.350	0.126	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[18]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.023	0.369	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA
1.272	0.249	tHld		1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.390, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path9

Path Summary:

Slack	0.078
Data Arrival Time	1.350
Data Required Time	1.272
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_4_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.044	0.390	tNET	RR	1	R24C52[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_4_s0/CLK
1.224	0.180	tC2Q	RR	1	R24C52[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_4_s0/Q
1.350	0.126	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.023	0.369	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA
1.272	0.249	tHld		1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.390, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path10

Path Summary:

Slack	0.106
Data Arrival Time	1.378
Data Required Time	1.272
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_17_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.024	0.370	tNET	RR	1	R27C51[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_17_s0/CLK
1.204	0.180	tC2Q	RR	1	R27C51[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_17_s0/Q
1.378	0.174	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.023	0.369	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA
1.272	0.249	tHld		1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.370, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.174, 49.117%; tC2Q: 0.180, 50.883%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path11

Path Summary:

Slack	0.106
Data Arrival Time	1.378
Data Required Time	1.272
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_15_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.024	0.370	tNET	RR	1	R27C51[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_15_s0/CLK
1.204	0.180	tC2Q	RR	1	R27C51[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_15_s0/Q
1.378	0.174	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[15]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.023	0.369	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA
1.272	0.249	tHld		1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.370, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.174, 49.117%; tC2Q: 0.180, 50.883%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path12

Path Summary:

Slack	0.161
Data Arrival Time	1.433
Data Required Time	1.272
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_30_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.036	0.381	tNET	RR	1	R26C52[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_30_s0/CLK
1.216	0.180	tC2Q	RR	1	R26C52[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_30_s0/Q
1.433	0.217	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[30]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.023	0.369	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA
1.272	0.249	tHld		1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.381, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path13

Path Summary:

Slack	0.162
Data Arrival Time	1.439
Data Required Time	1.277
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_36_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.039	0.385	tNET	RR	1	R24C51[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_36_s0/CLK
1.219	0.180	tC2Q	RR	1	R24C51[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_36_s0/Q
1.439	0.220	tNET	RR	1	BSRAM_R28[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.028	0.374	tNET	RR	1	BSRAM_R28[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA
1.277	0.249	tHld		1	BSRAM_R28[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	-0.011
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.385, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.220, 55.000%; tC2Q: 0.180, 45.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.374, 100.000%

Path14

Path Summary:

Slack	0.171
Data Arrival Time	1.438
Data Required Time	1.267
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_27_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.041	0.386	tNET	RR	1	R8C73[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_27_s0/CLK
1.221	0.180	tC2Q	RR	1	R8C73[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_27_s0/Q
1.438	0.217	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[27]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.018	0.364	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.267	0.249	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.023
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.386, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.364, 100.000%

Path15

Path Summary:

Slack	0.171
Data Arrival Time	1.438
Data Required Time	1.267
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_25_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.041	0.386	tNET	RR	1	R8C73[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_25_s0/CLK
1.221	0.180	tC2Q	RR	1	R8C73[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_25_s0/Q
1.438	0.217	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[25]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.018	0.364	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.267	0.249	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.023
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.386, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.364, 100.000%

Path16

Path Summary:

Slack	0.180
Data Arrival Time	1.457
Data Required Time	1.277
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_59_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.041	0.386	tNET	RR	1	R26C53[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_59_s0/CLK
1.221	0.180	tC2Q	RR	1	R26C53[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_59_s0/Q
1.457	0.236	tNET	RR	1	BSRAM_R28[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[23]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.028	0.374	tNET	RR	1	BSRAM_R28[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA
1.277	0.249	tHld		1	BSRAM_R28[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	-0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.386, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.374, 100.000%

Path17

Path Summary:

Slack	0.180
Data Arrival Time	1.457
Data Required Time	1.277
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_55_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.041	0.386	tNET	RR	1	R26C53[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_55_s0/CLK
1.221	0.180	tC2Q	RR	1	R26C53[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_55_s0/Q
1.457	0.236	tNET	RR	1	BSRAM_R28[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[19]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.028	0.374	tNET	RR	1	BSRAM_R28[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA
1.277	0.249	tHld		1	BSRAM_R28[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	-0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.386, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.374, 100.000%

Path18

Path Summary:

Slack	0.184
Data Arrival Time	1.451
Data Required Time	1.267
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.034	0.380	tNET	RR	1	R9C73[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/CLK
1.214	0.180	tC2Q	RR	1	R9C73[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/Q
1.451	0.236	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[20]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.018	0.364	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.267	0.249	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.016
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.380, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.364, 100.000%

Path19

Path Summary:

Slack	0.184
Data Arrival Time	1.451
Data Required Time	1.267
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.034	0.380	tNET	RR	1	R9C73[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0/CLK
1.214	0.180	tC2Q	RR	1	R9C73[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0/Q
1.451	0.236	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[19]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.018	0.364	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.267	0.249	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.016
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.380, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.364, 100.000%

Path20

Path Summary:

Slack	0.184
Data Arrival Time	1.451
Data Required Time	1.267
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.034	0.380	tNET	RR	1	R9C73[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0/CLK
1.214	0.180	tC2Q	RR	1	R9C73[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0/Q
1.451	0.236	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.018	0.364	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.267	0.249	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.016
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.380, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.364, 100.000%

Path21

Path Summary:

Slack	0.184
Data Arrival Time	1.451
Data Required Time	1.267
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.034	0.380	tNET	RR	1	R9C73[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0/CLK
1.214	0.180	tC2Q	RR	1	R9C73[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0/Q
1.451	0.236	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[16]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.018	0.364	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.267	0.249	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.016
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.380, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.364, 100.000%

Path22

Path Summary:

Slack	0.186
Data Arrival Time	1.458
Data Required Time	1.272
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_1_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.042	0.387	tNET	RR	1	R25C50[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_1_s0/CLK
1.222	0.180	tC2Q	RR	1	R25C50[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_1_s0/Q
1.458	0.236	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.023	0.369	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA
1.272	0.249	tHld		1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.019
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.387, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path23

Path Summary:

Slack	0.188
Data Arrival Time	1.488
Data Required Time	1.300
From	ad9238_12bit_to_16bit/ad_out_11_s1
To	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.070	0.387	tNET	RR	1	R25C42[2][A]	ad9238_12bit_to_16bit/ad_out_11_s1/CLK
1.250	0.180	tC2Q	RR	1	R25C42[2][A]	ad9238_12bit_to_16bit/ad_out_11_s1/Q
1.488	0.239	tNET	RR	1	BSRAM_R28[13]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.051	0.369	tNET	RR	1	BSRAM_R28[13]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s/CLKA
1.300	0.249	tHld		1	BSRAM_R28[13]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s

Path Statistics:

Clock Skew	-0.019
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.387, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.239, 57.015%; tC2Q: 0.180, 42.985%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Path24

Path Summary:

Slack	0.190
Data Arrival Time	1.457
Data Required Time	1.267
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_23_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.041	0.386	tNET	RR	1	R8C73[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_23_s0/CLK
1.221	0.180	tC2Q	RR	1	R8C73[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_23_s0/Q
1.457	0.236	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[23]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.018	0.364	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.267	0.249	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.023
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.386, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.364, 100.000%

Path25

Path Summary:

Slack	0.191
Data Arrival Time	1.463
Data Required Time	1.272
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_22_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.039	0.385	tNET	RR	1	R24C51[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_22_s0/CLK
1.219	0.180	tC2Q	RR	1	R24C51[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_22_s0/Q
1.463	0.244	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[22]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.023	0.369	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA
1.272	0.249	tHld		1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.016
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.385, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.244, 57.522%; tC2Q: 0.180, 42.478%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.369, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.022
Data Arrival Time	3.727
Data Required Time	3.750
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	10	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.182	0.682	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.182	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368	0.186	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.272	0.904	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
4.237	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
3.750	-0.487	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.214
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.186, 17.068%; route: 0.904, 82.932%

Path2

Path Summary:

Slack	0.022
Data Arrival Time	3.727
Data Required Time	3.750
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	10	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.182	0.682	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.182	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368	0.186	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.272	0.904	tNET	FF	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
4.237	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
3.750	-0.487	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.214
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.186, 17.068%; route: 0.904, 82.932%

Path3

Path Summary:

Slack	0.358
Data Arrival Time	3.727
Data Required Time	4.086
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	2	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.182	0.682	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.182	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368	0.186	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.272	0.904	tNET	FF	1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/FCLK
4.237	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
4.086	-0.151	tSu		1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen

Path Statistics:

Clock Skew	0.214
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.186, 17.068%; route: 0.904, 82.932%

Path4

Path Summary:

Slack	0.358
Data Arrival Time	3.727
Data Required Time	4.086
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	2	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.182	0.682	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.182	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368	0.186	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.272	0.904	tNET	FF	1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/FCLK
4.237	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
4.086	-0.151	tSu		1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen

Path Statistics:

Clock Skew	0.214
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.186, 17.068%; route: 0.904, 82.932%

Path5

Path Summary:

Slack	0.358
Data Arrival Time	3.727
Data Required Time	4.086
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	2	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.182	0.682	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.182	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368	0.186	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.272	0.904	tNET	FF	1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/FCLK
4.237	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
4.086	-0.151	tSu		1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen

Path Statistics:

Clock Skew	0.214
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.186, 17.068%; route: 0.904, 82.932%

Path6

Path Summary:

Slack	0.358
Data Arrival Time	3.727
Data Required Time	4.086
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	2	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.182	0.682	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.182	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368	0.186	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.272	0.904	tNET	FF	1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/FCLK
4.237	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
4.086	-0.151	tSu		1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew	0.214
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.186, 17.068%; route: 0.904, 82.932%

Path7

Path Summary:

Slack	0.298
Data Arrival Time	8.824
Data Required Time	9.123
From	fifo_tx/fifo_inst/reset_r_1_s0
To	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
5.534	0.852	tNET	FF	1	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/CLK
5.977	0.442	tC2Q	FF	36	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/Q
8.824	2.848	tNET	FF	16	BSRAM_R10[9]	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.561	0.878	tNET	RR	1	BSRAM_R10[9]	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CLKB
9.123	-0.438	tSu		1	BSRAM_R10[9]	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s

Path Statistics:

Clock Skew	0.026
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.852, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.848, 86.550%; tC2Q: 0.442, 13.450%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.878, 100.000%

Path8

Path Summary:

Slack	0.358
Data Arrival Time	8.824
Data Required Time	9.182
From	fifo_tx/fifo_inst/reset_r_1_s0
To	fifo_tx/fifo_inst/Small.rq1_wptr_0_s5
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
5.534	0.852	tNET	FF	1	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/CLK
5.977	0.442	tC2Q	FF	36	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/Q
8.824	2.848	tNET	FF	1	R14C31[1][A]	fifo_tx/fifo_inst/Small.rq1_wptr_0_s5/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.530	0.848	tNET	RR	1	R14C31[1][A]	fifo_tx/fifo_inst/Small.rq1_wptr_0_s5/CLK
9.182	-0.347	tSu		1	R14C31[1][A]	fifo_tx/fifo_inst/Small.rq1_wptr_0_s5

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.852, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.848, 86.550%; tC2Q: 0.442, 13.450%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.848, 100.000%

Path9

Path Summary:

Slack	0.358
Data Arrival Time	8.812
Data Required Time	9.171
From	fifo_tx/fifo_inst/reset_r_1_s0
To	fifo_tx/fifo_inst/rbin_num_2_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
5.534	0.852	tNET	FF	1	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/CLK
5.977	0.442	tC2Q	FF	36	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/Q
8.812	2.836	tNET	FF	1	R12C31[0][A]	fifo_tx/fifo_inst/rbin_num_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.518	0.836	tNET	RR	1	R12C31[0][A]	fifo_tx/fifo_inst/rbin_num_2_s0/CLK
9.171	-0.347	tSu		1	R12C31[0][A]	fifo_tx/fifo_inst/rbin_num_2_s0

Path Statistics:

Clock Skew	-0.016
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.852, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.836, 86.501%; tC2Q: 0.442, 13.499%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.836, 100.000%

Path10

Path Summary:

Slack	0.358
Data Arrival Time	8.818
Data Required Time	9.177
From	fifo_tx/fifo_inst/reset_r_1_s0
To	fifo_tx/fifo_inst/rbin_num_6_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
5.534	0.852	tNET	FF	1	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/CLK
5.977	0.442	tC2Q	FF	36	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/Q
8.818	2.842	tNET	FF	1	R13C31[1][B]	fifo_tx/fifo_inst/rbin_num_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.524	0.842	tNET	RR	1	R13C31[1][B]	fifo_tx/fifo_inst/rbin_num_6_s0/CLK
9.177	-0.347	tSu		1	R13C31[1][B]	fifo_tx/fifo_inst/rbin_num_6_s0

Path Statistics:

Clock Skew	-0.010
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.852, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.842, 86.526%; tC2Q: 0.442, 13.474%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.842, 100.000%

Path11

Path Summary:

Slack	0.358
Data Arrival Time	8.818
Data Required Time	9.177
From	fifo_tx/fifo_inst/reset_r_1_s0
To	fifo_tx/fifo_inst/rbin_num_7_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
5.534	0.852	tNET	FF	1	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/CLK
5.977	0.442	tC2Q	FF	36	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/Q
8.818	2.842	tNET	FF	1	R13C31[0][A]	fifo_tx/fifo_inst/rbin_num_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.524	0.842	tNET	RR	1	R13C31[0][A]	fifo_tx/fifo_inst/rbin_num_7_s0/CLK
9.177	-0.347	tSu		1	R13C31[0][A]	fifo_tx/fifo_inst/rbin_num_7_s0

Path Statistics:

Clock Skew	-0.010
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.852, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.842, 86.526%; tC2Q: 0.442, 13.474%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.842, 100.000%

Path12

Path Summary:

Slack	0.358
Data Arrival Time	8.818
Data Required Time	9.177
From	fifo_tx/fifo_inst/reset_r_1_s0
To	fifo_tx/fifo_inst/rbin_num_9_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
5.534	0.852	tNET	FF	1	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/CLK
5.977	0.442	tC2Q	FF	36	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/Q
8.818	2.842	tNET	FF	1	R13C31[1][A]	fifo_tx/fifo_inst/rbin_num_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.524	0.842	tNET	RR	1	R13C31[1][A]	fifo_tx/fifo_inst/rbin_num_9_s0/CLK
9.177	-0.347	tSu		1	R13C31[1][A]	fifo_tx/fifo_inst/rbin_num_9_s0

Path Statistics:

Clock Skew	-0.010
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.852, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.842, 86.526%; tC2Q: 0.442, 13.474%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.842, 100.000%

Path13

Path Summary:

Slack	0.358
Data Arrival Time	8.818
Data Required Time	9.177
From	fifo_tx/fifo_inst/reset_r_1_s0
To	fifo_tx/fifo_inst/rbin_num_10_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
5.534	0.852	tNET	FF	1	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/CLK
5.977	0.442	tC2Q	FF	36	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/Q
8.818	2.842	tNET	FF	1	R13C31[0][B]	fifo_tx/fifo_inst/rbin_num_10_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.524	0.842	tNET	RR	1	R13C31[0][B]	fifo_tx/fifo_inst/rbin_num_10_s0/CLK
9.177	-0.347	tSu		1	R13C31[0][B]	fifo_tx/fifo_inst/rbin_num_10_s0

Path Statistics:

Clock Skew	-0.010
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.852, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.842, 86.526%; tC2Q: 0.442, 13.474%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.842, 100.000%

Path14

Path Summary:

Slack	0.358
Data Arrival Time	8.824
Data Required Time	9.182
From	fifo_tx/fifo_inst/reset_r_1_s0
To	fifo_tx/fifo_inst/rbin_num_11_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[F]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
5.534	0.852	tNET	FF	1	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/CLK
5.977	0.442	tC2Q	FF	36	R14C32[1][B]	fifo_tx/fifo_inst/reset_r_1_s0/Q
8.824	2.848	tNET	FF	1	R14C31[0][A]	fifo_tx/fifo_inst/rbin_num_11_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	749	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.530	0.848	tNET	RR	1	R14C31[0][A]	fifo_tx/fifo_inst/rbin_num_11_s0/CLK
9.182	-0.347	tSu		1	R14C31[0][A]	fifo_tx/fifo_inst/rbin_num_11_s0

Path Statistics:

Clock Skew	-0.004
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.852, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.848, 86.550%; tC2Q: 0.442, 13.450%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.848, 100.000%

Path15

Path Summary:

Slack	2.518
Data Arrival Time	3.727
Data Required Time	6.246
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	10	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
5.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
5.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.770	0.906	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
6.735	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
6.246	-0.489	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.211
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.182, 16.734%; route: 0.906, 83.266%

Path16

Path Summary:

Slack	2.518
Data Arrival Time	3.727
Data Required Time	6.246
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	10	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
5.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
5.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.770	0.906	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
6.735	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
6.246	-0.489	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.211
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.182, 16.734%; route: 0.906, 83.266%

Path17

Path Summary:

Slack	2.854
Data Arrival Time	3.727
Data Required Time	6.582
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	2	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
5.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
5.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.770	0.906	tNET	RR	1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/FCLK
6.735	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
6.582	-0.153	tSu		1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen

Path Statistics:

Clock Skew	0.211
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.182, 16.734%; route: 0.906, 83.266%

Path18

Path Summary:

Slack	2.854
Data Arrival Time	3.727
Data Required Time	6.582
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	2	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
5.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
5.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.770	0.906	tNET	RR	1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/FCLK
6.735	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
6.582	-0.153	tSu		1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen

Path Statistics:

Clock Skew	0.211
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.182, 16.734%; route: 0.906, 83.266%

Path19

Path Summary:

Slack	2.854
Data Arrival Time	3.727
Data Required Time	6.582
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	2	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
5.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
5.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.770	0.906	tNET	RR	1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/FCLK
6.735	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
6.582	-0.153	tSu		1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen

Path Statistics:

Clock Skew	0.211
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.182, 16.734%; route: 0.906, 83.266%

Path20

Path Summary:

Slack	2.854
Data Arrival Time	3.727
Data Required Time	6.582
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	2	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
5.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
5.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.864	0.182	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.770	0.906	tNET	RR	1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/FCLK
6.735	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
6.582	-0.153	tSu		1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew	0.211
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.182, 16.734%; route: 0.906, 83.266%

Path21

Path Summary:

Slack	17.300
Data Arrival Time	3.727
Data Required Time	21.027
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	10	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.560	0.906	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/PCLK
21.525	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
21.027	-0.498	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.906, 100.000%

Path22

Path Summary:

Slack	17.300
Data Arrival Time	3.727
Data Required Time	21.027
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	10	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.560	0.906	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/PCLK
21.525	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
21.027	-0.498	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.906, 100.000%

Path23

Path Summary:

Slack	17.645
Data Arrival Time	3.727
Data Required Time	21.372
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	2	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.560	0.906	tNET	RR	1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/PCLK
21.525	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
21.372	-0.153	tSu		1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.906, 100.000%

Path24

Path Summary:

Slack	17.645
Data Arrival Time	3.727
Data Required Time	21.372
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	2	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.560	0.906	tNET	RR	1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/PCLK
21.525	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
21.372	-0.153	tSu		1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.906, 100.000%

Path25

Path Summary:

Slack	17.645
Data Arrival Time	3.727
Data Required Time	21.372
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.558	0.876	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.926	0.368	tC2Q	RF	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.727	1.802	tNET	FF	2	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.560	0.906	tNET	RR	1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/PCLK
21.525	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
21.372	-0.153	tSu		1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.876, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.802, 83.057%; tC2Q: 0.368, 16.943%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.906, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.948
Data Arrival Time	51.486
Data Required Time	52.433
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[F]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
50.654	0.654	tCL	FF	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
51.029	0.375	tNET	FF	1	R33C21[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
51.227	0.198	tC2Q	FR	51	R33C21[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
51.486	0.259	tNET	RR	1	R32C20[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.351	0.675	tINS	RR	199	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.587	1.236	tNET	RR	1	R32C20[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLK
52.622	0.035	tUnc				gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0
52.433	-0.189	tHld		1	R32C20[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0

Path Statistics:

Clock Skew	1.558
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.259, 56.712%; tC2Q: 0.198, 43.288%
Required Clock Path Delay	cell: 1.351, 52.218%; route: 1.236, 47.782%

Path2

Path Summary:

Slack	-0.818
Data Arrival Time	51.611
Data Required Time	52.428
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[F]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
50.654	0.654	tCL	FF	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
51.029	0.375	tNET	FF	1	R33C21[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
51.227	0.198	tC2Q	FR	51	R33C21[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
51.611	0.384	tNET	RR	1	R32C23[0][B]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.351	0.675	tINS	RR	199	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.582	1.231	tNET	RR	1	R32C23[0][B]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK
52.617	0.035	tUnc				gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0
52.428	-0.189	tHld		1	R32C23[0][B]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0

Path Statistics:

Clock Skew	1.553
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.384, 66.021%; tC2Q: 0.198, 33.978%
Required Clock Path Delay	cell: 1.351, 52.319%; route: 1.231, 47.681%

Path3

Path Summary:

Slack	-0.818
Data Arrival Time	51.611
Data Required Time	52.428
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[F]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
50.654	0.654	tCL	FF	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
51.029	0.375	tNET	FF	1	R33C21[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
51.227	0.198	tC2Q	FR	51	R33C21[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
51.611	0.384	tNET	RR	1	R32C23[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.351	0.675	tINS	RR	199	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.582	1.231	tNET	RR	1	R32C23[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLK
52.617	0.035	tUnc				gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0
52.428	-0.189	tHld		1	R32C23[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0

Path Statistics:

Clock Skew	1.553
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.384, 66.021%; tC2Q: 0.198, 33.978%
Required Clock Path Delay	cell: 1.351, 52.319%; route: 1.231, 47.681%

Path4

Path Summary:

Slack	0.451
Data Arrival Time	2.246
Data Required Time	1.795
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838	0.156	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.239	0.401	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.607	0.368	tINS	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
1.607	0.000	tNET	RR	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
1.642	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.795	0.153	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.550
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.524, 56.672%; route: 0.401, 43.328%

Path5

Path Summary:

Slack	0.451
Data Arrival Time	2.246
Data Required Time	1.795
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838	0.156	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.239	0.401	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.607	0.368	tINS	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
1.607	0.000	tNET	RR	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
1.642	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.795	0.153	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.550
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.524, 56.672%; route: 0.401, 43.328%

Path6

Path Summary:

Slack	0.540
Data Arrival Time	2.246
Data Required Time	1.706
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838	0.156	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.239	0.401	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.518	0.279	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.518	0.000	tNET	RR	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TCLK
1.553	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
1.706	0.153	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	0.461
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.435, 52.057%; route: 0.401, 47.943%

Path7

Path Summary:

Slack	0.540
Data Arrival Time	2.246
Data Required Time	1.706
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838	0.156	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.239	0.401	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.518	0.279	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.518	0.000	tNET	RR	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TCLK
1.553	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
1.706	0.153	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	0.461
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.435, 52.057%; route: 0.401, 47.943%

Path8

Path Summary:

Slack	0.540
Data Arrival Time	2.246
Data Required Time	1.706
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838	0.156	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.239	0.401	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.518	0.279	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.518	0.000	tNET	RR	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TCLK
1.553	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
1.706	0.153	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	0.461
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.435, 52.057%; route: 0.401, 47.943%

Path9

Path Summary:

Slack	0.540
Data Arrival Time	2.246
Data Required Time	1.706
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838	0.156	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.239	0.401	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.518	0.279	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.518	0.000	tNET	RR	1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/TCLK
1.553	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
1.706	0.153	tHld		1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew	0.461
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.435, 52.057%; route: 0.401, 47.943%

Path10

Path Summary:

Slack	0.819
Data Arrival Time	2.246
Data Required Time	1.427
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838	0.156	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.239	0.401	tNET	RR	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/FCLK
1.274	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.427	0.153	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.182
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.156, 28.026%; route: 0.401, 71.974%

Path11

Path Summary:

Slack	0.819
Data Arrival Time	2.246
Data Required Time	1.427
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838	0.156	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.239	0.401	tNET	RR	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/FCLK
1.274	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.427	0.153	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.182
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.156, 28.026%; route: 0.401, 71.974%

Path12

Path Summary:

Slack	0.819
Data Arrival Time	2.246
Data Required Time	1.427
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838	0.156	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.239	0.401	tNET	RR	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/FCLK
1.274	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
1.427	0.153	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	0.182
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.156, 28.026%; route: 0.401, 71.974%

Path13

Path Summary:

Slack	0.819
Data Arrival Time	2.246
Data Required Time	1.427
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838	0.156	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.239	0.401	tNET	RR	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/FCLK
1.274	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
1.427	0.153	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	0.182
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.156, 28.026%; route: 0.401, 71.974%

Path14

Path Summary:

Slack	0.819
Data Arrival Time	2.246
Data Required Time	1.427
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838	0.156	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.239	0.401	tNET	RR	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/FCLK
1.274	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
1.427	0.153	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	0.182
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.156, 28.026%; route: 0.401, 71.974%

Path15

Path Summary:

Slack	0.819
Data Arrival Time	2.246
Data Required Time	1.427
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.682	0.682	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.682	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838	0.156	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.239	0.401	tNET	RR	1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/FCLK
1.274	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
1.427	0.153	tHld		1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew	0.182
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.156, 28.026%; route: 0.401, 71.974%

Path16

Path Summary:

Slack	0.998
Data Arrival Time	2.246
Data Required Time	1.248
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.060	0.406	tNET	RR	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/PCLK
1.095	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.248	0.153	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.406, 100.000%

Path17

Path Summary:

Slack	0.998
Data Arrival Time	2.246
Data Required Time	1.248
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.060	0.406	tNET	RR	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/PCLK
1.095	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
1.248	0.153	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.406, 100.000%

Path18

Path Summary:

Slack	1.003
Data Arrival Time	2.246
Data Required Time	1.243
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.055	0.401	tNET	RR	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/PCLK
1.090	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.243	0.153	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.401, 100.000%

Path19

Path Summary:

Slack	1.003
Data Arrival Time	2.246
Data Required Time	1.243
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.055	0.401	tNET	RR	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/PCLK
1.090	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
1.243	0.153	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.401, 100.000%

Path20

Path Summary:

Slack	1.008
Data Arrival Time	2.246
Data Required Time	1.238
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.654	0.654	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.050	0.396	tNET	RR	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/PCLK
1.085	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
1.238	0.153	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	-0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.396, 100.000%

Path21

Path Summary:

Slack	2.919
Data Arrival Time	2.246
Data Required Time	-0.673
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.818	0.682	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.818	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.656	0.162	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.248	0.407	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-0.859	0.389	tINS	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
-0.859	0.000	tNET	FF	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
-0.824	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
-0.673	0.151	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.584
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.551, 57.486%; route: 0.407, 42.514%

Path22

Path Summary:

Slack	2.919
Data Arrival Time	2.246
Data Required Time	-0.673
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.818	0.682	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.818	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.656	0.162	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.248	0.407	tNET	FF	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-0.859	0.389	tINS	FF	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
-0.859	0.000	tNET	FF	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
-0.824	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
-0.673	0.151	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.584
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.551, 57.486%; route: 0.407, 42.514%

Path23

Path Summary:

Slack	3.019
Data Arrival Time	2.246
Data Required Time	-0.773
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.818	0.682	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.818	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.656	0.162	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.248	0.407	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-0.959	0.289	tINS	FF	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-0.959	0.000	tNET	FF	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TCLK
-0.924	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
-0.773	0.151	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	0.484
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.451, 52.533%; route: 0.407, 47.467%

Path24

Path Summary:

Slack	3.019
Data Arrival Time	2.246
Data Required Time	-0.773
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.818	0.682	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.818	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.656	0.162	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.248	0.407	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-0.959	0.289	tINS	FF	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-0.959	0.000	tNET	FF	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TCLK
-0.924	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
-0.773	0.151	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	0.484
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.451, 52.533%; route: 0.407, 47.467%

Path25

Path Summary:

Slack	3.019
Data Arrival Time	2.246
Data Required Time	-0.773
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	548	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.057	0.375	tNET	RR	1	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.237	0.180	tC2Q	RR	2196	R9C50[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.246	1.008	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.818	0.682	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.818	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.656	0.162	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.248	0.407	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-0.959	0.289	tINS	FF	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-0.959	0.000	tNET	FF	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TCLK
-0.924	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
-0.773	0.151	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	0.484
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.008, 84.854%; tC2Q: 0.180, 15.146%
Required Clock Path Delay	cell: 0.451, 52.533%; route: 0.407, 47.467%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.499
Actual Width:	3.499
Required Width:	1.000
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.557	0.875	tNET	FF	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
9.056	0.374	tNET	RR	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

MPW2

MPW Summary:

Slack:	2.499
Actual Width:	3.499
Required Width:	1.000
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.557	0.875	tNET	FF	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
9.056	0.374	tNET	RR	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CLKB

MPW3

MPW Summary:

Slack:	2.501
Actual Width:	3.501
Required Width:	1.000
Type:	High Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
1.561	0.878	tNET	RR	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.062	0.380	tNET	FF	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

MPW4

MPW Summary:

Slack:	2.501
Actual Width:	3.501
Required Width:	1.000
Type:	High Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.682	0.682	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
1.561	0.878	tNET	RR	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.062	0.380	tNET	FF	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CLKB

MPW5

MPW Summary:

Slack:	3.243
Actual Width:	3.493
Required Width:	0.250
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	eth_udp_rx_gmii/reg_gmii_rxd_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.592	0.910	tNET	FF	eth_udp_rx_gmii/reg_gmii_rxd_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
9.086	0.403	tNET	RR	eth_udp_rx_gmii/reg_gmii_rxd_2_s0/CLK

MPW6

MPW Summary:

Slack:	3.243
Actual Width:	3.493
Required Width:	0.250
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	eth_udp_rx_gmii/rx_ip_ttl_7_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.592	0.910	tNET	FF	eth_udp_rx_gmii/rx_ip_ttl_7_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
9.086	0.403	tNET	RR	eth_udp_rx_gmii/rx_ip_ttl_7_s0/CLK

MPW7

MPW Summary:

Slack:	3.243
Actual Width:	3.493
Required Width:	0.250
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	eth_udp_rx_gmii/cnt_data_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.592	0.910	tNET	FF	eth_udp_rx_gmii/cnt_data_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
9.086	0.403	tNET	RR	eth_udp_rx_gmii/cnt_data_0_s0/CLK

MPW8

MPW Summary:

Slack:	3.243
Actual Width:	3.493
Required Width:	0.250
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	eth_udp_rx_gmii/rx_ip_ttl_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.592	0.910	tNET	FF	eth_udp_rx_gmii/rx_ip_ttl_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
9.086	0.403	tNET	RR	eth_udp_rx_gmii/rx_ip_ttl_4_s0/CLK

MPW9

MPW Summary:

Slack:	3.243
Actual Width:	3.493
Required Width:	0.250
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	eth_udp_rx_gmii/cnt_udp_header_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.592	0.910	tNET	FF	eth_udp_rx_gmii/cnt_udp_header_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
9.086	0.403	tNET	RR	eth_udp_rx_gmii/cnt_udp_header_1_s0/CLK

MPW10

MPW Summary:

Slack:	3.243
Actual Width:	3.493
Required Width:	0.250
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	eth_udp_rx_gmii/cnt_udp_header_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.682	0.682	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.592	0.910	tNET	FF	eth_udp_rx_gmii/cnt_udp_header_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.682	0.682	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
9.086	0.403	tNET	RR	eth_udp_rx_gmii/cnt_udp_header_0_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
3297	ddr3_ctrl_2port_4	-0.571	0.924
2196	ui_clk_sync_rst	0.022	1.885
749	gmii_tx_clk	-0.013	0.915
548	ad_clk2_d	-1.463	1.035
389	eye_calib_start_Z	10.570	5.924
251	raddr[3]	10.311	2.243
221	led_d_10[1]	12.121	2.676
199	control0[0]	3.413	2.340
148	dqsts1	16.607	2.400
147	dqs_reg	16.475	2.521

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R10C68	69.44%
R10C69	68.06%
R10C71	65.28%
R10C65	59.72%
R10C70	59.72%
R28C32	58.33%
R28C45	58.33%
R10C61	58.33%
R10C72	58.33%
R10C73	58.33%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command