Timing Messages

Report Title	Timing Analysis Report
Design File	H:\01_gaoyun\01_gao_project\62_acm1030_ddr3_rgmii\impl\gwsynthesis\acm1030_ddr3_rgmii.vg
Physical Constraints File	H:\01_gaoyun\01_gao_project\62_acm1030_ddr3_rgmii\src\acm1030_ddr3_rgmii.cst
Timing Constraint File	---
Version	V1.9.9 Beta-6
Part Number	GW5A-LV25UG324C2/I1
Device	GW5A-25
Device Version	A
Created Time	Mon Mar 04 09:26:14 2024
Legal Announcement	Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.85V -40C C2/I1
Hold Delay Model	Fast 0.95V 100C C2/I1
Numbers of Paths Analyzed	22653
Numbers of Endpoints Analyzed	16194
Numbers of Falling Endpoints	70
Numbers of Setup Violated Endpoints	11
Numbers of Hold Violated Endpoints	4

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Fall	Source	Master	Objects
clk50m	Base	20.000	50.000	10.000			clk50m_ibuf/I
rgmii_rx_clk_i	Base	8.000	125.000	4.000			rgmii_rx_clk_i_ibuf/I
tck_pad_i	Base	50.000	20.000	25.000			gw_gao_inst_0/tck_ibuf/I
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk	Generated	20.000	50.000	10.000	clk50m_ibuf/I	clk50m	Gowin_PLL/PLLA_inst/CLKOUT0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	Generated	5.000	200.000	2.500	clk50m_ibuf/I	clk50m	Gowin_PLL/PLLA_inst/CLKOUT1
eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	Generated	8.000	125.000	4.000	rgmii_rx_clk_i_ibuf/I	rgmii_rx_clk_i	eth_pll/PLLA_inst/CLKOUT0
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	Generated	20.000	50.000	10.000	Gowin_PLL/PLLA_inst/CLKOUT1	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	tck_pad_i	20.000(MHz)	138.562(MHz)	9	TOP
2	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk	50.000(MHz)	111.195(MHz)	8	TOP
3	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	200.000(MHz)	2338.896(MHz)	1	TOP
4	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	125.000(MHz)	133.547(MHz)	8	TOP
5	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	50.000(MHz)	70.147(MHz)	9	TOP

No timing paths to get frequency of clk50m!

No timing paths to get frequency of rgmii_rx_clk_i!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk50m	Setup	0.000	0
clk50m	Hold	0.000	0
rgmii_rx_clk_i	Setup	0.000	0
rgmii_rx_clk_i	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk	Setup	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk	Hold	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	Setup	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	Hold	0.000	0
eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	Setup	0.000	0
eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	Hold	0.000	0
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	Setup	0.000	0
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-0.803	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.477	6.194
2	-0.786	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.456	6.156
3	-0.613	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.470	5.996
4	-0.613	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.470	5.996
5	-0.576	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.470	5.959
6	-0.467	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.456	5.837
7	-0.454	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.470	5.837
8	-0.454	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.470	5.837
9	-0.361	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/stop_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CEN	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	0.713	1.953
10	-0.180	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.240	2.467
11	-0.104	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.487	5.504
12	0.048	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.494	5.360
13	0.512	eth_udp_tx_gmii/curr_state.TX_DATA_s1/Q	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CEB	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	-0.019	7.432
14	0.518	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.240	1.769
15	0.707	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_7_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.491	4.698
16	0.846	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_3_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.497	4.564
17	0.877	eth_udp_tx_gmii/curr_state.TX_DATA_s1/Q	fifo_tx/fifo_inst/Empty_s0/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	-0.032	7.104
18	0.915	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_7_s1/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.489	4.487
19	1.300	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_2_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.504	4.118
20	1.340	eth_udp_tx_gmii/curr_state.TX_DATA_s1/Q	eth_udp_tx_gmii/tx_data_6_s0/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	0.003	6.606
21	1.348	fifo_tx/fifo_inst/Rnum_2_s0/Q	eth_send_ctrl/state_0_s0/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	0.006	6.595
22	1.396	eth_udp_tx_gmii/curr_state.TX_DATA_s1/Q	eth_udp_tx_gmii/tx_data_0_s0/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	-0.012	6.565
23	1.435	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_3_s1/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.474	3.952
24	1.436	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_2_s1/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	-0.474	3.951
25	1.485	fifo_tx/fifo_inst/Rnum_2_s0/Q	eth_send_ctrl/state_1_s0/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	8.000	0.006	6.458

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Clock Skew	Data Delay
1	-0.695	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/Q	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	tck_pad_i:[R]	-1.339	0.680
2	0.061	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_18_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[18]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.021	0.255
3	0.137	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_9_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[9]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.019	0.333
4	0.139	eth_udp_rx_gmii/payload_dat_o_1_s0/Q	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/DI[1]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	0.012	0.341
5	0.145	fifo_rx/fifo_inst/Equal.wbin_2_s0/Q	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/ADA[5]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	0.001	0.246
6	0.147	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_12_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[12]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.026	0.335
7	0.147	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_11_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[11]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.026	0.335
8	0.150	eth_udp_rx_gmii/payload_dat_o_3_s0/Q	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/DI[3]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	0.014	0.350
9	0.153	eth_udp_tx_gmii/gmii_txd_2_s0/Q	gmii_to_rgmii/[2].U_ODDR_dq1/D0	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.002	0.237
10	0.153	eth_udp_tx_gmii/gmii_txd_0_s0/Q	gmii_to_rgmii/[0].U_ODDR_dq1/D0	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.002	0.237
11	0.154	eth_udp_rx_gmii/payload_dat_o_7_s0/Q	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/DI[7]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	0.013	0.356
12	0.155	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/oserdes_d_reg_r_42_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/D4	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	-0.002	0.239
13	0.164	eth_udp_tx_gmii/gmii_txd_6_s0/Q	gmii_to_rgmii/[2].U_ODDR_dq1/D1	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.002	0.237
14	0.164	eth_udp_tx_gmii/gmii_txd_4_s0/Q	gmii_to_rgmii/[0].U_ODDR_dq1/D1	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.002	0.237
15	0.166	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/oserdes_d_reg_r_42_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/D5	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	-0.002	0.239
16	0.168	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12/DI[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.065	0.318
17	0.177	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wbin_2_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s/ADA[4]	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	0.021	0.258
18	0.184	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.064	0.333
19	0.185	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_22_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.018	0.381
20	0.187	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[3]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.061	0.333
21	0.193	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.026	0.381
22	0.193	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_14_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[14]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.026	0.381
23	0.193	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_13_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[13]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.026	0.381
24	0.194	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/ADA[7]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.005	0.291
25	0.195	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_36_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.018	0.391

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.326	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.163	1.882
2	0.326	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.163	1.882
3	0.616	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.163	1.882
4	0.616	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.163	1.882
5	0.616	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.163	1.882
6	0.616	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.163	1.882
7	0.616	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.163	1.882
8	0.616	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.163	1.882
9	0.616	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.163	1.882
10	2.823	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.161	1.882
11	2.823	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.161	1.882
12	3.112	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.161	1.882
13	3.112	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.161	1.882
14	3.112	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.161	1.882
15	3.112	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.161	1.882
16	3.112	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.161	1.882
17	3.112	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.161	1.882
18	17.595	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.058	1.882
19	17.595	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.058	1.882
20	17.885	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.066	1.882
21	17.892	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.058	1.882
22	17.892	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.058	1.882
23	17.892	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.058	1.882
24	17.892	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.058	1.882
25	17.900	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.051	1.882

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-0.859	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[F]	tck_pad_i:[R]	0.000	-1.331	0.356
2	-0.859	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[F]	tck_pad_i:[R]	0.000	-1.331	0.356
3	-0.569	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[F]	tck_pad_i:[R]	0.000	-1.316	0.631
4	0.422	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.458	1.047
5	0.422	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.458	1.047
6	0.498	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.381	1.047
7	0.498	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.381	1.047
8	0.498	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.381	1.047
9	0.498	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.381	1.047
10	0.739	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.141	1.047
11	0.739	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.141	1.047
12	0.739	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.141	1.047
13	0.739	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.141	1.047
14	0.739	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.141	1.047
15	0.739	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.141	1.047
16	0.932	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.052	1.047
17	0.932	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.052	1.047
18	0.936	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.056	1.047
19	0.936	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.056	1.047
20	0.940	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.060	1.047
21	2.895	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-0.487	1.047
22	2.895	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-0.487	1.047
23	2.981	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-0.401	1.047
24	2.981	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-0.401	1.047
25	2.981	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-0.401	1.047

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.737	3.599	0.862	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s
2	2.739	3.601	0.862	High Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s
3	2.741	3.603	0.862	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s
4	2.742	3.604	0.862	High Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s
5	3.395	3.595	0.200	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	eth_udp_rx_gmii/rx_data_dly1_5_s0
6	3.395	3.595	0.200	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	eth_udp_rx_gmii/rx_src_ip_17_s0
7	3.395	3.595	0.200	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	eth_udp_rx_gmii/cnt_drp_data_4_s0
8	3.395	3.595	0.200	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	eth_udp_rx_gmii/cnt_drp_data_0_s0
9	3.395	3.595	0.200	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	eth_udp_rx_gmii/rx_src_ip_16_s0
10	3.395	3.595	0.200	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	eth_udp_rx_gmii/rx_dst_ip_25_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.803
Data Arrival Time	21.938
Data Required Time	21.135
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
19.640	2.809	tNET	RR	2	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.034	0.394	tINS	RR	1	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.034	0.000	tNET	RR	2	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.074	0.040	tINS	RR	1	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.074	0.000	tNET	RR	2	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.114	0.040	tINS	RR	1	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.114	0.000	tNET	RR	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.154	0.040	tINS	RF	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
20.357	0.203	tNET	FF	1	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
20.774	0.417	tINS	FR	9	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
21.517	0.743	tNET	RR	1	R11C49[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/I2
21.938	0.421	tINS	RR	1	R11C49[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/F
21.938	0.000	tNET	RR	1	R11C49[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.221	0.697	tNET	RR	1	R11C49[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/CLK
21.186	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0
21.135	-0.051	tSu		1	R11C49[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0

Path Statistics:

Clock Skew	0.477
Setup Relationship	5.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.702, 27.476%; route: 3.755, 60.619%; tC2Q: 0.738, 11.906%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.697, 100.000%

Path2

Path Summary:

Slack	-0.786
Data Arrival Time	21.900
Data Required Time	21.114
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
19.640	2.809	tNET	RR	2	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.034	0.394	tINS	RR	1	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.034	0.000	tNET	RR	2	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.074	0.040	tINS	RR	1	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.074	0.000	tNET	RR	2	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.114	0.040	tINS	RR	1	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.114	0.000	tNET	RR	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.154	0.040	tINS	RF	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
20.357	0.203	tNET	FF	1	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
20.774	0.417	tINS	FR	9	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
21.479	0.705	tNET	RR	1	R12C48[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n213_s0/I2
21.900	0.421	tINS	RR	1	R12C48[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n213_s0/F
21.900	0.000	tNET	RR	1	R12C48[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.200	0.676	tNET	RR	1	R12C48[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0/CLK
21.165	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0
21.114	-0.051	tSu		1	R12C48[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0

Path Statistics:

Clock Skew	0.456
Setup Relationship	5.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.702, 27.645%; route: 3.717, 60.375%; tC2Q: 0.738, 11.979%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.676, 100.000%

Path3

Path Summary:

Slack	-0.613
Data Arrival Time	21.740
Data Required Time	21.127
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
19.640	2.809	tNET	RR	2	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.034	0.394	tINS	RR	1	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.034	0.000	tNET	RR	2	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.074	0.040	tINS	RR	1	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.074	0.000	tNET	RR	2	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.114	0.040	tINS	RR	1	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.114	0.000	tNET	RR	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.154	0.040	tINS	RF	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
20.357	0.203	tNET	FF	1	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
20.774	0.417	tINS	FR	9	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
21.371	0.597	tNET	RR	1	R11C48[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/I2
21.740	0.369	tINS	RR	1	R11C48[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/F
21.740	0.000	tNET	RR	1	R11C48[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.213	0.689	tNET	RR	1	R11C48[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/CLK
21.178	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0
21.127	-0.051	tSu		1	R11C48[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0

Path Statistics:

Clock Skew	0.470
Setup Relationship	5.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.650, 27.516%; route: 3.609, 60.185%; tC2Q: 0.738, 12.299%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.689, 100.000%

Path4

Path Summary:

Slack	-0.613
Data Arrival Time	21.740
Data Required Time	21.127
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
19.640	2.809	tNET	RR	2	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.034	0.394	tINS	RR	1	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.034	0.000	tNET	RR	2	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.074	0.040	tINS	RR	1	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.074	0.000	tNET	RR	2	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.114	0.040	tINS	RR	1	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.114	0.000	tNET	RR	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.154	0.040	tINS	RF	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
20.357	0.203	tNET	FF	1	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
20.774	0.417	tINS	FR	9	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
21.371	0.597	tNET	RR	1	R11C48[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n214_s0/I2
21.740	0.369	tINS	RR	1	R11C48[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n214_s0/F
21.740	0.000	tNET	RR	1	R11C48[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.213	0.689	tNET	RR	1	R11C48[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0/CLK
21.178	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0
21.127	-0.051	tSu		1	R11C48[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0

Path Statistics:

Clock Skew	0.470
Setup Relationship	5.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.650, 27.516%; route: 3.609, 60.185%; tC2Q: 0.738, 12.299%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.689, 100.000%

Path5

Path Summary:

Slack	-0.576
Data Arrival Time	21.703
Data Required Time	21.127
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
19.640	2.809	tNET	RR	2	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.034	0.394	tINS	RR	1	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.034	0.000	tNET	RR	2	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.074	0.040	tINS	RR	1	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.074	0.000	tNET	RR	2	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.114	0.040	tINS	RR	1	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.114	0.000	tNET	RR	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.154	0.040	tINS	RF	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
20.357	0.203	tNET	FF	1	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
20.774	0.417	tINS	FR	9	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
21.371	0.597	tNET	RR	1	R11C48[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n217_s0/I2
21.703	0.332	tINS	RR	1	R11C48[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n217_s0/F
21.703	0.000	tNET	RR	1	R11C48[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.213	0.689	tNET	RR	1	R11C48[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/CLK
21.178	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0
21.127	-0.051	tSu		1	R11C48[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0

Path Statistics:

Clock Skew	0.470
Setup Relationship	5.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.613, 27.066%; route: 3.609, 60.559%; tC2Q: 0.738, 12.375%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.689, 100.000%

Path6

Path Summary:

Slack	-0.467
Data Arrival Time	21.581
Data Required Time	21.114
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
19.640	2.809	tNET	RR	2	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.034	0.394	tINS	RR	1	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.034	0.000	tNET	RR	2	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.074	0.040	tINS	RR	1	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.074	0.000	tNET	RR	2	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.114	0.040	tINS	RR	1	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.114	0.000	tNET	RR	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.154	0.040	tINS	RF	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
20.357	0.203	tNET	FF	1	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
20.774	0.417	tINS	FR	9	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
21.371	0.597	tNET	RR	1	R12C48[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n216_s0/I2
21.581	0.210	tINS	RR	1	R12C48[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n216_s0/F
21.581	0.000	tNET	RR	1	R12C48[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.200	0.676	tNET	RR	1	R12C48[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/CLK
21.165	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0
21.114	-0.051	tSu		1	R12C48[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0

Path Statistics:

Clock Skew	0.456
Setup Relationship	5.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.491, 25.541%; route: 3.609, 61.825%; tC2Q: 0.738, 12.634%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.676, 100.000%

Path7

Path Summary:

Slack	-0.454
Data Arrival Time	21.581
Data Required Time	21.127
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
19.640	2.809	tNET	RR	2	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.034	0.394	tINS	RR	1	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.034	0.000	tNET	RR	2	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.074	0.040	tINS	RR	1	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.074	0.000	tNET	RR	2	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.114	0.040	tINS	RR	1	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.114	0.000	tNET	RR	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.154	0.040	tINS	RF	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
20.357	0.203	tNET	FF	1	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
20.774	0.417	tINS	FR	9	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
21.371	0.597	tNET	RR	1	R11C48[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n218_s0/I2
21.581	0.210	tINS	RR	1	R11C48[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n218_s0/F
21.581	0.000	tNET	RR	1	R11C48[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.213	0.689	tNET	RR	1	R11C48[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/CLK
21.178	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0
21.127	-0.051	tSu		1	R11C48[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0

Path Statistics:

Clock Skew	0.470
Setup Relationship	5.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.491, 25.541%; route: 3.609, 61.825%; tC2Q: 0.738, 12.634%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.689, 100.000%

Path8

Path Summary:

Slack	-0.454
Data Arrival Time	21.581
Data Required Time	21.127
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
19.640	2.809	tNET	RR	2	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.034	0.394	tINS	RR	1	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.034	0.000	tNET	RR	2	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.074	0.040	tINS	RR	1	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.074	0.000	tNET	RR	2	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.114	0.040	tINS	RR	1	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.114	0.000	tNET	RR	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.154	0.040	tINS	RF	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
20.357	0.203	tNET	FF	1	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
20.774	0.417	tINS	FR	9	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
21.371	0.597	tNET	RR	1	R11C48[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n215_s0/I2
21.581	0.210	tINS	RR	1	R11C48[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n215_s0/F
21.581	0.000	tNET	RR	1	R11C48[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.213	0.689	tNET	RR	1	R11C48[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0/CLK
21.178	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0
21.127	-0.051	tSu		1	R11C48[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0

Path Statistics:

Clock Skew	0.470
Setup Relationship	5.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.491, 25.541%; route: 3.609, 61.825%; tC2Q: 0.738, 12.634%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.689, 100.000%

Path9

Path Summary:

Slack	-0.361
Data Arrival Time	3.252
Data Required Time	2.891
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/stop_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.299	0.713	tNET	RR	1	R3C45[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/stop_reg_2_s0/CLK
1.593	0.294	tC2Q	RF	1	R3C45[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/stop_reg_2_s0/Q
3.252	1.659	tNET	FF	1	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CEN

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.086	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.086	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.051	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen
2.891	-0.160	tSu		1	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen

Path Statistics:

Clock Skew	-0.713
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.659, 84.946%; tC2Q: 0.294, 15.054%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack	-0.180
Data Arrival Time	3.697
Data Required Time	3.518
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.230	0.707	tNET	RR	1	R8C52[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/CLK
1.536	0.306	tC2Q	RR	2	R8C52[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/Q
1.816	0.280	tNET	RR	1	R7C53[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I1
2.229	0.413	tINS	RR	1	R7C53[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F
3.697	1.468	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.086	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.086	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.247	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.970	0.723	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
3.935	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
3.518	-0.417	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.240
Setup Relationship	2.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.707, 100.000%
Arrival Data Path Delay	cell: 0.413, 16.741%; route: 1.748, 70.855%; tC2Q: 0.306, 12.404%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path11

Path Summary:

Slack	-0.104
Data Arrival Time	21.248
Data Required Time	21.144
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
19.640	2.809	tNET	RR	2	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/I1
20.034	0.394	tINS	RR	1	R8C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
20.034	0.000	tNET	RR	2	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
20.074	0.040	tINS	RR	1	R8C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
20.074	0.000	tNET	RR	2	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
20.114	0.040	tINS	RR	1	R8C47[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
20.114	0.000	tNET	RR	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
20.154	0.040	tINS	RF	2	R8C48[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
20.357	0.203	tNET	FF	1	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
20.774	0.417	tINS	FR	9	R8C48[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
21.248	0.474	tNET	RR	1	R8C50[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.230	0.707	tNET	RR	1	R8C50[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0/CLK
21.195	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0
21.144	-0.051	tSu		1	R8C50[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0

Path Statistics:

Clock Skew	0.487
Setup Relationship	5.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.281, 23.271%; route: 3.486, 63.330%; tC2Q: 0.738, 13.398%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.707, 100.000%

Path12

Path Summary:

Slack	0.048
Data Arrival Time	21.104
Data Required Time	21.152
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
19.902	3.071	tNET	RR	2	R8C49[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n245_s19/I0
20.347	0.445	tINS	RF	1	R8C49[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n245_s19/COUT
20.347	0.000	tNET	FF	2	R8C49[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n245_s20/CIN
20.387	0.040	tINS	FR	1	R8C49[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n245_s20/COUT
20.387	0.000	tNET	RR	2	R8C49[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n245_s21/CIN
20.427	0.040	tINS	RR	1	R8C49[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n245_s21/COUT
20.427	0.000	tNET	RR	2	R8C49[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n245_s22/CIN
20.467	0.040	tINS	RR	1	R8C49[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n245_s22/COUT
20.467	0.000	tNET	RR	2	R8C49[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n245_s23/CIN
20.507	0.040	tINS	RF	1	R8C49[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n245_s23/COUT
20.706	0.199	tNET	FF	1	R8C49[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s2/I0
21.104	0.398	tINS	FR	1	R8C49[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s2/F
21.104	0.000	tNET	RR	1	R8C49[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.238	0.714	tNET	RR	1	R8C49[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0/CLK
21.203	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0
21.152	-0.051	tSu		1	R8C49[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0

Path Statistics:

Clock Skew	0.494
Setup Relationship	5.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.353, 25.240%; route: 3.270, 61.002%; tC2Q: 0.738, 13.758%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.714, 100.000%

Path13

Path Summary:

Slack	0.512
Data Arrival Time	8.695
Data Required Time	9.207
From	eth_udp_tx_gmii/curr_state.TX_DATA_s1
To	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.263	0.676	tNET	RR	1	R30C24[1][A]	eth_udp_tx_gmii/curr_state.TX_DATA_s1/CLK
1.569	0.306	tC2Q	RR	33	R30C24[1][A]	eth_udp_tx_gmii/curr_state.TX_DATA_s1/Q
3.553	1.984	tNET	RR	1	R9C25[3][B]	fifo_tx/fifo_inst/rbin_num_next_2_s6/I1
3.951	0.398	tINS	RR	7	R9C25[3][B]	fifo_tx/fifo_inst/rbin_num_next_2_s6/F
4.237	0.286	tNET	RR	1	R9C22[0][A]	fifo_tx/fifo_inst/rbin_num_next_5_s6/I3
4.658	0.421	tINS	RR	8	R9C22[0][A]	fifo_tx/fifo_inst/rbin_num_next_5_s6/F
4.951	0.293	tNET	RR	1	R8C23[2][A]	fifo_tx/fifo_inst/Small.rgraynext_6_s2/I1
5.161	0.210	tINS	RR	3	R8C23[2][A]	fifo_tx/fifo_inst/Small.rgraynext_6_s2/F
5.724	0.563	tNET	RR	1	R11C23[3][A]	fifo_tx/fifo_inst/Small.rgraynext_6_s0/I2
6.141	0.417	tINS	RR	2	R11C23[3][A]	fifo_tx/fifo_inst/Small.rgraynext_6_s0/F
6.405	0.264	tNET	RR	2	R11C21[0][A]	fifo_tx/fifo_inst/n289_s0/I0
6.850	0.445	tINS	RF	1	R11C21[0][A]	fifo_tx/fifo_inst/n289_s0/COUT
6.850	0.000	tNET	FF	2	R11C21[0][B]	fifo_tx/fifo_inst/n290_s0/CIN
6.890	0.040	tINS	FR	1	R11C21[0][B]	fifo_tx/fifo_inst/n290_s0/COUT
6.890	0.000	tNET	RR	2	R11C21[1][A]	fifo_tx/fifo_inst/n291_s0/CIN
6.930	0.040	tINS	RR	1	R11C21[1][A]	fifo_tx/fifo_inst/n291_s0/COUT
6.930	0.000	tNET	RR	2	R11C21[1][B]	fifo_tx/fifo_inst/n292_s0/CIN
6.970	0.040	tINS	RR	1	R11C21[1][B]	fifo_tx/fifo_inst/n292_s0/COUT
6.970	0.000	tNET	RR	2	R11C21[2][A]	fifo_tx/fifo_inst/n293_s0/CIN
7.010	0.040	tINS	RR	2	R11C21[2][A]	fifo_tx/fifo_inst/n293_s0/COUT
7.946	0.936	tNET	RR	1	R9C24[1][B]	fifo_tx/fifo_inst/n36_s1/I2
8.367	0.421	tINS	RR	1	R9C24[1][B]	fifo_tx/fifo_inst/n36_s1/F
8.695	0.328	tNET	RR	1	BSRAM_R10[6]	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CEB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.282	0.695	tNET	RR	1	BSRAM_R10[6]	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CLKB
9.207	-0.075	tSu		1	BSRAM_R10[6]	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s

Path Statistics:

Clock Skew	0.019
Setup Relationship	8.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay	cell: 2.472, 33.262%; route: 4.654, 62.621%; tC2Q: 0.306, 4.117%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.695, 100.000%

Path14

Path Summary:

Slack	0.518
Data Arrival Time	2.999
Data Required Time	3.518
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.230	0.707	tNET	RR	1	R8C52[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/CLK
1.536	0.306	tC2Q	RR	2	R8C52[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/Q
1.816	0.280	tNET	RR	1	R7C53[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I1
2.237	0.421	tINS	RR	1	R7C53[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F
2.999	0.762	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.086	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.086	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.247	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.970	0.723	tNET	FF	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
3.935	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
3.518	-0.417	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.240
Setup Relationship	2.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.707, 100.000%
Arrival Data Path Delay	cell: 0.421, 23.799%; route: 1.042, 58.903%; tC2Q: 0.306, 17.298%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path15

Path Summary:

Slack	0.707
Data Arrival Time	20.442
Data Required Time	21.149
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_7_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	9	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[7]
20.442	3.611	tNET	RR	1	R4C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.235	0.711	tNET	RR	1	R4C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_7_s0/CLK
21.200	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_7_s0
21.149	-0.051	tSu		1	R4C47[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_7_s0

Path Statistics:

Clock Skew	0.491
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.350, 7.449%; route: 3.611, 76.855%; tC2Q: 0.738, 15.697%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.711, 100.000%

Path16

Path Summary:

Slack	0.846
Data Arrival Time	20.308
Data Required Time	21.154
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_3_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
20.308	3.477	tNET	RR	1	R5C48[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.240	0.717	tNET	RR	1	R5C48[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_3_s0/CLK
21.205	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_3_s0
21.154	-0.051	tSu		1	R5C48[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_3_s0

Path Statistics:

Clock Skew	0.497
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.350, 7.667%; route: 3.477, 76.175%; tC2Q: 0.738, 16.157%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.717, 100.000%

Path17

Path Summary:

Slack	0.877
Data Arrival Time	8.367
Data Required Time	9.244
From	eth_udp_tx_gmii/curr_state.TX_DATA_s1
To	fifo_tx/fifo_inst/Empty_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.263	0.676	tNET	RR	1	R30C24[1][A]	eth_udp_tx_gmii/curr_state.TX_DATA_s1/CLK
1.569	0.306	tC2Q	RR	33	R30C24[1][A]	eth_udp_tx_gmii/curr_state.TX_DATA_s1/Q
3.553	1.984	tNET	RR	1	R9C25[3][B]	fifo_tx/fifo_inst/rbin_num_next_2_s6/I1
3.951	0.398	tINS	RR	7	R9C25[3][B]	fifo_tx/fifo_inst/rbin_num_next_2_s6/F
4.237	0.286	tNET	RR	1	R9C22[0][A]	fifo_tx/fifo_inst/rbin_num_next_5_s6/I3
4.658	0.421	tINS	RR	8	R9C22[0][A]	fifo_tx/fifo_inst/rbin_num_next_5_s6/F
4.951	0.293	tNET	RR	1	R8C23[2][A]	fifo_tx/fifo_inst/Small.rgraynext_6_s2/I1
5.161	0.210	tINS	RR	3	R8C23[2][A]	fifo_tx/fifo_inst/Small.rgraynext_6_s2/F
5.724	0.563	tNET	RR	1	R11C23[3][A]	fifo_tx/fifo_inst/Small.rgraynext_6_s0/I2
6.141	0.417	tINS	RR	2	R11C23[3][A]	fifo_tx/fifo_inst/Small.rgraynext_6_s0/F
6.405	0.264	tNET	RR	2	R11C21[0][A]	fifo_tx/fifo_inst/n289_s0/I0
6.850	0.445	tINS	RF	1	R11C21[0][A]	fifo_tx/fifo_inst/n289_s0/COUT
6.850	0.000	tNET	FF	2	R11C21[0][B]	fifo_tx/fifo_inst/n290_s0/CIN
6.890	0.040	tINS	FR	1	R11C21[0][B]	fifo_tx/fifo_inst/n290_s0/COUT
6.890	0.000	tNET	RR	2	R11C21[1][A]	fifo_tx/fifo_inst/n291_s0/CIN
6.930	0.040	tINS	RR	1	R11C21[1][A]	fifo_tx/fifo_inst/n291_s0/COUT
6.930	0.000	tNET	RR	2	R11C21[1][B]	fifo_tx/fifo_inst/n292_s0/CIN
6.970	0.040	tINS	RR	1	R11C21[1][B]	fifo_tx/fifo_inst/n292_s0/COUT
6.970	0.000	tNET	RR	2	R11C21[2][A]	fifo_tx/fifo_inst/n293_s0/CIN
7.010	0.040	tINS	RR	2	R11C21[2][A]	fifo_tx/fifo_inst/n293_s0/COUT
7.946	0.936	tNET	RR	1	R9C25[0][B]	fifo_tx/fifo_inst/rempty_val_s1/I0
8.367	0.421	tINS	RR	1	R9C25[0][B]	fifo_tx/fifo_inst/rempty_val_s1/F
8.367	0.000	tNET	RR	1	R9C25[0][B]	fifo_tx/fifo_inst/Empty_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.295	0.709	tNET	RR	1	R9C25[0][B]	fifo_tx/fifo_inst/Empty_s0/CLK
9.244	-0.051	tSu		1	R9C25[0][B]	fifo_tx/fifo_inst/Empty_s0

Path Statistics:

Clock Skew	0.032
Setup Relationship	8.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay	cell: 2.472, 34.797%; route: 4.326, 60.895%; tC2Q: 0.306, 4.307%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.709, 100.000%

Path18

Path Summary:

Slack	0.915
Data Arrival Time	20.231
Data Required Time	21.146
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_7_s1
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	9	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[7]
19.810	2.979	tNET	RR	1	R9C49[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n147_s0/I1
20.231	0.421	tINS	RR	1	R9C49[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n147_s0/F
20.231	0.000	tNET	RR	1	R9C49[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.232	0.709	tNET	RR	1	R9C49[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_7_s1/CLK
21.197	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_7_s1
21.146	-0.051	tSu		1	R9C49[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_7_s1

Path Statistics:

Clock Skew	0.489
Setup Relationship	5.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.771, 17.181%; route: 2.979, 66.385%; tC2Q: 0.738, 16.435%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.709, 100.000%

Path19

Path Summary:

Slack	1.300
Data Arrival Time	19.862
Data Required Time	21.161
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_2_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
19.862	3.031	tNET	RR	1	R5C49[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.247	0.724	tNET	RR	1	R5C49[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_2_s0/CLK
21.212	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_2_s0
21.161	-0.051	tSu		1	R5C49[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_2_s0

Path Statistics:

Clock Skew	0.504
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.350, 8.498%; route: 3.031, 73.595%; tC2Q: 0.738, 17.907%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%

Path20

Path Summary:

Slack	1.340
Data Arrival Time	7.869
Data Required Time	9.209
From	eth_udp_tx_gmii/curr_state.TX_DATA_s1
To	eth_udp_tx_gmii/tx_data_6_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.263	0.676	tNET	RR	1	R30C24[1][A]	eth_udp_tx_gmii/curr_state.TX_DATA_s1/CLK
1.569	0.306	tC2Q	RR	33	R30C24[1][A]	eth_udp_tx_gmii/curr_state.TX_DATA_s1/Q
3.441	1.872	tNET	RR	1	R9C25[1][B]	fifo_tx/fifo_inst/n200_s2/I3
3.854	0.413	tINS	RR	8	R9C25[1][B]	fifo_tx/fifo_inst/n200_s2/F
4.561	0.707	tNET	RR	1	R11C24[1][B]	fifo_tx/fifo_inst/n201_s0/I2
4.982	0.421	tINS	RR	1	R11C24[1][B]	fifo_tx/fifo_inst/n201_s0/F
6.414	1.432	tNET	RR	1	R32C24[2][B]	eth_udp_tx_gmii/n934_s13/I0
6.827	0.413	tINS	RR	1	R32C24[2][B]	eth_udp_tx_gmii/n934_s13/F
6.953	0.126	tNET	RR	1	R32C23[2][B]	eth_udp_tx_gmii/n934_s10/I3
7.322	0.369	tINS	RR	1	R32C23[2][B]	eth_udp_tx_gmii/n934_s10/F
7.448	0.126	tNET	RR	1	R31C23[0][B]	eth_udp_tx_gmii/n934_s7/I3
7.869	0.421	tINS	RR	1	R31C23[0][B]	eth_udp_tx_gmii/n934_s7/F
7.869	0.000	tNET	RR	1	R31C23[0][B]	eth_udp_tx_gmii/tx_data_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.260	0.674	tNET	RR	1	R31C23[0][B]	eth_udp_tx_gmii/tx_data_6_s0/CLK
9.209	-0.051	tSu		1	R31C23[0][B]	eth_udp_tx_gmii/tx_data_6_s0

Path Statistics:

Clock Skew	-0.003
Setup Relationship	8.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay	cell: 2.037, 30.836%; route: 4.263, 64.532%; tC2Q: 0.306, 4.632%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.674, 100.000%

Path21

Path Summary:

Slack	1.348
Data Arrival Time	7.888
Data Required Time	9.236
From	fifo_tx/fifo_inst/Rnum_2_s0
To	eth_send_ctrl/state_0_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.293	0.707	tNET	RR	1	R8C22[0][B]	fifo_tx/fifo_inst/Rnum_2_s0/CLK
1.599	0.306	tC2Q	RR	2	R8C22[0][B]	fifo_tx/fifo_inst/Rnum_2_s0/Q
3.592	1.993	tNET	RR	1	R33C28[2][A]	eth_send_ctrl/n426_s42/I2
4.013	0.421	tINS	RR	1	R33C28[2][A]	eth_send_ctrl/n426_s42/F
4.015	0.002	tNET	RR	1	R33C28[2][B]	eth_send_ctrl/n426_s38/I0
4.384	0.369	tINS	RR	1	R33C28[2][B]	eth_send_ctrl/n426_s38/F
4.386	0.002	tNET	RR	1	R33C28[3][B]	eth_send_ctrl/n426_s31/I1
4.784	0.398	tINS	RR	2	R33C28[3][B]	eth_send_ctrl/n426_s31/F
5.202	0.418	tNET	RR	1	R34C30[3][A]	eth_send_ctrl/n426_s24/I0
5.600	0.398	tINS	RR	2	R34C30[3][A]	eth_send_ctrl/n426_s24/F
5.604	0.004	tNET	RR	1	R34C30[2][B]	eth_send_ctrl/n426_s15/I1
5.973	0.369	tINS	RR	3	R34C30[2][B]	eth_send_ctrl/n426_s15/F
6.313	0.340	tNET	RR	1	R33C28[1][A]	eth_send_ctrl/n426_s12/I0
6.734	0.421	tINS	RR	1	R33C28[1][A]	eth_send_ctrl/n426_s12/F
6.860	0.126	tNET	RR	1	R34C28[2][B]	eth_send_ctrl/n426_s9/I1
7.070	0.210	tINS	RR	3	R34C28[2][B]	eth_send_ctrl/n426_s9/F
7.490	0.420	tNET	RR	1	R35C29[3][A]	eth_send_ctrl/n427_s9/I3
7.888	0.398	tINS	RR	1	R35C29[3][A]	eth_send_ctrl/n427_s9/F
7.888	0.000	tNET	RR	1	R35C29[3][A]	eth_send_ctrl/state_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.287	0.701	tNET	RR	1	R35C29[3][A]	eth_send_ctrl/state_0_s0/CLK
9.236	-0.051	tSu		1	R35C29[3][A]	eth_send_ctrl/state_0_s0

Path Statistics:

Clock Skew	-0.006
Setup Relationship	8.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.707, 100.000%
Arrival Data Path Delay	cell: 2.984, 45.246%; route: 3.305, 50.114%; tC2Q: 0.306, 4.640%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%

Path22

Path Summary:

Slack	1.396
Data Arrival Time	7.828
Data Required Time	9.224
From	eth_udp_tx_gmii/curr_state.TX_DATA_s1
To	eth_udp_tx_gmii/tx_data_0_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.263	0.676	tNET	RR	1	R30C24[1][A]	eth_udp_tx_gmii/curr_state.TX_DATA_s1/CLK
1.569	0.306	tC2Q	RR	33	R30C24[1][A]	eth_udp_tx_gmii/curr_state.TX_DATA_s1/Q
3.441	1.872	tNET	RR	1	R9C25[1][B]	fifo_tx/fifo_inst/n200_s2/I3
3.854	0.413	tINS	RR	8	R9C25[1][B]	fifo_tx/fifo_inst/n200_s2/F
4.453	0.599	tNET	RR	1	R11C24[1][A]	fifo_tx/fifo_inst/n207_s0/I2
4.866	0.413	tINS	RR	1	R11C24[1][A]	fifo_tx/fifo_inst/n207_s0/F
6.373	1.507	tNET	RR	1	R31C21[1][A]	eth_udp_tx_gmii/n946_s13/I0
6.742	0.369	tINS	RR	1	R31C21[1][A]	eth_udp_tx_gmii/n946_s13/F
6.868	0.126	tNET	RR	1	R31C20[2][B]	eth_udp_tx_gmii/n946_s9/I3
7.281	0.413	tINS	RR	1	R31C20[2][B]	eth_udp_tx_gmii/n946_s9/F
7.407	0.126	tNET	RR	1	R31C21[0][A]	eth_udp_tx_gmii/n946_s7/I3
7.828	0.421	tINS	RR	1	R31C21[0][A]	eth_udp_tx_gmii/n946_s7/F
7.828	0.000	tNET	RR	1	R31C21[0][A]	eth_udp_tx_gmii/tx_data_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.275	0.688	tNET	RR	1	R31C21[0][A]	eth_udp_tx_gmii/tx_data_0_s0/CLK
9.224	-0.051	tSu		1	R31C21[0][A]	eth_udp_tx_gmii/tx_data_0_s0

Path Statistics:

Clock Skew	0.012
Setup Relationship	8.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay	cell: 2.029, 30.906%; route: 4.230, 64.433%; tC2Q: 0.306, 4.661%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.688, 100.000%

Path23

Path Summary:

Slack	1.435
Data Arrival Time	19.696
Data Required Time	21.131
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_3_s1
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
19.486	2.655	tNET	RR	1	R9C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n151_s0/I0
19.696	0.210	tINS	RR	1	R9C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n151_s0/F
19.696	0.000	tNET	RR	1	R9C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.217	0.693	tNET	RR	1	R9C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_3_s1/CLK
21.182	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_3_s1
21.131	-0.051	tSu		1	R9C47[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_3_s1

Path Statistics:

Clock Skew	0.474
Setup Relationship	5.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.560, 14.168%; route: 2.655, 67.173%; tC2Q: 0.738, 18.659%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.693, 100.000%

Path24

Path Summary:

Slack	1.436
Data Arrival Time	19.695
Data Required Time	21.131
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_2_s1
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
15.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
15.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.481	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.831	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
19.485	2.654	tNET	RR	1	R9C47[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n152_s0/I0
19.695	0.210	tINS	RR	1	R9C47[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n152_s0/F
19.695	0.000	tNET	RR	1	R9C47[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.217	0.693	tNET	RR	1	R9C47[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_2_s1/CLK
21.182	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_2_s1
21.131	-0.051	tSu		1	R9C47[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_2_s1

Path Statistics:

Clock Skew	0.474
Setup Relationship	5.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.560, 14.171%; route: 2.654, 67.165%; tC2Q: 0.738, 18.664%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.693, 100.000%

Path25

Path Summary:

Slack	1.485
Data Arrival Time	7.751
Data Required Time	9.236
From	fifo_tx/fifo_inst/Rnum_2_s0
To	eth_send_ctrl/state_1_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
1.293	0.707	tNET	RR	1	R8C22[0][B]	fifo_tx/fifo_inst/Rnum_2_s0/CLK
1.599	0.306	tC2Q	RR	2	R8C22[0][B]	fifo_tx/fifo_inst/Rnum_2_s0/Q
3.592	1.993	tNET	RR	1	R33C28[2][A]	eth_send_ctrl/n426_s42/I2
4.013	0.421	tINS	RR	1	R33C28[2][A]	eth_send_ctrl/n426_s42/F
4.015	0.002	tNET	RR	1	R33C28[2][B]	eth_send_ctrl/n426_s38/I0
4.384	0.369	tINS	RR	1	R33C28[2][B]	eth_send_ctrl/n426_s38/F
4.386	0.002	tNET	RR	1	R33C28[3][B]	eth_send_ctrl/n426_s31/I1
4.784	0.398	tINS	RR	2	R33C28[3][B]	eth_send_ctrl/n426_s31/F
5.202	0.418	tNET	RR	1	R34C30[3][A]	eth_send_ctrl/n426_s24/I0
5.600	0.398	tINS	RR	2	R34C30[3][A]	eth_send_ctrl/n426_s24/F
5.604	0.004	tNET	RR	1	R34C30[2][B]	eth_send_ctrl/n426_s15/I1
5.973	0.369	tINS	RR	3	R34C30[2][B]	eth_send_ctrl/n426_s15/F
6.313	0.340	tNET	RR	1	R33C28[1][A]	eth_send_ctrl/n426_s12/I0
6.734	0.421	tINS	RR	1	R33C28[1][A]	eth_send_ctrl/n426_s12/F
6.860	0.126	tNET	RR	1	R34C28[2][B]	eth_send_ctrl/n426_s9/I1
7.070	0.210	tINS	RR	3	R34C28[2][B]	eth_send_ctrl/n426_s9/F
7.382	0.312	tNET	RR	1	R35C29[2][B]	eth_send_ctrl/n426_s10/I2
7.751	0.369	tINS	RR	1	R35C29[2][B]	eth_send_ctrl/n426_s10/F
7.751	0.000	tNET	RR	1	R35C29[2][B]	eth_send_ctrl/state_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
9.287	0.701	tNET	RR	1	R35C29[2][B]	eth_send_ctrl/state_1_s0/CLK
9.236	-0.051	tSu		1	R35C29[2][B]	eth_send_ctrl/state_1_s0

Path Statistics:

Clock Skew	-0.006
Setup Relationship	8.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.707, 100.000%
Arrival Data Path Delay	cell: 2.955, 45.757%; route: 3.197, 49.504%; tC2Q: 0.306, 4.738%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.695
Data Arrival Time	101.489
Data Required Time	102.184
From	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
To	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
100.000	100.000					active clock edge time
100.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
100.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
100.809	0.285	tNET	RR	1	R30C33[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
100.952	0.144	tC2Q	RR	3	R30C33[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/Q
101.283	0.330	tNET	RR	1	R29C35[1][A]	gw_gao_inst_0/u_la0_top/n1151_s1/I0
101.489	0.206	tINS	RF	1	R29C35[1][A]	gw_gao_inst_0/u_la0_top/n1151_s1/F
101.489	0.000	tNET	FF	1	R29C35[1][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
100.000	100.000					active clock edge time
100.000	0.000					tck_pad_i
100.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
100.581	0.581	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
100.581	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
101.162	0.581	tINS	RR	199	-	gw_gao_inst_0/u_gw_jtag/tck_o
102.148	0.986	tNET	RR	1	R29C35[1][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK
102.183	0.035	tUnc				gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0
102.184	0.001	tHld		1	R29C35[1][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0

Path Statistics:

Clock Skew	1.339
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.285, 100.000%
Arrival Data Path Delay	cell: 0.206, 30.294%; route: 0.330, 48.529%; tC2Q: 0.144, 21.176%
Required Clock Path Delay	cell: 1.162, 54.094%; route: 0.986, 45.906%

Path2

Path Summary:

Slack	0.061
Data Arrival Time	1.090
Data Required Time	1.029
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_18_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.835	0.312	tNET	RR	1	R6C72[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_18_s0/CLK
0.979	0.144	tC2Q	RR	1	R6C72[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_18_s0/Q
1.090	0.111	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[18]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.814	0.291	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.029	0.215	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.312, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.111, 43.529%; tC2Q: 0.144, 56.471%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.291, 100.000%

Path3

Path Summary:

Slack	0.137
Data Arrival Time	1.166
Data Required Time	1.029
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_9_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.833	0.310	tNET	RR	1	R7C72[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_9_s0/CLK
0.977	0.144	tC2Q	RR	1	R7C72[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_9_s0/Q
1.166	0.189	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.814	0.291	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.029	0.215	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.019
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.310, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.291, 100.000%

Path4

Path Summary:

Slack	0.139
Data Arrival Time	1.239
Data Required Time	1.100
From	eth_udp_rx_gmii/payload_dat_o_1_s0
To	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.898	0.311	tNET	RR	1	R4C31[0][A]	eth_udp_rx_gmii/payload_dat_o_1_s0/CLK
1.042	0.144	tC2Q	RR	1	R4C31[0][A]	eth_udp_rx_gmii/payload_dat_o_1_s0/Q
1.239	0.197	tNET	RR	1	BSRAM_R10[8]	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.885	0.299	tNET	RR	1	BSRAM_R10[8]	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA
1.100	0.215	tHld		1	BSRAM_R10[8]	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	-0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.311, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.197, 57.771%; tC2Q: 0.144, 42.229%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.299, 100.000%

Path5

Path Summary:

Slack	0.145
Data Arrival Time	1.132
Data Required Time	0.987
From	fifo_rx/fifo_inst/Equal.wbin_2_s0
To	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.886	0.300	tNET	RR	1	R9C30[1][A]	fifo_rx/fifo_inst/Equal.wbin_2_s0/CLK
1.030	0.144	tC2Q	RR	12	R9C30[1][A]	fifo_rx/fifo_inst/Equal.wbin_2_s0/Q
1.132	0.102	tNET	RR	1	BSRAM_R10[8]	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/ADA[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.885	0.299	tNET	RR	1	BSRAM_R10[8]	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA
0.987	0.102	tHld		1	BSRAM_R10[8]	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.102, 41.463%; tC2Q: 0.144, 58.537%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.299, 100.000%

Path6

Path Summary:

Slack	0.147
Data Arrival Time	1.176
Data Required Time	1.029
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_12_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.841	0.317	tNET	RR	1	R5C73[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_12_s0/CLK
0.985	0.144	tC2Q	RR	1	R5C73[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_12_s0/Q
1.176	0.191	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.814	0.291	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.029	0.215	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.026
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.317, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.291, 100.000%

Path7

Path Summary:

Slack	0.147
Data Arrival Time	1.176
Data Required Time	1.029
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_11_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.841	0.317	tNET	RR	1	R5C73[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_11_s0/CLK
0.985	0.144	tC2Q	RR	1	R5C73[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_11_s0/Q
1.176	0.191	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.814	0.291	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.029	0.215	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.026
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.317, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.291, 100.000%

Path8

Path Summary:

Slack	0.150
Data Arrival Time	1.250
Data Required Time	1.100
From	eth_udp_rx_gmii/payload_dat_o_3_s0
To	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.900	0.313	tNET	RR	1	R5C30[0][A]	eth_udp_rx_gmii/payload_dat_o_3_s0/CLK
1.044	0.144	tC2Q	RR	1	R5C30[0][A]	eth_udp_rx_gmii/payload_dat_o_3_s0/Q
1.250	0.206	tNET	RR	1	BSRAM_R10[8]	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.885	0.299	tNET	RR	1	BSRAM_R10[8]	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA
1.100	0.215	tHld		1	BSRAM_R10[8]	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	-0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.313, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.206, 58.857%; tC2Q: 0.144, 41.143%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.299, 100.000%

Path9

Path Summary:

Slack	0.153
Data Arrival Time	1.138
Data Required Time	0.985
From	eth_udp_tx_gmii/gmii_txd_2_s0
To	gmii_to_rgmii/[2].U_ODDR_dq1
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.901	0.315	tNET	RR	1	R2C11[1][B]	eth_udp_tx_gmii/gmii_txd_2_s0/CLK
1.045	0.144	tC2Q	RR	1	R2C11[1][B]	eth_udp_tx_gmii/gmii_txd_2_s0/Q
1.138	0.093	tNET	RR	1	IOT11[A]	gmii_to_rgmii/[2].U_ODDR_dq1/D0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.903	0.317	tNET	RR	1	IOT11[A]	gmii_to_rgmii/[2].U_ODDR_dq1/CLK
0.985	0.082	tHld		1	IOT11[A]	gmii_to_rgmii/[2].U_ODDR_dq1

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.315, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.317, 100.000%

Path10

Path Summary:

Slack	0.153
Data Arrival Time	1.138
Data Required Time	0.985
From	eth_udp_tx_gmii/gmii_txd_0_s0
To	gmii_to_rgmii/[0].U_ODDR_dq1
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.901	0.315	tNET	RR	1	R2C19[1][A]	eth_udp_tx_gmii/gmii_txd_0_s0/CLK
1.045	0.144	tC2Q	RR	1	R2C19[1][A]	eth_udp_tx_gmii/gmii_txd_0_s0/Q
1.138	0.093	tNET	RR	1	IOT19[A]	gmii_to_rgmii/[0].U_ODDR_dq1/D0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.903	0.317	tNET	RR	1	IOT19[A]	gmii_to_rgmii/[0].U_ODDR_dq1/CLK
0.985	0.082	tHld		1	IOT19[A]	gmii_to_rgmii/[0].U_ODDR_dq1

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.315, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.317, 100.000%

Path11

Path Summary:

Slack	0.154
Data Arrival Time	1.254
Data Required Time	1.100
From	eth_udp_rx_gmii/payload_dat_o_7_s0
To	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.898	0.312	tNET	RR	1	R6C26[1][A]	eth_udp_rx_gmii/payload_dat_o_7_s0/CLK
1.042	0.144	tC2Q	RR	1	R6C26[1][A]	eth_udp_rx_gmii/payload_dat_o_7_s0/Q
1.254	0.212	tNET	RR	1	BSRAM_R10[8]	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.885	0.299	tNET	RR	1	BSRAM_R10[8]	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA
1.100	0.215	tHld		1	BSRAM_R10[8]	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	-0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.312, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.212, 59.551%; tC2Q: 0.144, 40.449%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.299, 100.000%

Path12

Path Summary:

Slack	0.155
Data Arrival Time	1.085
Data Required Time	0.930
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/oserdes_d_reg_r_42_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.846	0.323	tNET	RR	1	R2C37[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/oserdes_d_reg_r_42_s0/CLK
0.990	0.144	tC2Q	RR	2	R2C37[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/oserdes_d_reg_r_42_s0/Q
1.085	0.095	tNET	RR	1	IOT37[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/D4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848	0.325	tNET	RR	1	IOT37[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/PCLK
0.930	0.082	tHld		1	IOT37[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.323, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.095, 39.749%; tC2Q: 0.144, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.325, 100.000%

Path13

Path Summary:

Slack	0.164
Data Arrival Time	1.138
Data Required Time	0.974
From	eth_udp_tx_gmii/gmii_txd_6_s0
To	gmii_to_rgmii/[2].U_ODDR_dq1
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.901	0.315	tNET	RR	1	R2C11[0][B]	eth_udp_tx_gmii/gmii_txd_6_s0/CLK
1.045	0.144	tC2Q	RR	1	R2C11[0][B]	eth_udp_tx_gmii/gmii_txd_6_s0/Q
1.138	0.093	tNET	RR	1	IOT11[A]	gmii_to_rgmii/[2].U_ODDR_dq1/D1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.903	0.317	tNET	RR	1	IOT11[A]	gmii_to_rgmii/[2].U_ODDR_dq1/CLK
0.974	0.072	tHld		1	IOT11[A]	gmii_to_rgmii/[2].U_ODDR_dq1

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.315, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.317, 100.000%

Path14

Path Summary:

Slack	0.164
Data Arrival Time	1.138
Data Required Time	0.974
From	eth_udp_tx_gmii/gmii_txd_4_s0
To	gmii_to_rgmii/[0].U_ODDR_dq1
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.901	0.315	tNET	RR	1	R2C19[0][B]	eth_udp_tx_gmii/gmii_txd_4_s0/CLK
1.045	0.144	tC2Q	RR	1	R2C19[0][B]	eth_udp_tx_gmii/gmii_txd_4_s0/Q
1.138	0.093	tNET	RR	1	IOT19[A]	gmii_to_rgmii/[0].U_ODDR_dq1/D1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
0.903	0.317	tNET	RR	1	IOT19[A]	gmii_to_rgmii/[0].U_ODDR_dq1/CLK
0.974	0.072	tHld		1	IOT19[A]	gmii_to_rgmii/[0].U_ODDR_dq1

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.315, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.317, 100.000%

Path15

Path Summary:

Slack	0.166
Data Arrival Time	1.085
Data Required Time	0.920
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/oserdes_d_reg_r_42_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.846	0.323	tNET	RR	1	R2C37[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/oserdes_d_reg_r_42_s0/CLK
0.990	0.144	tC2Q	RR	2	R2C37[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/oserdes_d_reg_r_42_s0/Q
1.085	0.095	tNET	RR	1	IOT37[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/D5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848	0.325	tNET	RR	1	IOT37[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/PCLK
0.920	0.072	tHld		1	IOT37[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.323, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.095, 39.749%; tC2Q: 0.144, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.325, 100.000%

Path16

Path Summary:

Slack	0.168
Data Arrival Time	1.136
Data Required Time	0.968
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.818	0.294	tNET	RR	1	R16C34[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0/CLK
0.962	0.144	tC2Q	RR	1	R16C34[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0/Q
1.136	0.174	tNET	RR	1	R18C34	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.883	0.297	tNET	RR	1	R18C34	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12/CLK
0.918	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12
0.968	0.050	tHld		1	R18C34	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12

Path Statistics:

Clock Skew	0.065
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.174, 54.717%; tC2Q: 0.144, 45.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.297, 100.000%

Path17

Path Summary:

Slack	0.177
Data Arrival Time	1.160
Data Required Time	0.983
From	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wbin_2_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.902	0.316	tNET	RR	1	R24C43[2][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wbin_2_s0/CLK
1.046	0.144	tC2Q	RR	10	R24C43[2][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wbin_2_s0/Q
1.160	0.114	tNET	RR	1	BSRAM_R28[13]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s/ADA[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.881	0.295	tNET	RR	1	BSRAM_R28[13]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s/CLKA
0.983	0.102	tHld		1	BSRAM_R28[13]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.316, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.114, 44.186%; tC2Q: 0.144, 55.814%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.295, 100.000%

Path18

Path Summary:

Slack	0.184
Data Arrival Time	1.148
Data Required Time	0.964
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.815	0.292	tNET	RR	1	R17C35[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0/CLK
0.959	0.144	tC2Q	RR	1	R17C35[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0/Q
1.148	0.189	tNET	RR	1	R18C33	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.879	0.293	tNET	RR	1	R18C33	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/CLK
0.914	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
0.964	0.050	tHld		1	R18C33	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8

Path Statistics:

Clock Skew	0.064
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.292, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.293, 100.000%

Path19

Path Summary:

Slack	0.185
Data Arrival Time	1.222
Data Required Time	1.037
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_22_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.841	0.317	tNET	RR	1	R23C53[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_22_s0/CLK
0.985	0.144	tC2Q	RR	1	R23C53[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_22_s0/Q
1.222	0.237	tNET	RR	1	BSRAM_R28[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[22]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.822	0.299	tNET	RR	1	BSRAM_R28[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA
1.037	0.215	tHld		1	BSRAM_R28[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.018
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.317, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.237, 62.205%; tC2Q: 0.144, 37.795%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.299, 100.000%

Path20

Path Summary:

Slack	0.187
Data Arrival Time	1.151
Data Required Time	0.964
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.818	0.294	tNET	RR	1	R16C34[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0/CLK
0.962	0.144	tC2Q	RR	1	R16C34[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0/Q
1.151	0.189	tNET	RR	1	R18C33	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.879	0.293	tNET	RR	1	R18C33	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/CLK
0.914	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
0.964	0.050	tHld		1	R18C33	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8

Path Statistics:

Clock Skew	0.061
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.293, 100.000%

Path21

Path Summary:

Slack	0.193
Data Arrival Time	1.222
Data Required Time	1.029
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.841	0.317	tNET	RR	1	R5C73[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0/CLK
0.985	0.144	tC2Q	RR	1	R5C73[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0/Q
1.222	0.237	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[16]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.814	0.291	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.029	0.215	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.026
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.317, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.237, 62.205%; tC2Q: 0.144, 37.795%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.291, 100.000%

Path22

Path Summary:

Slack	0.193
Data Arrival Time	1.222
Data Required Time	1.029
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_14_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.841	0.317	tNET	RR	1	R5C73[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_14_s0/CLK
0.985	0.144	tC2Q	RR	1	R5C73[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_14_s0/Q
1.222	0.237	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.814	0.291	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.029	0.215	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.026
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.317, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.237, 62.205%; tC2Q: 0.144, 37.795%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.291, 100.000%

Path23

Path Summary:

Slack	0.193
Data Arrival Time	1.222
Data Required Time	1.029
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_13_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.841	0.317	tNET	RR	1	R5C73[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_13_s0/CLK
0.985	0.144	tC2Q	RR	1	R5C73[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_13_s0/Q
1.222	0.237	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.814	0.291	tNET	RR	1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
1.029	0.215	tHld		1	BSRAM_R10[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.026
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.317, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.237, 62.205%; tC2Q: 0.144, 37.795%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.291, 100.000%

Path24

Path Summary:

Slack	0.194
Data Arrival Time	1.118
Data Required Time	0.924
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.827	0.304	tNET	RR	1	R27C53[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_2_s0/CLK
0.971	0.144	tC2Q	RR	6	R27C53[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/wbin_2_s0/Q
1.118	0.147	tNET	RR	1	BSRAM_R28[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/ADA[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.822	0.299	tNET	RR	1	BSRAM_R28[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA
0.924	0.102	tHld		1	BSRAM_R28[16]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.304, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.147, 50.515%; tC2Q: 0.144, 49.485%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.299, 100.000%

Path25

Path Summary:

Slack	0.195
Data Arrival Time	1.228
Data Required Time	1.033
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_36_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.837	0.313	tNET	RR	1	R23C54[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_36_s0/CLK
0.981	0.144	tC2Q	RR	1	R23C54[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_36_s0/Q
1.228	0.247	tNET	RR	1	BSRAM_R28[17]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.818	0.295	tNET	RR	1	BSRAM_R28[17]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA
1.033	0.215	tHld		1	BSRAM_R28[17]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	-0.018
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.313, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.247, 63.171%; tC2Q: 0.144, 36.829%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.295, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.326
Data Arrival Time	3.189
Data Required Time	3.515
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	10	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.086	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.086	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.247	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.970	0.723	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
3.935	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
3.515	-0.420	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.163
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path2

Path Summary:

Slack	0.326
Data Arrival Time	3.189
Data Required Time	3.515
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	10	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.086	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.086	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.247	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.970	0.723	tNET	FF	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
3.935	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
3.515	-0.420	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.163
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path3

Path Summary:

Slack	0.616
Data Arrival Time	3.189
Data Required Time	3.805
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.086	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.086	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.247	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.970	0.723	tNET	FF	1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/FCLK
3.935	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
3.805	-0.130	tSu		1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen

Path Statistics:

Clock Skew	0.163
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path4

Path Summary:

Slack	0.616
Data Arrival Time	3.189
Data Required Time	3.805
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.086	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.086	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.247	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.970	0.723	tNET	FF	1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/FCLK
3.935	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
3.805	-0.130	tSu		1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen

Path Statistics:

Clock Skew	0.163
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path5

Path Summary:

Slack	0.616
Data Arrival Time	3.189
Data Required Time	3.805
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.086	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.086	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.247	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.970	0.723	tNET	FF	1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/FCLK
3.935	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
3.805	-0.130	tSu		1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen

Path Statistics:

Clock Skew	0.163
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path6

Path Summary:

Slack	0.616
Data Arrival Time	3.189
Data Required Time	3.805
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.086	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.086	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.247	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.970	0.723	tNET	FF	1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/FCLK
3.935	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
3.805	-0.130	tSu		1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew	0.163
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path7

Path Summary:

Slack	0.616
Data Arrival Time	3.189
Data Required Time	3.805
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.086	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.086	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.247	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.970	0.723	tNET	FF	1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/FCLK
3.935	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
3.805	-0.130	tSu		1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen

Path Statistics:

Clock Skew	0.163
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path8

Path Summary:

Slack	0.616
Data Arrival Time	3.189
Data Required Time	3.805
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.086	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.086	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.247	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.970	0.723	tNET	FF	1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/FCLK
3.935	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
3.805	-0.130	tSu		1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen

Path Statistics:

Clock Skew	0.163
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path9

Path Summary:

Slack	0.616
Data Arrival Time	3.189
Data Required Time	3.805
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT43[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.086	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.086	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.247	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.970	0.723	tNET	FF	1	IOT43[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/FCLK
3.935	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen
3.805	-0.130	tSu		1	IOT43[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen

Path Statistics:

Clock Skew	0.163
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path10

Path Summary:

Slack	2.823
Data Arrival Time	3.189
Data Required Time	6.011
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	10	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
5.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
5.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.468	0.725	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
6.433	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
6.011	-0.422	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.161
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path11

Path Summary:

Slack	2.823
Data Arrival Time	3.189
Data Required Time	6.011
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	10	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
5.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
5.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.468	0.725	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
6.433	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
6.011	-0.422	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.161
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path12

Path Summary:

Slack	3.112
Data Arrival Time	3.189
Data Required Time	6.301
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
5.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
5.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.468	0.725	tNET	RR	1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/FCLK
6.433	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
6.301	-0.132	tSu		1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen

Path Statistics:

Clock Skew	0.161
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path13

Path Summary:

Slack	3.112
Data Arrival Time	3.189
Data Required Time	6.301
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
5.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
5.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.468	0.725	tNET	RR	1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/FCLK
6.433	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
6.301	-0.132	tSu		1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen

Path Statistics:

Clock Skew	0.161
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path14

Path Summary:

Slack	3.112
Data Arrival Time	3.189
Data Required Time	6.301
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
5.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
5.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.468	0.725	tNET	RR	1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/FCLK
6.433	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
6.301	-0.132	tSu		1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen

Path Statistics:

Clock Skew	0.161
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path15

Path Summary:

Slack	3.112
Data Arrival Time	3.189
Data Required Time	6.301
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
5.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
5.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.468	0.725	tNET	RR	1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/FCLK
6.433	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
6.301	-0.132	tSu		1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew	0.161
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path16

Path Summary:

Slack	3.112
Data Arrival Time	3.189
Data Required Time	6.301
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
5.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
5.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.468	0.725	tNET	RR	1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/FCLK
6.433	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
6.301	-0.132	tSu		1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen

Path Statistics:

Clock Skew	0.161
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path17

Path Summary:

Slack	3.112
Data Arrival Time	3.189
Data Required Time	6.301
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
5.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
5.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.743	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.468	0.725	tNET	RR	1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/FCLK
6.433	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
6.301	-0.132	tSu		1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen

Path Statistics:

Clock Skew	0.161
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path18

Path Summary:

Slack	17.595
Data Arrival Time	3.189
Data Required Time	20.784
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	10	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.248	0.725	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/PCLK
21.213	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
20.784	-0.429	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	-0.058
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path19

Path Summary:

Slack	17.595
Data Arrival Time	3.189
Data Required Time	20.784
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	10	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.248	0.725	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/PCLK
21.213	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
20.784	-0.429	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	-0.058
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path20

Path Summary:

Slack	17.885
Data Arrival Time	3.189
Data Required Time	21.074
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.240	0.717	tNET	RR	1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/PCLK
21.205	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
21.074	-0.132	tSu		1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen

Path Statistics:

Clock Skew	-0.066
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.717, 100.000%

Path21

Path Summary:

Slack	17.892
Data Arrival Time	3.189
Data Required Time	21.081
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.248	0.725	tNET	RR	1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/PCLK
21.213	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
21.081	-0.132	tSu		1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen

Path Statistics:

Clock Skew	-0.058
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path22

Path Summary:

Slack	17.892
Data Arrival Time	3.189
Data Required Time	21.081
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.248	0.725	tNET	RR	1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/PCLK
21.213	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
21.081	-0.132	tSu		1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen

Path Statistics:

Clock Skew	-0.058
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path23

Path Summary:

Slack	17.892
Data Arrival Time	3.189
Data Required Time	21.081
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.248	0.725	tNET	RR	1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/PCLK
21.213	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
21.081	-0.132	tSu		1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen

Path Statistics:

Clock Skew	-0.058
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path24

Path Summary:

Slack	17.892
Data Arrival Time	3.189
Data Required Time	21.081
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.248	0.725	tNET	RR	1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/PCLK
21.213	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
21.081	-0.132	tSu		1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen

Path Statistics:

Clock Skew	-0.058
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path25

Path Summary:

Slack	17.900
Data Arrival Time	3.189
Data Required Time	21.089
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
1.306	0.720	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.600	0.294	tC2Q	RF	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.189	1.588	tNET	FF	2	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.256	0.732	tNET	RR	1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/PCLK
21.221	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
21.089	-0.132	tSu		1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew	-0.051
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.588, 84.380%; tC2Q: 0.294, 15.620%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.732, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.859
Data Arrival Time	51.188
Data Required Time	52.047
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[F]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
50.523	0.523	tCL	FF	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
50.832	0.308	tNET	FF	1	R27C33[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
50.990	0.158	tC2Q	FR	51	R27C33[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
51.188	0.198	tNET	RR	1	R26C35[0][B]	gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.581	0.581	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.581	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.162	0.581	tINS	RR	199	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.163	1.001	tNET	RR	1	R26C35[0][B]	gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLK
52.198	0.035	tUnc				gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0
52.047	-0.151	tHld		1	R26C35[0][B]	gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0

Path Statistics:

Clock Skew	1.331
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.308, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.198, 55.618%; tC2Q: 0.158, 44.382%
Required Clock Path Delay	cell: 1.162, 53.719%; route: 1.001, 46.281%

Path2

Path Summary:

Slack	-0.859
Data Arrival Time	51.188
Data Required Time	52.047
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[F]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
50.523	0.523	tCL	FF	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
50.832	0.308	tNET	FF	1	R27C33[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
50.990	0.158	tC2Q	FR	51	R27C33[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
51.188	0.198	tNET	RR	1	R26C35[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.581	0.581	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.581	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.162	0.581	tINS	RR	199	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.163	1.001	tNET	RR	1	R26C35[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLK
52.198	0.035	tUnc				gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0
52.047	-0.151	tHld		1	R26C35[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0

Path Statistics:

Clock Skew	1.331
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.308, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.198, 55.618%; tC2Q: 0.158, 44.382%
Required Clock Path Delay	cell: 1.162, 53.719%; route: 1.001, 46.281%

Path3

Path Summary:

Slack	-0.569
Data Arrival Time	51.463
Data Required Time	52.032
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[F]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
50.523	0.523	tCL	FF	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
50.832	0.308	tNET	FF	1	R27C33[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
50.990	0.158	tC2Q	FR	51	R27C33[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
51.463	0.473	tNET	RR	1	R29C35[1][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.581	0.581	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.581	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.162	0.581	tINS	RR	199	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.148	0.986	tNET	RR	1	R29C35[1][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK
52.183	0.035	tUnc				gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0
52.032	-0.151	tHld		1	R29C35[1][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0

Path Statistics:

Clock Skew	1.316
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.308, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 1.162, 54.094%; route: 0.986, 45.906%

Path4

Path Summary:

Slack	0.422
Data Arrival Time	1.947
Data Required Time	1.526
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.721	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.041	0.321	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.359	0.317	tINS	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
1.359	0.000	tNET	RR	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
1.394	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.526	0.132	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.458
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.452, 58.495%; route: 0.321, 41.505%

Path5

Path Summary:

Slack	0.422
Data Arrival Time	1.947
Data Required Time	1.526
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.721	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.041	0.321	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.359	0.317	tINS	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
1.359	0.000	tNET	RR	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
1.394	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.526	0.132	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.458
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.452, 58.495%; route: 0.321, 41.505%

Path6

Path Summary:

Slack	0.498
Data Arrival Time	1.947
Data Required Time	1.449
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.721	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.041	0.321	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.282	0.240	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.282	0.000	tNET	RR	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TCLK
1.317	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
1.449	0.132	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	0.381
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.375, 53.916%; route: 0.321, 46.084%

Path7

Path Summary:

Slack	0.498
Data Arrival Time	1.947
Data Required Time	1.449
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.721	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.041	0.321	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.282	0.240	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.282	0.000	tNET	RR	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TCLK
1.317	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
1.449	0.132	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	0.381
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.375, 53.916%; route: 0.321, 46.084%

Path8

Path Summary:

Slack	0.498
Data Arrival Time	1.947
Data Required Time	1.449
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.721	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.041	0.321	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.282	0.240	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.282	0.000	tNET	RR	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TCLK
1.317	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
1.449	0.132	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	0.381
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.375, 53.916%; route: 0.321, 46.084%

Path9

Path Summary:

Slack	0.498
Data Arrival Time	1.947
Data Required Time	1.449
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.721	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.041	0.321	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.282	0.240	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.282	0.000	tNET	RR	1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/TCLK
1.317	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
1.449	0.132	tHld		1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew	0.381
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.375, 53.916%; route: 0.321, 46.084%

Path10

Path Summary:

Slack	0.739
Data Arrival Time	1.947
Data Required Time	1.208
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.721	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.041	0.321	tNET	RR	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/FCLK
1.076	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.208	0.132	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.141
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.134, 29.556%; route: 0.321, 70.444%

Path11

Path Summary:

Slack	0.739
Data Arrival Time	1.947
Data Required Time	1.208
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.721	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.041	0.321	tNET	RR	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/FCLK
1.076	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.208	0.132	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.141
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.134, 29.556%; route: 0.321, 70.444%

Path12

Path Summary:

Slack	0.739
Data Arrival Time	1.947
Data Required Time	1.208
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.721	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.041	0.321	tNET	RR	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/FCLK
1.076	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
1.208	0.132	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	0.141
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.134, 29.556%; route: 0.321, 70.444%

Path13

Path Summary:

Slack	0.739
Data Arrival Time	1.947
Data Required Time	1.208
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.721	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.041	0.321	tNET	RR	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/FCLK
1.076	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
1.208	0.132	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	0.141
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.134, 29.556%; route: 0.321, 70.444%

Path14

Path Summary:

Slack	0.739
Data Arrival Time	1.947
Data Required Time	1.208
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.721	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.041	0.321	tNET	RR	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/FCLK
1.076	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
1.208	0.132	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	0.141
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.134, 29.556%; route: 0.321, 70.444%

Path15

Path Summary:

Slack	0.739
Data Arrival Time	1.947
Data Required Time	1.208
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
0.586	0.586	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
0.586	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.721	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.041	0.321	tNET	RR	1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/FCLK
1.076	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
1.208	0.132	tHld		1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew	0.141
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.134, 29.556%; route: 0.321, 70.444%

Path16

Path Summary:

Slack	0.932
Data Arrival Time	1.947
Data Required Time	1.015
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848	0.325	tNET	RR	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/PCLK
0.883	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.015	0.132	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	-0.052
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.325, 100.000%

Path17

Path Summary:

Slack	0.932
Data Arrival Time	1.947
Data Required Time	1.015
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848	0.325	tNET	RR	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/PCLK
0.883	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
1.015	0.132	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	-0.052
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.325, 100.000%

Path18

Path Summary:

Slack	0.936
Data Arrival Time	1.947
Data Required Time	1.011
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.844	0.321	tNET	RR	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/PCLK
0.879	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.011	0.132	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	-0.056
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.321, 100.000%

Path19

Path Summary:

Slack	0.936
Data Arrival Time	1.947
Data Required Time	1.011
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.844	0.321	tNET	RR	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/PCLK
0.879	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
1.011	0.132	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	-0.056
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.321, 100.000%

Path20

Path Summary:

Slack	0.940
Data Arrival Time	1.947
Data Required Time	1.007
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3297	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.840	0.317	tNET	RR	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/PCLK
0.875	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
1.007	0.132	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	-0.060
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.317, 100.000%

Path21

Path Summary:

Slack	2.895
Data Arrival Time	1.947
Data Required Time	-0.947
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.914	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.914	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.774	0.140	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.448	0.326	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.113	0.335	tINS	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
-1.113	0.000	tNET	FF	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
-1.078	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
-0.947	0.130	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.487
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.475, 59.299%; route: 0.326, 40.701%

Path22

Path Summary:

Slack	2.895
Data Arrival Time	1.947
Data Required Time	-0.947
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.914	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.914	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.774	0.140	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.448	0.326	tNET	FF	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.113	0.335	tINS	FF	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
-1.113	0.000	tNET	FF	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
-1.078	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
-0.947	0.130	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.487
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.475, 59.299%; route: 0.326, 40.701%

Path23

Path Summary:

Slack	2.981
Data Arrival Time	1.947
Data Required Time	-1.034
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.914	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.914	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.774	0.140	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.448	0.326	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.199	0.249	tINS	FF	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-1.199	0.000	tNET	FF	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TCLK
-1.164	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
-1.034	0.130	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	0.401
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.389, 54.390%; route: 0.326, 45.610%

Path24

Path Summary:

Slack	2.981
Data Arrival Time	1.947
Data Required Time	-1.034
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.914	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.914	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.774	0.140	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.448	0.326	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.199	0.249	tINS	FF	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-1.199	0.000	tNET	FF	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TCLK
-1.164	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
-1.034	0.130	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	0.401
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.389, 54.390%; route: 0.326, 45.610%

Path25

Path Summary:

Slack	2.981
Data Arrival Time	1.947
Data Required Time	-1.034
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	543	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT0
0.900	0.314	tNET	RR	1	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.044	0.144	tC2Q	RR	2196	R7C43[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.947	0.903	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.914	0.586	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.914	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.774	0.140	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.448	0.326	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.199	0.249	tINS	FF	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-1.199	0.000	tNET	FF	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TCLK
-1.164	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
-1.034	0.130	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	0.401
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.314, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.903, 86.243%; tC2Q: 0.144, 13.757%
Required Clock Path Delay	cell: 0.389, 54.390%; route: 0.326, 45.610%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.737
Actual Width:	3.599
Required Width:	0.862
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.286	0.700	tNET	FF	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.885	0.299	tNET	RR	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

MPW2

MPW Summary:

Slack:	2.739
Actual Width:	3.601
Required Width:	0.862
Type:	High Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
1.289	0.703	tNET	RR	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
4.890	0.304	tNET	FF	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

MPW3

MPW Summary:

Slack:	2.741
Actual Width:	3.603
Required Width:	0.862
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.279	0.692	tNET	FF	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.881	0.295	tNET	RR	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CLKB

MPW4

MPW Summary:

Slack:	2.742
Actual Width:	3.604
Required Width:	0.862
Type:	High Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
1.282	0.695	tNET	RR	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
4.886	0.300	tNET	FF	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CLKB

MPW5

MPW Summary:

Slack:	3.395
Actual Width:	3.595
Required Width:	0.200
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	eth_udp_rx_gmii/rx_data_dly1_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.315	0.728	tNET	FF	eth_udp_rx_gmii/rx_data_dly1_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.909	0.323	tNET	RR	eth_udp_rx_gmii/rx_data_dly1_5_s0/CLK

MPW6

MPW Summary:

Slack:	3.395
Actual Width:	3.595
Required Width:	0.200
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	eth_udp_rx_gmii/rx_src_ip_17_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.315	0.728	tNET	FF	eth_udp_rx_gmii/rx_src_ip_17_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.909	0.323	tNET	RR	eth_udp_rx_gmii/rx_src_ip_17_s0/CLK

MPW7

MPW Summary:

Slack:	3.395
Actual Width:	3.595
Required Width:	0.200
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	eth_udp_rx_gmii/cnt_drp_data_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.315	0.728	tNET	FF	eth_udp_rx_gmii/cnt_drp_data_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.909	0.323	tNET	RR	eth_udp_rx_gmii/cnt_drp_data_4_s0/CLK

MPW8

MPW Summary:

Slack:	3.395
Actual Width:	3.595
Required Width:	0.200
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	eth_udp_rx_gmii/cnt_drp_data_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.315	0.728	tNET	FF	eth_udp_rx_gmii/cnt_drp_data_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.909	0.323	tNET	RR	eth_udp_rx_gmii/cnt_drp_data_0_s0/CLK

MPW9

MPW Summary:

Slack:	3.395
Actual Width:	3.595
Required Width:	0.200
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	eth_udp_rx_gmii/rx_src_ip_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.315	0.728	tNET	FF	eth_udp_rx_gmii/rx_src_ip_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.909	0.323	tNET	RR	eth_udp_rx_gmii/rx_src_ip_16_s0/CLK

MPW10

MPW Summary:

Slack:	3.395
Actual Width:	3.595
Required Width:	0.200
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	eth_udp_rx_gmii/rx_dst_ip_25_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.315	0.728	tNET	FF	eth_udp_rx_gmii/rx_dst_ip_25_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.909	0.323	tNET	RR	eth_udp_rx_gmii/rx_dst_ip_25_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
3297	ddr3_ctrl_2port_4	-0.180	0.739
2196	ui_clk_sync_rst	0.326	1.660
751	gmii_tx_clk	0.512	0.732
543	loc_clk50m	-0.361	0.819
389	eye_calib_start_Z	13.023	4.774
251	raddr[3]	12.669	1.456
221	led_d_10[1]	14.775	2.085
199	control0[0]	4.442	1.858
148	dqsts1	17.767	1.459
147	dqs_reg	17.753	1.461

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R10C69	69.44%
R10C68	68.06%
R10C61	66.67%
R10C66	66.67%
R10C60	65.28%
R28C45	62.50%
R10C65	62.50%
R10C72	62.50%
R28C48	61.11%
R11C61	61.11%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command