Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2405991
date_generatedThu Jul 25 09:45:46 2024 os_platformWIN64
product_versionVivado v2018.3 (64-bit) project_id9fe3c7e32ad04bd0b8de51084ea63cc1
project_iteration1 random_idd5dafe613c7d52b294e5305d9a62f2fb
registration_idd5dafe613c7d52b294e5305d9a62f2fb route_designTRUE
target_devicexc7a100t target_familyartix7
target_packagefgg484 target_speed-2
tool_flowVivado

user_environment
cpu_name12th Gen Intel(R) Core(TM) i7-12700 cpu_speed2112 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram16.000 GB total_processors1

vivado_usage
gui_handlers
basedialog_ok=60 basedialog_yes=1 coretreetablepanel_core_tree_table=5 createconstraintsfilepanel_file_name=1
createsrcfiledialog_file_name=28 filesetpanel_file_set_panel_tree=103 flownavigatortreepanel_flow_navigator_tree=4 fpgachooser_fpga_table=2
gettingstartedview_create_new_project=1 pacommandnames_add_sources=28 pacommandnames_goto_netlist_design=1 paviews_project_summary=2
projectnamechooser_choose_project_location=3 projectnamechooser_project_name=1 rdicommands_save_file=1 saveprojectutils_dont_save=1
saveprojectutils_save=1 signaltreepanel_signal_tree_table=49 simpleoutputproductdialog_generate_output_products_immediately=1 srcchooserpanel_create_file=28
srcchooserpanel_scan_and_add_rtl_include_files_into=1
java_command_handlers
addsources=28 coreview=1 customizecore=1 newproject=1
runbitgen=1 runsynthesis=2 savedesign=1 viewtasksynthesis=2
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=1 export_simulation_ies=1
export_simulation_modelsim=1 export_simulation_questa=1 export_simulation_riviera=1 export_simulation_vcs=1
export_simulation_xsim=1 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=27 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=2 totalsynthesisruns=2

unisim_transformation
post_unisim_transformation
bufg=3 carry4=9 fdce=334 fdpe=41
gnd=6 ibuf=4 lut1=10 lut2=83
lut3=61 lut4=147 lut5=254 lut6=307
mmcme2_adv=1 obuf=4 ramb18e1=2 vcc=34
pre_unisim_transformation
bufg=3 carry4=9 fdce=334 fdpe=41
gnd=6 ibuf=4 lut1=10 lut2=83
lut3=61 lut4=147 lut5=254 lut6=307
mmcme2_adv=1 obuf=4 ramb18e1=2 vcc=34

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=0 bram_ports_total=4 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=375 srls_augmented=0
srls_newly_gated=0 srls_total=0

ip_statistics
clk_wiz_v6_0_2_0_0/1
clkin1_period=20.000 clkin2_period=10.0 clock_mgr_type=NA component_name=pll
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=1 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=false use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=false

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1 check-3=1 reqp-1840=20

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
lutar-1=1 timing-16=6 timing-17=124

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.001063 clocks=0.002925
confidence_level_clock_activity=Low confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Medium confidence_level_overall=Low customer=TBD customer_class=TBD
devstatic=0.097278 die=xc7a100tfgg484-2 dsp_output_toggle=12.500000 dynamic=0.113281
effective_thetaja=2.7 enable_probability=0.990000 family=artix7 ff_toggle=12.500000
flow_state=routed heatsink=medium (Medium Profile) i/o=0.002384 input_toggle=12.500000
junction_temp=25.6 (C) logic=0.000835 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mmcm=0.105339 netlist_net_matched=NA
off-chip_power=0.000000 on-chip_power=0.210559 output_enable=1.000000 output_load=5.000000
output_toggle=12.500000 package=fgg484 pct_clock_constrained=0.000000 pct_inputs_defined=25
platform=nt64 process=typical ram_enable=50.000000 ram_write=50.000000
read_saif=False set/reset_probability=0.000000 signal_rate=False signals=0.000735
simulation_file=None speedgrade=-2 static_prob=False temp_grade=commercial
thetajb=6.8 (C/W) thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C)
user_effective_thetaja=2.7 user_junc_temp=25.6 (C) user_thetajb=6.8 (C/W) user_thetasa=4.6 (C/W)
vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000
vccaux_dynamic_current=0.058433 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 vccaux_static_current=0.018149 vccaux_total_current=0.076582 vccaux_voltage=1.800000
vccbram_dynamic_current=0.000081 vccbram_static_current=0.000270 vccbram_total_current=0.000351 vccbram_voltage=1.000000
vccint_dynamic_current=0.005831 vccint_static_current=0.015140 vccint_total_current=0.020971 vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000
vcco33_dynamic_current=0.000664 vcco33_static_current=0.004000 vcco33_total_current=0.004664 vcco33_voltage=3.300000
version=2018.3

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=3 bufgctrl_util_percentage=9.38
bufhce_available=96 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=24 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=12 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=24 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=6 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=16.67
plle2_adv_available=6 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=240 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=135 block_ram_tile_fixed=0 block_ram_tile_used=1 block_ram_tile_util_percentage=0.74
ramb18_available=270 ramb18_fixed=0 ramb18_used=2 ramb18_util_percentage=0.74
ramb18e1_only_used=2 ramb36_fifo_available=135 ramb36_fifo_fixed=0 ramb36_fifo_used=0
ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=3 carry4_functional_category=CarryLogic carry4_used=9
fdce_functional_category=Flop & Latch fdce_used=334 fdpe_functional_category=Flop & Latch fdpe_used=41
ibuf_functional_category=IO ibuf_used=4 lut1_functional_category=LUT lut1_used=10
lut2_functional_category=LUT lut2_used=83 lut3_functional_category=LUT lut3_used=61
lut4_functional_category=LUT lut4_used=147 lut5_functional_category=LUT lut5_used=254
lut6_functional_category=LUT lut6_used=307 mmcme2_adv_functional_category=Clock mmcme2_adv_used=1
obuf_functional_category=IO obuf_used=4 ramb18e1_functional_category=Block Memory ramb18e1_used=2
slice_logic
f7_muxes_available=31700 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=15850 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=63400 lut_as_logic_fixed=0 lut_as_logic_used=712 lut_as_logic_util_percentage=1.12
lut_as_memory_available=19000 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=126800 register_as_flip_flop_fixed=0 register_as_flip_flop_used=375 register_as_flip_flop_util_percentage=0.30
register_as_latch_available=126800 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=63400 slice_luts_fixed=0 slice_luts_used=712 slice_luts_util_percentage=1.12
slice_registers_available=126800 slice_registers_fixed=0 slice_registers_used=375 slice_registers_util_percentage=0.30
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=63400 lut_as_logic_fixed=0
lut_as_logic_used=712 lut_as_logic_util_percentage=1.12 lut_as_memory_available=19000 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=72 lut_in_front_of_the_register_is_used_fixed=72 lut_in_front_of_the_register_is_used_used=57
register_driven_from_outside_the_slice_fixed=57 register_driven_from_outside_the_slice_used=129 register_driven_from_within_the_slice_fixed=129 register_driven_from_within_the_slice_used=246
slice_available=15850 slice_fixed=0 slice_registers_available=126800 slice_registers_fixed=0
slice_registers_used=375 slice_registers_util_percentage=0.30 slice_used=243 slice_util_percentage=1.53
slicel_fixed=0 slicel_used=166 slicem_fixed=0 slicem_used=77
unique_control_sets_available=15850 unique_control_sets_fixed=15850 unique_control_sets_used=44 unique_control_sets_util_percentage=0.28
using_o5_and_o6_fixed=0.28 using_o5_and_o6_used=150 using_o5_output_only_fixed=150 using_o5_output_only_used=7
using_o6_output_only_fixed=7 using_o6_output_only_used=555
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a100tfgg484-2
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=top -verilog_define=default::[not_specified]
usage
elapsed=00:00:34s hls_ip=0 memory_gain=724.645MB memory_peak=1080.941MB