
State Machine - |CoreCourse_GHRD|i2s_tx:i2s_tx|state
Name state.state_idle state.state_tx_right_data state.state_tx_left_data 
state.state_idle 0 0 0 
state.state_tx_left_data 1 0 1 
state.state_tx_right_data 1 1 0 

State Machine - |CoreCourse_GHRD|i2s_rx:i2s_rx|state
Name state.state_fifo_write state.state_right_data state.state_left_data state.state_idle 
state.state_idle 0 0 0 0 
state.state_left_data 0 0 1 1 
state.state_right_data 0 1 0 1 
state.state_fifo_write 1 0 0 1 

State Machine - |CoreCourse_GHRD|WM8960_Init:WM8960_Init|I2C_Init_Dev:I2C_Init_Dev|state
Name state.00 state.10 state.01 
state.00 0 0 0 
state.01 1 0 1 
state.10 1 1 0 

State Machine - |CoreCourse_GHRD|WM8960_Init:WM8960_Init|I2C_Init_Dev:I2C_Init_Dev|i2c_control:i2c_control|state
Name state.RD_REG_DONE state.WAIT_RD_DONE state.RD_REG state.WR_REG_DONE state.WAIT_WR_DONE state.WR_REG state.IDLE 
state.IDLE 0 0 0 0 0 0 0 
state.WR_REG 0 0 0 0 0 1 1 
state.WAIT_WR_DONE 0 0 0 0 1 0 1 
state.WR_REG_DONE 0 0 0 1 0 0 1 
state.RD_REG 0 0 1 0 0 0 1 
state.WAIT_RD_DONE 0 1 0 0 0 0 1 
state.RD_REG_DONE 1 0 0 0 0 0 1 

State Machine - |CoreCourse_GHRD|WM8960_Init:WM8960_Init|I2C_Init_Dev:I2C_Init_Dev|i2c_control:i2c_control|i2c_bit_shift:i2c_bit_shift|state
Name state.GEN_STO state.GEN_ACK state.CHECK_ACK state.RD_DATA state.WR_DATA state.GEN_STA state.IDLE 
state.IDLE 0 0 0 0 0 0 0 
state.GEN_STA 0 0 0 0 0 1 1 
state.WR_DATA 0 0 0 0 1 0 1 
state.RD_DATA 0 0 0 1 0 0 1 
state.CHECK_ACK 0 0 1 0 0 0 1 
state.GEN_ACK 0 1 0 0 0 0 1 
state.GEN_STO 1 0 0 0 0 0 1 
