Synthesis Messages

Report Title	GowinSynthesis Report
Design File	E:\project\Gowin\ch62_audio_loopback\src\WM8960_Init\I2C_Init_Dev.v E:\project\Gowin\ch62_audio_loopback\src\WM8960_Init\WM8960_Init.v E:\project\Gowin\ch62_audio_loopback\src\WM8960_Init\i2c_bit_shift.v E:\project\Gowin\ch62_audio_loopback\src\WM8960_Init\i2c_control.v E:\project\Gowin\ch62_audio_loopback\src\WM8960_Init\wm8960_init_table.v E:\project\Gowin\ch62_audio_loopback\src\fifo\async_fifo.v E:\project\Gowin\ch62_audio_loopback\src\fifo\async_fifo_ctrl.v E:\project\Gowin\ch62_audio_loopback\src\fifo\dpram.v E:\project\Gowin\ch62_audio_loopback\src\gowin_pll\gowin_pll.v E:\project\Gowin\ch62_audio_loopback\src\i2s\i2s_rx.v E:\project\Gowin\ch62_audio_loopback\src\i2s\i2s_tx.v E:\project\Gowin\ch62_audio_loopback\src\top\audio_lookback.v
GowinSynthesis Constraints File	---
Tool Version	V1.9.9.03 Education (64-bit)
Part Number	GW5A-LV25UG324C2/I1
Device	GW5A-25
Device Version	A
Created Time	Wed Aug 21 09:42:43 2024
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	audio_lookback
Synthesis Process	Running parser: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.172s, Peak memory usage = 520.832MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 520.832MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 520.832MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 520.832MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 520.832MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 520.832MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 520.832MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 520.832MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 520.832MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 520.832MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 520.832MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.781s, Elapsed time = 0h 0m 0.8s, Peak memory usage = 520.832MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 520.832MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 520.832MB
Total Time and Memory Usage	CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 520.832MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	11
I/O Buf	11
IBUF	6
OBUF	4
IOBUF	1
Register	449
DFFRE	69
DFFPE	7
DFFCE	373
LUT	426
LUT2	90
LUT3	109
LUT4	227
ALU	47
ALU	47
INV	6
INV	6
BSRAM	3
SDPB	2
pROM	1
CLOCK	1
PLLA	1

Resource Utilization Summary

Resource	Usage	Utilization
Logic	479(432 LUT, 47 ALU) / 23040	3%
Register	449 / 23685	2%
--Register as Latch	0 / 23685	0%
--Register as FF	449 / 23685	2%
BSRAM	3 / 56	6%

Timing

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Fall	Source	Master	Object
clk	Base	20.000	50.0	10.000			clk_ibuf/I
I2S_BCLK	Base	10.000	100.0	5.000			I2S_BCLK_ibuf/I
I2S_DACLRC	Base	10.000	100.0	5.000			I2S_DACLRC_ibuf/I
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk	Generated	83.333	12.0	41.667	clk_ibuf/I	clk	Gowin_PLL/PLLA_inst/CLKOUT0

Max Frequency Summary:

No.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	200.320(MHz)	7	TOP
2	I2S_BCLK	100.000(MHz)	193.424(MHz)	4	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	4.213
Data Arrival Time	6.001
Data Required Time	10.214
From	i2s_tx/n15_s0
To	i2s_tx/daclrc_nege_s0
Launch Clk	I2S_DACLRC[R]
Latch Clk	I2S_BCLK[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
5.000	0.000				I2S_DACLRC
5.000	0.000	tCL	FF	1	I2S_DACLRC_ibuf/I
5.000	0.000	tINS	FF	35	I2S_DACLRC_ibuf/O
5.280	0.280	tNET	FF	1	i2s_tx/n15_s0/I0
5.701	0.421	tINS	FR	1	i2s_tx/n15_s0/F
6.001	0.300	tNET	RR	1	i2s_tx/daclrc_nege_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				I2S_BCLK
10.000	0.000	tCL	RR	1	I2S_BCLK_ibuf/I
10.000	0.000	tINS	RR	204	I2S_BCLK_ibuf/O
10.300	0.300	tNET	RR	1	i2s_tx/daclrc_nege_s0/CLK
10.265	-0.035	tUnc			i2s_tx/daclrc_nege_s0
10.214	-0.051	tSu		1	i2s_tx/daclrc_nege_s0

Path Statistics:

Clock Skew:	0.300
Setup Relationship:	5.000
Logic Level:	2
Arrival Clock Path Delay:	cell: 0.000, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay:	cell: 0.421, 42.058%; route: 0.300, 29.970%; tC2Q: 0.280, 27.972%
Required Clock Path Delay:	cell: 0.000, 100.000%; route: 0.000, 0.000%

Path 2

Path Summary:

Slack	4.221
Data Arrival Time	5.993
Data Required Time	10.214
From	i2s_tx/n13_s0
To	i2s_tx/daclrc_pose_s0
Launch Clk	I2S_DACLRC[R]
Latch Clk	I2S_BCLK[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
5.000	0.000				I2S_DACLRC
5.000	0.000	tCL	FF	1	I2S_DACLRC_ibuf/I
5.000	0.000	tINS	FF	35	I2S_DACLRC_ibuf/O
5.280	0.280	tNET	FF	1	i2s_tx/n13_s0/I1
5.693	0.413	tINS	FR	1	i2s_tx/n13_s0/F
5.993	0.300	tNET	RR	1	i2s_tx/daclrc_pose_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				I2S_BCLK
10.000	0.000	tCL	RR	1	I2S_BCLK_ibuf/I
10.000	0.000	tINS	RR	204	I2S_BCLK_ibuf/O
10.300	0.300	tNET	RR	1	i2s_tx/daclrc_pose_s0/CLK
10.265	-0.035	tUnc			i2s_tx/daclrc_pose_s0
10.214	-0.051	tSu		1	i2s_tx/daclrc_pose_s0

Path Statistics:

Clock Skew:	0.300
Setup Relationship:	5.000
Logic Level:	2
Arrival Clock Path Delay:	cell: 0.000, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay:	cell: 0.413, 41.592%; route: 0.300, 30.211%; tC2Q: 0.280, 28.197%
Required Clock Path Delay:	cell: 0.000, 100.000%; route: 0.000, 0.000%

Path 3

Path Summary:

Slack	4.332
Data Arrival Time	0.906
Data Required Time	5.238
From	i2s_tx/dac_fifo/rddata_tmp_latch_0_s0
To	i2s_tx/dacfifo_rddata_r0_0_s0
Launch Clk	I2S_BCLK[F]
Latch Clk	I2S_DACLRC[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				I2S_BCLK
0.000	0.000	tCL	RR	1	I2S_BCLK_ibuf/I
0.000	0.000	tINS	RR	204	I2S_BCLK_ibuf/O
0.300	0.300	tNET	RR	1	i2s_tx/dac_fifo/rddata_tmp_latch_0_s0/CLK
0.606	0.306	tC2Q	RR	1	i2s_tx/dac_fifo/rddata_tmp_latch_0_s0/Q
0.906	0.300	tNET	RR	1	i2s_tx/dacfifo_rddata_r0_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
5.000	0.000				I2S_DACLRC
5.000	0.000	tCL	FF	1	I2S_DACLRC_ibuf/I
5.000	0.000	tINS	FF	35	I2S_DACLRC_ibuf/O
5.280	0.280	tNET	FF	1	i2s_tx/dacfifo_rddata_r0_0_s0/CLK
5.245	-0.035	tUnc			i2s_tx/dacfifo_rddata_r0_0_s0
5.238	-0.007	tSu		1	i2s_tx/dacfifo_rddata_r0_0_s0

Path Statistics:

Clock Skew:	-0.020
Setup Relationship:	5.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.300, 49.505%; tC2Q: 0.306, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 4

Path Summary:

Slack	4.332
Data Arrival Time	0.906
Data Required Time	5.238
From	i2s_tx/dac_fifo/rddata_tmp_latch_1_s0
To	i2s_tx/dacfifo_rddata_r0_1_s0
Launch Clk	I2S_BCLK[F]
Latch Clk	I2S_DACLRC[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				I2S_BCLK
0.000	0.000	tCL	RR	1	I2S_BCLK_ibuf/I
0.000	0.000	tINS	RR	204	I2S_BCLK_ibuf/O
0.300	0.300	tNET	RR	1	i2s_tx/dac_fifo/rddata_tmp_latch_1_s0/CLK
0.606	0.306	tC2Q	RR	1	i2s_tx/dac_fifo/rddata_tmp_latch_1_s0/Q
0.906	0.300	tNET	RR	1	i2s_tx/dacfifo_rddata_r0_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
5.000	0.000				I2S_DACLRC
5.000	0.000	tCL	FF	1	I2S_DACLRC_ibuf/I
5.000	0.000	tINS	FF	35	I2S_DACLRC_ibuf/O
5.280	0.280	tNET	FF	1	i2s_tx/dacfifo_rddata_r0_1_s0/CLK
5.245	-0.035	tUnc			i2s_tx/dacfifo_rddata_r0_1_s0
5.238	-0.007	tSu		1	i2s_tx/dacfifo_rddata_r0_1_s0

Path Statistics:

Clock Skew:	-0.020
Setup Relationship:	5.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.300, 49.505%; tC2Q: 0.306, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 5

Path Summary:

Slack	4.332
Data Arrival Time	0.906
Data Required Time	5.238
From	i2s_tx/dac_fifo/rddata_tmp_latch_2_s0
To	i2s_tx/dacfifo_rddata_r0_2_s0
Launch Clk	I2S_BCLK[F]
Latch Clk	I2S_DACLRC[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				I2S_BCLK
0.000	0.000	tCL	RR	1	I2S_BCLK_ibuf/I
0.000	0.000	tINS	RR	204	I2S_BCLK_ibuf/O
0.300	0.300	tNET	RR	1	i2s_tx/dac_fifo/rddata_tmp_latch_2_s0/CLK
0.606	0.306	tC2Q	RR	1	i2s_tx/dac_fifo/rddata_tmp_latch_2_s0/Q
0.906	0.300	tNET	RR	1	i2s_tx/dacfifo_rddata_r0_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
5.000	0.000				I2S_DACLRC
5.000	0.000	tCL	FF	1	I2S_DACLRC_ibuf/I
5.000	0.000	tINS	FF	35	I2S_DACLRC_ibuf/O
5.280	0.280	tNET	FF	1	i2s_tx/dacfifo_rddata_r0_2_s0/CLK
5.245	-0.035	tUnc			i2s_tx/dacfifo_rddata_r0_2_s0
5.238	-0.007	tSu		1	i2s_tx/dacfifo_rddata_r0_2_s0

Path Statistics:

Clock Skew:	-0.020
Setup Relationship:	5.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.300, 49.505%; tC2Q: 0.306, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.300, 100.000%