Timing Messages

Report Title Timing Analysis Report
Design File E:\project\Gowin\ch62_audio_loopback\impl\gwsynthesis\audio_loopback.vg
Physical Constraints File E:\project\Gowin\ch62_audio_loopback\src\audio_loopback.cst
Timing Constraint File ---
Tool Version V1.9.9.03 Education (64-bit)
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version A
Created Time Wed Aug 21 09:42:50 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C C2/I1
Hold Delay Model Fast 0.945V 85C C2/I1
Numbers of Paths Analyzed 1558
Numbers of Endpoints Analyzed 1492
Numbers of Falling Endpoints 54
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 1

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I
I2S_BCLK Base 10.000 100.000 0.000 5.000 I2S_BCLK_ibuf/I
I2S_DACLRC Base 10.000 100.000 0.000 5.000 I2S_DACLRC_ibuf/I
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk Generated 83.333 12.000 0.000 41.667 clk_ibuf/I clk Gowin_PLL/PLLA_inst/CLKOUT0

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 168.293(MHz) 8 TOP
2 I2S_BCLK 100.000(MHz) 129.293(MHz) 3 TOP

No timing paths to get frequency of I2S_DACLRC!

No timing paths to get frequency of Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk Setup 0.000 0
clk Hold 0.000 0
I2S_BCLK Setup 0.000 0
I2S_BCLK Hold 0.000 0
I2S_DACLRC Setup 0.000 0
I2S_DACLRC Hold 0.000 0
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk Setup 0.000 0
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.133 i2s_tx/daclrc_pose_s0/Q i2s_tx/dacdat_s1/D I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.011 3.871
2 3.277 i2s_tx/n15_s0/I0 i2s_tx/daclrc_nege_s0/D I2S_DACLRC:[F] I2S_BCLK:[R] 5.000 -1.062 2.699
3 3.300 i2s_tx/n13_s0/I1 i2s_tx/daclrc_pose_s0/D I2S_DACLRC:[F] I2S_BCLK:[R] 5.000 -1.062 2.676
4 5.242 i2s_rx/adcfifo_write_s1/Q i2s_rx/adc_fifo/async_fifo_ctrl_inst/full_s0/D I2S_BCLK:[R] I2S_BCLK:[R] 10.000 -0.005 4.712
5 5.262 i2s_tx/dac_fifo/rddata_tmp_latch_3_s0/Q i2s_tx/dacfifo_rddata_r0_3_s0/D I2S_BCLK:[R] I2S_DACLRC:[F] 5.000 -1.098 0.794
6 5.268 i2s_tx/dac_fifo/rddata_tmp_latch_22_s0/Q i2s_tx/dacfifo_rddata_r0_22_s0/D I2S_BCLK:[R] I2S_DACLRC:[F] 5.000 -1.104 0.794
7 5.280 i2s_tx/dac_fifo/rddata_tmp_latch_9_s0/Q i2s_tx/dacfifo_rddata_r0_9_s0/D I2S_BCLK:[R] I2S_DACLRC:[F] 5.000 -1.100 0.778
8 5.282 i2s_tx/dac_fifo/rddata_tmp_latch_11_s0/Q i2s_tx/dacfifo_rddata_r0_11_s0/D I2S_BCLK:[R] I2S_DACLRC:[F] 5.000 -1.102 0.778
9 3.178 i2s_tx/daclrc_pose_s0/Q i2s_tx/bit_cnt_3_s1/CE I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.012 1.629
10 3.178 i2s_tx/daclrc_pose_s0/Q i2s_tx/bit_cnt_6_s1/CE I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.012 1.629
11 3.185 i2s_tx/daclrc_pose_s0/Q i2s_tx/bit_cnt_1_s1/CE I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.019 1.629
12 3.185 i2s_tx/daclrc_pose_s0/Q i2s_tx/bit_cnt_2_s1/CE I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.019 1.629
13 3.185 i2s_tx/daclrc_pose_s0/Q i2s_tx/bit_cnt_4_s1/CE I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.019 1.629
14 3.185 i2s_tx/daclrc_pose_s0/Q i2s_tx/bit_cnt_5_s1/CE I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.019 1.629
15 3.185 i2s_tx/daclrc_pose_s0/Q i2s_tx/bit_cnt_7_s1/CE I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.019 1.629
16 3.363 i2s_tx/daclrc_nege_s0/Q i2s_tx/state_0_s1/CE I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.012 1.444
17 3.363 i2s_tx/daclrc_nege_s0/Q i2s_tx/state_1_s1/CE I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.012 1.444
18 3.685 i2s_tx/daclrc_nege_s0/Q i2s_tx/bit_cnt_1_s1/D I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.019 1.327
19 3.685 i2s_tx/daclrc_nege_s0/Q i2s_tx/bit_cnt_4_s1/D I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.019 1.327
20 3.685 i2s_tx/daclrc_nege_s0/Q i2s_tx/bit_cnt_5_s1/D I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.019 1.327
21 3.685 i2s_tx/daclrc_nege_s0/Q i2s_tx/bit_cnt_7_s1/D I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.019 1.327
22 3.699 i2s_tx/daclrc_nege_s0/Q i2s_tx/bit_cnt_2_s1/D I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.019 1.313
23 3.860 i2s_tx/daclrc_nege_s0/Q i2s_tx/bit_cnt_0_s1/D I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.012 1.145
24 4.046 i2s_tx/daclrc_nege_s0/Q i2s_tx/bit_cnt_3_s1/D I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.012 0.959
25 4.046 i2s_tx/daclrc_nege_s0/Q i2s_tx/bit_cnt_6_s1/D I2S_BCLK:[R] I2S_BCLK:[F] 5.000 -0.012 0.959

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -0.559 i2s_tx/daclrc_r0_s0/D i2s_tx/daclrc_r0_s0/D I2S_DACLRC:[R] I2S_BCLK:[R] 0.000 -0.511 0.000
2 0.122 dacfifo_writedata_30_s0/Q i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[30] clk:[R] clk:[R] 0.000 0.017 0.320
3 0.122 dacfifo_writedata_26_s0/Q i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[26] clk:[R] clk:[R] 0.000 0.017 0.320
4 0.123 dacfifo_writedata_24_s0/Q i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[24] clk:[R] clk:[R] 0.000 0.005 0.333
5 0.216 i2s_rx/adcfifo_writedata_22_s0/Q i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[22] I2S_BCLK:[R] I2S_BCLK:[R] 0.000 -0.001 0.431
6 0.218 i2s_rx/adcfifo_writedata_14_s0/Q i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[14] I2S_BCLK:[R] I2S_BCLK:[R] 0.000 0.003 0.429
7 0.219 dacfifo_writedata_16_s0/Q i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[16] clk:[R] clk:[R] 0.000 0.005 0.429
8 0.222 i2s_rx/adcfifo_writedata_23_s0/Q i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[23] I2S_BCLK:[R] I2S_BCLK:[R] 0.000 0.007 0.429
9 0.230 dacfifo_writedata_23_s0/Q i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[23] clk:[R] clk:[R] 0.000 0.010 0.435
10 0.230 dacfifo_writedata_20_s0/Q i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[20] clk:[R] clk:[R] 0.000 0.010 0.435
11 0.262 dacfifo_writedata_10_s0/Q i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[10] clk:[R] clk:[R] 0.000 0.013 0.463
12 0.262 dacfifo_writedata_9_s0/Q i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[9] clk:[R] clk:[R] 0.000 0.013 0.463
13 0.269 dacfifo_writedata_17_s0/Q i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[17] clk:[R] clk:[R] 0.000 0.008 0.475
14 0.274 i2s_rx/adcfifo_writedata_1_s0/Q i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[1] I2S_BCLK:[R] I2S_BCLK:[R] 0.000 0.003 0.485
15 0.275 WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/state.GEN_STO_s0/Q WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/state.GEN_STO_s0/D clk:[R] clk:[R] 0.000 0.000 0.300
16 0.275 WM8960_Init/I2C_Init_Dev/i2c_control/Cmd_0_s1/Q WM8960_Init/I2C_Init_Dev/i2c_control/Cmd_0_s1/D clk:[R] clk:[R] 0.000 0.000 0.300
17 0.275 WM8960_Init/I2C_Init_Dev/wrreg_req_s5/Q WM8960_Init/I2C_Init_Dev/wrreg_req_s5/D clk:[R] clk:[R] 0.000 0.000 0.300
18 0.275 dacfifo_writedata_25_s0/Q i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[25] clk:[R] clk:[R] 0.000 0.015 0.475
19 0.278 i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_8_s0/Q i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_8_s0/D I2S_BCLK:[R] I2S_BCLK:[R] 0.000 0.000 0.303
20 0.278 WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_2_s3/Q WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_2_s3/D clk:[R] clk:[R] 0.000 0.000 0.303
21 0.278 WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_4_s4/Q WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_4_s4/D clk:[R] clk:[R] 0.000 0.000 0.303
22 0.278 WM8960_Init/I2C_Init_Dev/i2c_control/cnt_0_s0/Q WM8960_Init/I2C_Init_Dev/i2c_control/cnt_0_s0/D clk:[R] clk:[R] 0.000 0.000 0.303
23 0.278 WM8960_Init/I2C_Init_Dev/i2c_control/cnt_1_s0/Q WM8960_Init/I2C_Init_Dev/i2c_control/cnt_1_s0/D clk:[R] clk:[R] 0.000 0.000 0.303
24 0.278 WM8960_Init/I2C_Init_Dev/cnt_4_s1/Q WM8960_Init/I2C_Init_Dev/cnt_4_s1/D clk:[R] clk:[R] 0.000 0.000 0.303
25 0.287 dacfifo_writedata_6_s0/Q i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[6] clk:[R] clk:[R] 0.000 0.013 0.488

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 3.563 4.425 0.862 Low Pulse Width I2S_BCLK i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
2 3.567 4.429 0.862 Low Pulse Width I2S_BCLK i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
3 3.573 4.435 0.862 High Pulse Width I2S_BCLK i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
4 3.577 4.439 0.862 High Pulse Width I2S_BCLK i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
5 3.832 4.032 0.200 Low Pulse Width I2S_DACLRC i2s_tx/dacfifo_rddata_r0_23_s0
6 3.832 4.032 0.200 Low Pulse Width I2S_DACLRC i2s_tx/dacfifo_rddata_r0_14_s0
7 3.832 4.032 0.200 Low Pulse Width I2S_DACLRC i2s_tx/dacfifo_rddata_r0_25_s0
8 3.832 4.032 0.200 Low Pulse Width I2S_DACLRC i2s_tx/dacfifo_rddata_r0_24_s0
9 3.834 4.034 0.200 Low Pulse Width I2S_DACLRC i2s_tx/dacfifo_rddata_r0_30_s0
10 3.834 4.034 0.200 Low Pulse Width I2S_DACLRC i2s_tx/dacfifo_rddata_r0_29_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.133
Data Arrival Time 5.524
Data Required Time 6.657
From i2s_tx/daclrc_pose_s0
To i2s_tx/dacdat_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[3][A] i2s_tx/daclrc_pose_s0/CLK
1.959 0.306 tC2Q RR 4 R22C39[3][A] i2s_tx/daclrc_pose_s0/Q
2.423 0.464 tNET RR 1 R23C41[3][B] i2s_tx/n147_s5/I0
2.755 0.332 tINS RR 1 R23C41[3][B] i2s_tx/n147_s5/F
3.033 0.278 tNET RR 1 R22C40[3][B] i2s_tx/n147_s4/I1
3.431 0.398 tINS RR 1 R22C40[3][B] i2s_tx/n147_s4/F
5.524 2.093 tNET RR 1 IOT15[A] i2s_tx/dacdat_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.664 1.072 tNET FF 1 IOT15[A] i2s_tx/dacdat_s1/CLK
6.657 -0.007 tSu 1 IOT15[A] i2s_tx/dacdat_s1

Path Statistics:

Clock Skew 0.011
Setup Relationship 5.000
Logic Level 3
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.730, 18.858%; route: 2.835, 73.237%; tC2Q: 0.306, 7.905%
Required Clock Path Delay cell: 0.591, 35.537%; route: 1.072, 64.463%

Path2

Path Summary:

Slack 3.277
Data Arrival Time 8.290
Data Required Time 11.567
From i2s_tx/n15_s0
To i2s_tx/daclrc_nege_s0
Launch Clk I2S_DACLRC:[F]
Latch Clk I2S_BCLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_DACLRC
5.000 0.000 tCL FF 1 IOT21[B] I2S_DACLRC_ibuf/I
5.591 0.591 tINS FF 35 IOT21[B] I2S_DACLRC_ibuf/O
7.869 2.278 tNET FF 1 R22C39[2][B] i2s_tx/n15_s0/I0
8.290 0.421 tINS FR 1 R22C39[2][B] i2s_tx/n15_s0/F
8.290 0.000 tNET RR 1 R22C39[2][B] i2s_tx/daclrc_nege_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 I2S_BCLK
10.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
10.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
11.653 1.066 tNET RR 1 R22C39[2][B] i2s_tx/daclrc_nege_s0/CLK
11.618 -0.035 tUnc i2s_tx/daclrc_nege_s0
11.567 -0.051 tSu 1 R22C39[2][B] i2s_tx/daclrc_nege_s0

Path Statistics:

Clock Skew 1.062
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.591, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.421, 15.600%; route: 0.000, 0.000%; tC2Q: 2.278, 84.400%
Required Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%

Path3

Path Summary:

Slack 3.300
Data Arrival Time 8.267
Data Required Time 11.567
From i2s_tx/n13_s0
To i2s_tx/daclrc_pose_s0
Launch Clk I2S_DACLRC:[F]
Latch Clk I2S_BCLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_DACLRC
5.000 0.000 tCL FF 1 IOT21[B] I2S_DACLRC_ibuf/I
5.591 0.591 tINS FF 35 IOT21[B] I2S_DACLRC_ibuf/O
7.869 2.278 tNET FF 1 R22C39[3][A] i2s_tx/n13_s0/I1
8.267 0.398 tINS FR 1 R22C39[3][A] i2s_tx/n13_s0/F
8.267 0.000 tNET RR 1 R22C39[3][A] i2s_tx/daclrc_pose_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 I2S_BCLK
10.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
10.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
11.653 1.066 tNET RR 1 R22C39[3][A] i2s_tx/daclrc_pose_s0/CLK
11.618 -0.035 tUnc i2s_tx/daclrc_pose_s0
11.567 -0.051 tSu 1 R22C39[3][A] i2s_tx/daclrc_pose_s0

Path Statistics:

Clock Skew 1.062
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.591, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.398, 14.874%; route: 0.000, 0.000%; tC2Q: 2.278, 85.126%
Required Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%

Path4

Path Summary:

Slack 5.242
Data Arrival Time 6.335
Data Required Time 11.577
From i2s_rx/adcfifo_write_s1
To i2s_rx/adc_fifo/async_fifo_ctrl_inst/full_s0
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.623 1.036 tNET RR 1 R13C52[1][A] i2s_rx/adcfifo_write_s1/CLK
1.929 0.306 tC2Q RR 4 R13C52[1][A] i2s_rx/adcfifo_write_s1/Q
2.494 0.565 tNET RR 1 R17C48[1][A] i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_next_1_s4/I1
2.907 0.413 tINS RR 3 R17C48[1][A] i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_next_1_s4/F
3.037 0.130 tNET RR 1 R18C48[3][A] i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_next_4_s4/I0
3.269 0.232 tINS RF 5 R18C48[3][A] i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_next_4_s4/F
3.399 0.130 tNET FF 1 R18C47[2][A] i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_next_5_s3/I0
3.812 0.413 tINS FR 2 R18C47[2][A] i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_next_5_s3/F
4.813 1.001 tNET RR 2 R20C46[2][B] i2s_rx/adc_fifo/async_fifo_ctrl_inst/n293_s0/I1
5.263 0.450 tINS RF 1 R20C46[2][B] i2s_rx/adc_fifo/async_fifo_ctrl_inst/n293_s0/COUT
5.263 0.000 tNET FF 2 R20C47[0][A] i2s_rx/adc_fifo/async_fifo_ctrl_inst/n294_s0/CIN
5.303 0.040 tINS FR 1 R20C47[0][A] i2s_rx/adc_fifo/async_fifo_ctrl_inst/n294_s0/COUT
5.303 0.000 tNET RR 2 R20C47[0][B] i2s_rx/adc_fifo/async_fifo_ctrl_inst/n295_s0/CIN
5.343 0.040 tINS RR 1 R20C47[0][B] i2s_rx/adc_fifo/async_fifo_ctrl_inst/n295_s0/COUT
6.125 0.782 tNET RR 1 R17C47[1][B] i2s_rx/adc_fifo/async_fifo_ctrl_inst/n297_s0/I0
6.335 0.210 tINS RR 1 R17C47[1][B] i2s_rx/adc_fifo/async_fifo_ctrl_inst/n297_s0/F
6.335 0.000 tNET RR 1 R17C47[1][B] i2s_rx/adc_fifo/async_fifo_ctrl_inst/full_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 I2S_BCLK
10.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
10.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
11.628 1.041 tNET RR 1 R17C47[1][B] i2s_rx/adc_fifo/async_fifo_ctrl_inst/full_s0/CLK
11.577 -0.051 tSu 1 R17C47[1][B] i2s_rx/adc_fifo/async_fifo_ctrl_inst/full_s0

Path Statistics:

Clock Skew 0.005
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.587, 36.166%; route: 1.036, 63.834%
Arrival Data Path Delay cell: 1.798, 38.158%; route: 2.608, 55.348%; tC2Q: 0.306, 6.494%
Required Clock Path Delay cell: 0.587, 36.055%; route: 1.041, 63.945%

Path5

Path Summary:

Slack 5.262
Data Arrival Time 2.456
Data Required Time 7.718
From i2s_tx/dac_fifo/rddata_tmp_latch_3_s0
To i2s_tx/dacfifo_rddata_r0_3_s0
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_DACLRC:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.662 1.075 tNET RR 1 R25C41[2][A] i2s_tx/dac_fifo/rddata_tmp_latch_3_s0/CLK
1.968 0.306 tC2Q RR 1 R25C41[2][A] i2s_tx/dac_fifo/rddata_tmp_latch_3_s0/Q
2.456 0.488 tNET RR 1 R23C41[1][B] i2s_tx/dacfifo_rddata_r0_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_DACLRC
5.000 0.000 tCL FF 1 IOT21[B] I2S_DACLRC_ibuf/I
5.591 0.591 tINS FF 35 IOT21[B] I2S_DACLRC_ibuf/O
7.760 2.169 tNET FF 1 R23C41[1][B] i2s_tx/dacfifo_rddata_r0_3_s0/CLK
7.725 -0.035 tUnc i2s_tx/dacfifo_rddata_r0_3_s0
7.718 -0.007 tSu 1 R23C41[1][B] i2s_tx/dacfifo_rddata_r0_3_s0

Path Statistics:

Clock Skew 1.098
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.587, 35.317%; route: 1.075, 64.683%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.488, 61.461%; tC2Q: 0.306, 38.539%
Required Clock Path Delay cell: 0.591, 21.420%; route: 2.169, 78.580%

Path6

Path Summary:

Slack 5.268
Data Arrival Time 2.448
Data Required Time 7.716
From i2s_tx/dac_fifo/rddata_tmp_latch_22_s0
To i2s_tx/dacfifo_rddata_r0_22_s0
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_DACLRC:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.654 1.067 tNET RR 1 R25C40[2][B] i2s_tx/dac_fifo/rddata_tmp_latch_22_s0/CLK
1.960 0.306 tC2Q RR 1 R25C40[2][B] i2s_tx/dac_fifo/rddata_tmp_latch_22_s0/Q
2.448 0.488 tNET RR 1 R24C39[0][B] i2s_tx/dacfifo_rddata_r0_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_DACLRC
5.000 0.000 tCL FF 1 IOT21[B] I2S_DACLRC_ibuf/I
5.591 0.591 tINS FF 35 IOT21[B] I2S_DACLRC_ibuf/O
7.758 2.167 tNET FF 1 R24C39[0][B] i2s_tx/dacfifo_rddata_r0_22_s0/CLK
7.723 -0.035 tUnc i2s_tx/dacfifo_rddata_r0_22_s0
7.716 -0.007 tSu 1 R24C39[0][B] i2s_tx/dacfifo_rddata_r0_22_s0

Path Statistics:

Clock Skew 1.104
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.587, 35.477%; route: 1.067, 64.523%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.488, 61.461%; tC2Q: 0.306, 38.539%
Required Clock Path Delay cell: 0.591, 21.438%; route: 2.167, 78.562%

Path7

Path Summary:

Slack 5.280
Data Arrival Time 2.427
Data Required Time 7.706
From i2s_tx/dac_fifo/rddata_tmp_latch_9_s0
To i2s_tx/dacfifo_rddata_r0_9_s0
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_DACLRC:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.649 1.062 tNET RR 1 R26C42[0][A] i2s_tx/dac_fifo/rddata_tmp_latch_9_s0/CLK
1.955 0.306 tC2Q RR 1 R26C42[0][A] i2s_tx/dac_fifo/rddata_tmp_latch_9_s0/Q
2.427 0.472 tNET RR 1 R25C42[2][B] i2s_tx/dacfifo_rddata_r0_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_DACLRC
5.000 0.000 tCL FF 1 IOT21[B] I2S_DACLRC_ibuf/I
5.591 0.591 tINS FF 35 IOT21[B] I2S_DACLRC_ibuf/O
7.748 2.157 tNET FF 1 R25C42[2][B] i2s_tx/dacfifo_rddata_r0_9_s0/CLK
7.713 -0.035 tUnc i2s_tx/dacfifo_rddata_r0_9_s0
7.706 -0.007 tSu 1 R25C42[2][B] i2s_tx/dacfifo_rddata_r0_9_s0

Path Statistics:

Clock Skew 1.100
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.587, 35.601%; route: 1.062, 64.399%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.472, 60.668%; tC2Q: 0.306, 39.332%
Required Clock Path Delay cell: 0.591, 21.514%; route: 2.157, 78.486%

Path8

Path Summary:

Slack 5.282
Data Arrival Time 2.427
Data Required Time 7.708
From i2s_tx/dac_fifo/rddata_tmp_latch_11_s0
To i2s_tx/dacfifo_rddata_r0_11_s0
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_DACLRC:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.649 1.062 tNET RR 1 R24C43[0][B] i2s_tx/dac_fifo/rddata_tmp_latch_11_s0/CLK
1.955 0.306 tC2Q RR 1 R24C43[0][B] i2s_tx/dac_fifo/rddata_tmp_latch_11_s0/Q
2.427 0.472 tNET RR 1 R24C42[2][B] i2s_tx/dacfifo_rddata_r0_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_DACLRC
5.000 0.000 tCL FF 1 IOT21[B] I2S_DACLRC_ibuf/I
5.591 0.591 tINS FF 35 IOT21[B] I2S_DACLRC_ibuf/O
7.750 2.159 tNET FF 1 R24C42[2][B] i2s_tx/dacfifo_rddata_r0_11_s0/CLK
7.715 -0.035 tUnc i2s_tx/dacfifo_rddata_r0_11_s0
7.708 -0.007 tSu 1 R24C42[2][B] i2s_tx/dacfifo_rddata_r0_11_s0

Path Statistics:

Clock Skew 1.102
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.587, 35.595%; route: 1.062, 64.405%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.472, 60.668%; tC2Q: 0.306, 39.332%
Required Clock Path Delay cell: 0.591, 21.496%; route: 2.159, 78.504%

Path9

Path Summary:

Slack 3.178
Data Arrival Time 3.282
Data Required Time 6.459
From i2s_tx/daclrc_pose_s0
To i2s_tx/bit_cnt_3_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[3][A] i2s_tx/daclrc_pose_s0/CLK
1.959 0.306 tC2Q RR 4 R22C39[3][A] i2s_tx/daclrc_pose_s0/Q
2.271 0.312 tNET RR 1 R22C42[1][A] i2s_tx/bit_cnt_7_s6/I0
2.692 0.421 tINS RR 7 R22C42[1][A] i2s_tx/bit_cnt_7_s6/F
3.282 0.590 tNET RR 1 R22C42[1][B] i2s_tx/bit_cnt_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.664 1.073 tNET FF 1 R22C42[1][B] i2s_tx/bit_cnt_3_s1/CLK
6.459 -0.205 tSu 1 R22C42[1][B] i2s_tx/bit_cnt_3_s1

Path Statistics:

Clock Skew 0.012
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.421, 25.844%; route: 0.902, 55.371%; tC2Q: 0.306, 18.785%
Required Clock Path Delay cell: 0.591, 35.521%; route: 1.073, 64.479%

Path10

Path Summary:

Slack 3.178
Data Arrival Time 3.282
Data Required Time 6.459
From i2s_tx/daclrc_pose_s0
To i2s_tx/bit_cnt_6_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[3][A] i2s_tx/daclrc_pose_s0/CLK
1.959 0.306 tC2Q RR 4 R22C39[3][A] i2s_tx/daclrc_pose_s0/Q
2.271 0.312 tNET RR 1 R22C42[1][A] i2s_tx/bit_cnt_7_s6/I0
2.692 0.421 tINS RR 7 R22C42[1][A] i2s_tx/bit_cnt_7_s6/F
3.282 0.590 tNET RR 1 R22C42[0][A] i2s_tx/bit_cnt_6_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.664 1.073 tNET FF 1 R22C42[0][A] i2s_tx/bit_cnt_6_s1/CLK
6.459 -0.205 tSu 1 R22C42[0][A] i2s_tx/bit_cnt_6_s1

Path Statistics:

Clock Skew 0.012
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.421, 25.844%; route: 0.902, 55.371%; tC2Q: 0.306, 18.785%
Required Clock Path Delay cell: 0.591, 35.521%; route: 1.073, 64.479%

Path11

Path Summary:

Slack 3.185
Data Arrival Time 3.282
Data Required Time 6.467
From i2s_tx/daclrc_pose_s0
To i2s_tx/bit_cnt_1_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[3][A] i2s_tx/daclrc_pose_s0/CLK
1.959 0.306 tC2Q RR 4 R22C39[3][A] i2s_tx/daclrc_pose_s0/Q
2.271 0.312 tNET RR 1 R22C42[1][A] i2s_tx/bit_cnt_7_s6/I0
2.692 0.421 tINS RR 7 R22C42[1][A] i2s_tx/bit_cnt_7_s6/F
3.282 0.590 tNET RR 1 R22C41[0][B] i2s_tx/bit_cnt_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.672 1.081 tNET FF 1 R22C41[0][B] i2s_tx/bit_cnt_1_s1/CLK
6.467 -0.205 tSu 1 R22C41[0][B] i2s_tx/bit_cnt_1_s1

Path Statistics:

Clock Skew 0.019
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.421, 25.844%; route: 0.902, 55.371%; tC2Q: 0.306, 18.785%
Required Clock Path Delay cell: 0.591, 35.362%; route: 1.081, 64.638%

Path12

Path Summary:

Slack 3.185
Data Arrival Time 3.282
Data Required Time 6.467
From i2s_tx/daclrc_pose_s0
To i2s_tx/bit_cnt_2_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[3][A] i2s_tx/daclrc_pose_s0/CLK
1.959 0.306 tC2Q RR 4 R22C39[3][A] i2s_tx/daclrc_pose_s0/Q
2.271 0.312 tNET RR 1 R22C42[1][A] i2s_tx/bit_cnt_7_s6/I0
2.692 0.421 tINS RR 7 R22C42[1][A] i2s_tx/bit_cnt_7_s6/F
3.282 0.590 tNET RR 1 R22C41[1][A] i2s_tx/bit_cnt_2_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.672 1.081 tNET FF 1 R22C41[1][A] i2s_tx/bit_cnt_2_s1/CLK
6.467 -0.205 tSu 1 R22C41[1][A] i2s_tx/bit_cnt_2_s1

Path Statistics:

Clock Skew 0.019
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.421, 25.844%; route: 0.902, 55.371%; tC2Q: 0.306, 18.785%
Required Clock Path Delay cell: 0.591, 35.362%; route: 1.081, 64.638%

Path13

Path Summary:

Slack 3.185
Data Arrival Time 3.282
Data Required Time 6.467
From i2s_tx/daclrc_pose_s0
To i2s_tx/bit_cnt_4_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[3][A] i2s_tx/daclrc_pose_s0/CLK
1.959 0.306 tC2Q RR 4 R22C39[3][A] i2s_tx/daclrc_pose_s0/Q
2.271 0.312 tNET RR 1 R22C42[1][A] i2s_tx/bit_cnt_7_s6/I0
2.692 0.421 tINS RR 7 R22C42[1][A] i2s_tx/bit_cnt_7_s6/F
3.282 0.590 tNET RR 1 R22C41[1][B] i2s_tx/bit_cnt_4_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.672 1.081 tNET FF 1 R22C41[1][B] i2s_tx/bit_cnt_4_s1/CLK
6.467 -0.205 tSu 1 R22C41[1][B] i2s_tx/bit_cnt_4_s1

Path Statistics:

Clock Skew 0.019
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.421, 25.844%; route: 0.902, 55.371%; tC2Q: 0.306, 18.785%
Required Clock Path Delay cell: 0.591, 35.362%; route: 1.081, 64.638%

Path14

Path Summary:

Slack 3.185
Data Arrival Time 3.282
Data Required Time 6.467
From i2s_tx/daclrc_pose_s0
To i2s_tx/bit_cnt_5_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[3][A] i2s_tx/daclrc_pose_s0/CLK
1.959 0.306 tC2Q RR 4 R22C39[3][A] i2s_tx/daclrc_pose_s0/Q
2.271 0.312 tNET RR 1 R22C42[1][A] i2s_tx/bit_cnt_7_s6/I0
2.692 0.421 tINS RR 7 R22C42[1][A] i2s_tx/bit_cnt_7_s6/F
3.282 0.590 tNET RR 1 R22C41[2][B] i2s_tx/bit_cnt_5_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.672 1.081 tNET FF 1 R22C41[2][B] i2s_tx/bit_cnt_5_s1/CLK
6.467 -0.205 tSu 1 R22C41[2][B] i2s_tx/bit_cnt_5_s1

Path Statistics:

Clock Skew 0.019
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.421, 25.844%; route: 0.902, 55.371%; tC2Q: 0.306, 18.785%
Required Clock Path Delay cell: 0.591, 35.362%; route: 1.081, 64.638%

Path15

Path Summary:

Slack 3.185
Data Arrival Time 3.282
Data Required Time 6.467
From i2s_tx/daclrc_pose_s0
To i2s_tx/bit_cnt_7_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[3][A] i2s_tx/daclrc_pose_s0/CLK
1.959 0.306 tC2Q RR 4 R22C39[3][A] i2s_tx/daclrc_pose_s0/Q
2.271 0.312 tNET RR 1 R22C42[1][A] i2s_tx/bit_cnt_7_s6/I0
2.692 0.421 tINS RR 7 R22C42[1][A] i2s_tx/bit_cnt_7_s6/F
3.282 0.590 tNET RR 1 R22C41[2][A] i2s_tx/bit_cnt_7_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.672 1.081 tNET FF 1 R22C41[2][A] i2s_tx/bit_cnt_7_s1/CLK
6.467 -0.205 tSu 1 R22C41[2][A] i2s_tx/bit_cnt_7_s1

Path Statistics:

Clock Skew 0.019
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.421, 25.844%; route: 0.902, 55.371%; tC2Q: 0.306, 18.785%
Required Clock Path Delay cell: 0.591, 35.362%; route: 1.081, 64.638%

Path16

Path Summary:

Slack 3.363
Data Arrival Time 3.097
Data Required Time 6.459
From i2s_tx/daclrc_nege_s0
To i2s_tx/state_0_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[2][B] i2s_tx/daclrc_nege_s0/CLK
1.959 0.306 tC2Q RR 7 R22C39[2][B] i2s_tx/daclrc_nege_s0/Q
2.117 0.158 tNET RR 1 R22C41[3][B] i2s_tx/state_1_s4/I2
2.515 0.398 tINS RR 1 R22C41[3][B] i2s_tx/state_1_s4/F
2.777 0.262 tNET RR 1 R22C40[2][B] i2s_tx/state_1_s3/I1
2.987 0.210 tINS RR 2 R22C40[2][B] i2s_tx/state_1_s3/F
3.097 0.110 tNET RR 1 R22C40[1][A] i2s_tx/state_0_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.664 1.073 tNET FF 1 R22C40[1][A] i2s_tx/state_0_s1/CLK
6.459 -0.205 tSu 1 R22C40[1][A] i2s_tx/state_0_s1

Path Statistics:

Clock Skew 0.012
Setup Relationship 5.000
Logic Level 3
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.608, 42.105%; route: 0.530, 36.704%; tC2Q: 0.306, 21.191%
Required Clock Path Delay cell: 0.591, 35.521%; route: 1.073, 64.479%

Path17

Path Summary:

Slack 3.363
Data Arrival Time 3.097
Data Required Time 6.459
From i2s_tx/daclrc_nege_s0
To i2s_tx/state_1_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[2][B] i2s_tx/daclrc_nege_s0/CLK
1.959 0.306 tC2Q RR 7 R22C39[2][B] i2s_tx/daclrc_nege_s0/Q
2.117 0.158 tNET RR 1 R22C41[3][B] i2s_tx/state_1_s4/I2
2.515 0.398 tINS RR 1 R22C41[3][B] i2s_tx/state_1_s4/F
2.777 0.262 tNET RR 1 R22C40[2][B] i2s_tx/state_1_s3/I1
2.987 0.210 tINS RR 2 R22C40[2][B] i2s_tx/state_1_s3/F
3.097 0.110 tNET RR 1 R22C40[1][B] i2s_tx/state_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.664 1.073 tNET FF 1 R22C40[1][B] i2s_tx/state_1_s1/CLK
6.459 -0.205 tSu 1 R22C40[1][B] i2s_tx/state_1_s1

Path Statistics:

Clock Skew 0.012
Setup Relationship 5.000
Logic Level 3
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.608, 42.105%; route: 0.530, 36.704%; tC2Q: 0.306, 21.191%
Required Clock Path Delay cell: 0.591, 35.521%; route: 1.073, 64.479%

Path18

Path Summary:

Slack 3.685
Data Arrival Time 2.980
Data Required Time 6.665
From i2s_tx/daclrc_nege_s0
To i2s_tx/bit_cnt_1_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[2][B] i2s_tx/daclrc_nege_s0/CLK
1.959 0.306 tC2Q RR 7 R22C39[2][B] i2s_tx/daclrc_nege_s0/Q
2.089 0.130 tNET RR 1 R22C40[3][A] i2s_tx/n68_s4/I0
2.421 0.332 tINS RR 7 R22C40[3][A] i2s_tx/n68_s4/F
2.559 0.138 tNET RR 1 R22C41[0][B] i2s_tx/n74_s1/I0
2.980 0.421 tINS RR 1 R22C41[0][B] i2s_tx/n74_s1/F
2.980 0.000 tNET RR 1 R22C41[0][B] i2s_tx/bit_cnt_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.672 1.081 tNET FF 1 R22C41[0][B] i2s_tx/bit_cnt_1_s1/CLK
6.665 -0.007 tSu 1 R22C41[0][B] i2s_tx/bit_cnt_1_s1

Path Statistics:

Clock Skew 0.019
Setup Relationship 5.000
Logic Level 3
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.753, 56.745%; route: 0.268, 20.196%; tC2Q: 0.306, 23.060%
Required Clock Path Delay cell: 0.591, 35.362%; route: 1.081, 64.638%

Path19

Path Summary:

Slack 3.685
Data Arrival Time 2.980
Data Required Time 6.665
From i2s_tx/daclrc_nege_s0
To i2s_tx/bit_cnt_4_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[2][B] i2s_tx/daclrc_nege_s0/CLK
1.959 0.306 tC2Q RR 7 R22C39[2][B] i2s_tx/daclrc_nege_s0/Q
2.089 0.130 tNET RR 1 R22C40[3][A] i2s_tx/n68_s4/I0
2.421 0.332 tINS RR 7 R22C40[3][A] i2s_tx/n68_s4/F
2.559 0.138 tNET RR 1 R22C41[1][B] i2s_tx/n71_s1/I0
2.980 0.421 tINS RR 1 R22C41[1][B] i2s_tx/n71_s1/F
2.980 0.000 tNET RR 1 R22C41[1][B] i2s_tx/bit_cnt_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.672 1.081 tNET FF 1 R22C41[1][B] i2s_tx/bit_cnt_4_s1/CLK
6.665 -0.007 tSu 1 R22C41[1][B] i2s_tx/bit_cnt_4_s1

Path Statistics:

Clock Skew 0.019
Setup Relationship 5.000
Logic Level 3
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.753, 56.745%; route: 0.268, 20.196%; tC2Q: 0.306, 23.060%
Required Clock Path Delay cell: 0.591, 35.362%; route: 1.081, 64.638%

Path20

Path Summary:

Slack 3.685
Data Arrival Time 2.980
Data Required Time 6.665
From i2s_tx/daclrc_nege_s0
To i2s_tx/bit_cnt_5_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[2][B] i2s_tx/daclrc_nege_s0/CLK
1.959 0.306 tC2Q RR 7 R22C39[2][B] i2s_tx/daclrc_nege_s0/Q
2.089 0.130 tNET RR 1 R22C40[3][A] i2s_tx/n68_s4/I0
2.421 0.332 tINS RR 7 R22C40[3][A] i2s_tx/n68_s4/F
2.559 0.138 tNET RR 1 R22C41[2][B] i2s_tx/n70_s3/I0
2.980 0.421 tINS RR 1 R22C41[2][B] i2s_tx/n70_s3/F
2.980 0.000 tNET RR 1 R22C41[2][B] i2s_tx/bit_cnt_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.672 1.081 tNET FF 1 R22C41[2][B] i2s_tx/bit_cnt_5_s1/CLK
6.665 -0.007 tSu 1 R22C41[2][B] i2s_tx/bit_cnt_5_s1

Path Statistics:

Clock Skew 0.019
Setup Relationship 5.000
Logic Level 3
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.753, 56.745%; route: 0.268, 20.196%; tC2Q: 0.306, 23.060%
Required Clock Path Delay cell: 0.591, 35.362%; route: 1.081, 64.638%

Path21

Path Summary:

Slack 3.685
Data Arrival Time 2.980
Data Required Time 6.665
From i2s_tx/daclrc_nege_s0
To i2s_tx/bit_cnt_7_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[2][B] i2s_tx/daclrc_nege_s0/CLK
1.959 0.306 tC2Q RR 7 R22C39[2][B] i2s_tx/daclrc_nege_s0/Q
2.089 0.130 tNET RR 1 R22C40[3][A] i2s_tx/n68_s4/I0
2.421 0.332 tINS RR 7 R22C40[3][A] i2s_tx/n68_s4/F
2.559 0.138 tNET RR 1 R22C41[2][A] i2s_tx/n68_s1/I0
2.980 0.421 tINS RR 1 R22C41[2][A] i2s_tx/n68_s1/F
2.980 0.000 tNET RR 1 R22C41[2][A] i2s_tx/bit_cnt_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.672 1.081 tNET FF 1 R22C41[2][A] i2s_tx/bit_cnt_7_s1/CLK
6.665 -0.007 tSu 1 R22C41[2][A] i2s_tx/bit_cnt_7_s1

Path Statistics:

Clock Skew 0.019
Setup Relationship 5.000
Logic Level 3
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.753, 56.745%; route: 0.268, 20.196%; tC2Q: 0.306, 23.060%
Required Clock Path Delay cell: 0.591, 35.362%; route: 1.081, 64.638%

Path22

Path Summary:

Slack 3.699
Data Arrival Time 2.966
Data Required Time 6.665
From i2s_tx/daclrc_nege_s0
To i2s_tx/bit_cnt_2_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[2][B] i2s_tx/daclrc_nege_s0/CLK
1.959 0.306 tC2Q RR 7 R22C39[2][B] i2s_tx/daclrc_nege_s0/Q
2.089 0.130 tNET RR 1 R22C40[3][A] i2s_tx/n68_s4/I0
2.421 0.332 tINS RR 7 R22C40[3][A] i2s_tx/n68_s4/F
2.553 0.132 tNET RR 1 R22C41[1][A] i2s_tx/n73_s3/I0
2.966 0.413 tINS RR 1 R22C41[1][A] i2s_tx/n73_s3/F
2.966 0.000 tNET RR 1 R22C41[1][A] i2s_tx/bit_cnt_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.672 1.081 tNET FF 1 R22C41[1][A] i2s_tx/bit_cnt_2_s1/CLK
6.665 -0.007 tSu 1 R22C41[1][A] i2s_tx/bit_cnt_2_s1

Path Statistics:

Clock Skew 0.019
Setup Relationship 5.000
Logic Level 3
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.745, 56.740%; route: 0.262, 19.954%; tC2Q: 0.306, 23.305%
Required Clock Path Delay cell: 0.591, 35.362%; route: 1.081, 64.638%

Path23

Path Summary:

Slack 3.860
Data Arrival Time 2.798
Data Required Time 6.657
From i2s_tx/daclrc_nege_s0
To i2s_tx/bit_cnt_0_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[2][B] i2s_tx/daclrc_nege_s0/CLK
1.959 0.306 tC2Q RR 7 R22C39[2][B] i2s_tx/daclrc_nege_s0/Q
2.089 0.130 tNET RR 1 R22C40[3][A] i2s_tx/n68_s4/I0
2.421 0.332 tINS RR 7 R22C40[3][A] i2s_tx/n68_s4/F
2.429 0.008 tNET RR 1 R22C40[2][A] i2s_tx/n146_s6/I0
2.798 0.369 tINS RR 1 R22C40[2][A] i2s_tx/n146_s6/F
2.798 0.000 tNET RR 1 R22C40[2][A] i2s_tx/bit_cnt_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.664 1.073 tNET FF 1 R22C40[2][A] i2s_tx/bit_cnt_0_s1/CLK
6.657 -0.007 tSu 1 R22C40[2][A] i2s_tx/bit_cnt_0_s1

Path Statistics:

Clock Skew 0.012
Setup Relationship 5.000
Logic Level 3
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.701, 61.223%; route: 0.138, 12.052%; tC2Q: 0.306, 26.725%
Required Clock Path Delay cell: 0.591, 35.521%; route: 1.073, 64.479%

Path24

Path Summary:

Slack 4.046
Data Arrival Time 2.612
Data Required Time 6.657
From i2s_tx/daclrc_nege_s0
To i2s_tx/bit_cnt_3_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[2][B] i2s_tx/daclrc_nege_s0/CLK
1.959 0.306 tC2Q RR 7 R22C39[2][B] i2s_tx/daclrc_nege_s0/Q
2.243 0.284 tNET RR 1 R22C42[1][B] i2s_tx/n72_s3/I0
2.612 0.369 tINS RR 1 R22C42[1][B] i2s_tx/n72_s3/F
2.612 0.000 tNET RR 1 R22C42[1][B] i2s_tx/bit_cnt_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.664 1.073 tNET FF 1 R22C42[1][B] i2s_tx/bit_cnt_3_s1/CLK
6.657 -0.007 tSu 1 R22C42[1][B] i2s_tx/bit_cnt_3_s1

Path Statistics:

Clock Skew 0.012
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.369, 38.478%; route: 0.284, 29.614%; tC2Q: 0.306, 31.908%
Required Clock Path Delay cell: 0.591, 35.521%; route: 1.073, 64.479%

Path25

Path Summary:

Slack 4.046
Data Arrival Time 2.612
Data Required Time 6.657
From i2s_tx/daclrc_nege_s0
To i2s_tx/bit_cnt_6_s1
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.587 0.587 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.653 1.066 tNET RR 1 R22C39[2][B] i2s_tx/daclrc_nege_s0/CLK
1.959 0.306 tC2Q RR 7 R22C39[2][B] i2s_tx/daclrc_nege_s0/Q
2.243 0.284 tNET RR 1 R22C42[0][A] i2s_tx/n69_s3/I0
2.612 0.369 tINS RR 1 R22C42[0][A] i2s_tx/n69_s3/F
2.612 0.000 tNET RR 1 R22C42[0][A] i2s_tx/bit_cnt_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF 1 IOT3[B] I2S_BCLK_ibuf/I
5.591 0.591 tINS FF 204 IOT3[B] I2S_BCLK_ibuf/O
6.664 1.073 tNET FF 1 R22C42[0][A] i2s_tx/bit_cnt_6_s1/CLK
6.657 -0.007 tSu 1 R22C42[0][A] i2s_tx/bit_cnt_6_s1

Path Statistics:

Clock Skew 0.012
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.587, 35.509%; route: 1.066, 64.491%
Arrival Data Path Delay cell: 0.369, 38.478%; route: 0.284, 29.614%; tC2Q: 0.306, 31.908%
Required Clock Path Delay cell: 0.591, 35.521%; route: 1.073, 64.479%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -0.559
Data Arrival Time 0.581
Data Required Time 1.139
From i2s_tx/daclrc_r0_s0
To i2s_tx/daclrc_r0_s0
Launch Clk I2S_DACLRC:[R]
Latch Clk I2S_BCLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_DACLRC
0.000 0.000 tCL RR 1 IOT21[B] I2S_DACLRC_ibuf/I
0.581 0.581 tINS RR 35 IOT21[B] I2S_DACLRC_ibuf/O
0.581 0.000 tNET RR 1 IOT21[B] i2s_tx/daclrc_r0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.581 0.581 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.091 0.511 tNET RR 1 IOT21[B] i2s_tx/daclrc_r0_s0/CLK
1.126 0.035 tUnc i2s_tx/daclrc_r0_s0
1.139 0.013 tHld 1 IOT21[B] i2s_tx/daclrc_r0_s0

Path Statistics:

Clock Skew 0.511
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%
Required Clock Path Delay cell: 0.581, 53.226%; route: 0.511, 46.774%

Path2

Path Summary:

Slack 0.122
Data Arrival Time 1.407
Data Required Time 1.285
From dacfifo_writedata_30_s0
To i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.087 0.506 tNET RR 1 R24C45[1][B] dacfifo_writedata_30_s0/CLK
1.231 0.144 tC2Q RR 1 R24C45[1][B] dacfifo_writedata_30_s0/Q
1.407 0.176 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[30]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.070 0.489 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA
1.285 0.215 tHld 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Path Statistics:

Clock Skew -0.017
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 53.459%; route: 0.506, 46.541%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.176, 55.000%; tC2Q: 0.144, 45.000%
Required Clock Path Delay cell: 0.581, 54.296%; route: 0.489, 45.704%

Path3

Path Summary:

Slack 0.122
Data Arrival Time 1.407
Data Required Time 1.285
From dacfifo_writedata_26_s0
To i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.087 0.506 tNET RR 1 R24C45[2][A] dacfifo_writedata_26_s0/CLK
1.231 0.144 tC2Q RR 1 R24C45[2][A] dacfifo_writedata_26_s0/Q
1.407 0.176 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[26]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.070 0.489 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA
1.285 0.215 tHld 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Path Statistics:

Clock Skew -0.017
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 53.459%; route: 0.506, 46.541%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.176, 55.000%; tC2Q: 0.144, 45.000%
Required Clock Path Delay cell: 0.581, 54.296%; route: 0.489, 45.704%

Path4

Path Summary:

Slack 0.123
Data Arrival Time 1.408
Data Required Time 1.285
From dacfifo_writedata_24_s0
To i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.075 0.494 tNET RR 1 R27C45[0][A] dacfifo_writedata_24_s0/CLK
1.219 0.144 tC2Q RR 1 R27C45[0][A] dacfifo_writedata_24_s0/Q
1.408 0.189 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[24]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.070 0.489 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA
1.285 0.215 tHld 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 54.044%; route: 0.494, 45.956%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay cell: 0.581, 54.296%; route: 0.489, 45.704%

Path5

Path Summary:

Slack 0.216
Data Arrival Time 1.492
Data Required Time 1.277
From i2s_rx/adcfifo_writedata_22_s0
To i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.581 0.581 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.061 0.480 tNET RR 1 R16C51[3][A] i2s_rx/adcfifo_writedata_22_s0/CLK
1.205 0.144 tC2Q RR 1 R16C51[3][A] i2s_rx/adcfifo_writedata_22_s0/Q
1.492 0.287 tNET RR 1 BSRAM_R28[14] i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[22]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.581 0.581 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.062 0.481 tNET RR 1 BSRAM_R28[14] i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA
1.277 0.215 tHld 1 BSRAM_R28[14] i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 54.744%; route: 0.480, 45.256%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.287, 66.589%; tC2Q: 0.144, 33.411%
Required Clock Path Delay cell: 0.581, 54.705%; route: 0.481, 45.295%

Path6

Path Summary:

Slack 0.218
Data Arrival Time 1.494
Data Required Time 1.277
From i2s_rx/adcfifo_writedata_14_s0
To i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.581 0.581 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.065 0.484 tNET RR 1 R16C50[1][B] i2s_rx/adcfifo_writedata_14_s0/CLK
1.209 0.144 tC2Q RR 1 R16C50[1][B] i2s_rx/adcfifo_writedata_14_s0/Q
1.494 0.285 tNET RR 1 BSRAM_R28[14] i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[14]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.581 0.581 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.062 0.481 tNET RR 1 BSRAM_R28[14] i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA
1.277 0.215 tHld 1 BSRAM_R28[14] i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Path Statistics:

Clock Skew -0.003
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 54.538%; route: 0.484, 45.462%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.285, 66.434%; tC2Q: 0.144, 33.566%
Required Clock Path Delay cell: 0.581, 54.705%; route: 0.481, 45.295%

Path7

Path Summary:

Slack 0.219
Data Arrival Time 1.504
Data Required Time 1.285
From dacfifo_writedata_16_s0
To i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.075 0.494 tNET RR 1 R27C45[0][B] dacfifo_writedata_16_s0/CLK
1.219 0.144 tC2Q RR 1 R27C45[0][B] dacfifo_writedata_16_s0/Q
1.504 0.285 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[16]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.070 0.489 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA
1.285 0.215 tHld 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 54.044%; route: 0.494, 45.956%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.285, 66.434%; tC2Q: 0.144, 33.566%
Required Clock Path Delay cell: 0.581, 54.296%; route: 0.489, 45.704%

Path8

Path Summary:

Slack 0.222
Data Arrival Time 1.498
Data Required Time 1.277
From i2s_rx/adcfifo_writedata_23_s0
To i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.581 0.581 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.069 0.488 tNET RR 1 R16C49[1][B] i2s_rx/adcfifo_writedata_23_s0/CLK
1.213 0.144 tC2Q RR 1 R16C49[1][B] i2s_rx/adcfifo_writedata_23_s0/Q
1.498 0.285 tNET RR 1 BSRAM_R28[14] i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[23]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.581 0.581 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.062 0.481 tNET RR 1 BSRAM_R28[14] i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA
1.277 0.215 tHld 1 BSRAM_R28[14] i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Path Statistics:

Clock Skew -0.007
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 54.334%; route: 0.488, 45.666%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.285, 66.434%; tC2Q: 0.144, 33.566%
Required Clock Path Delay cell: 0.581, 54.705%; route: 0.481, 45.295%

Path9

Path Summary:

Slack 0.230
Data Arrival Time 1.515
Data Required Time 1.285
From dacfifo_writedata_23_s0
To i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.080 0.499 tNET RR 1 R26C45[1][A] dacfifo_writedata_23_s0/CLK
1.224 0.144 tC2Q RR 1 R26C45[1][A] dacfifo_writedata_23_s0/Q
1.515 0.291 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[23]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.070 0.489 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA
1.285 0.215 tHld 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 53.793%; route: 0.499, 46.207%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.291, 66.897%; tC2Q: 0.144, 33.103%
Required Clock Path Delay cell: 0.581, 54.296%; route: 0.489, 45.704%

Path10

Path Summary:

Slack 0.230
Data Arrival Time 1.515
Data Required Time 1.285
From dacfifo_writedata_20_s0
To i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.080 0.499 tNET RR 1 R26C45[2][B] dacfifo_writedata_20_s0/CLK
1.224 0.144 tC2Q RR 1 R26C45[2][B] dacfifo_writedata_20_s0/Q
1.515 0.291 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[20]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.070 0.489 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA
1.285 0.215 tHld 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 53.793%; route: 0.499, 46.207%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.291, 66.897%; tC2Q: 0.144, 33.103%
Required Clock Path Delay cell: 0.581, 54.296%; route: 0.489, 45.704%

Path11

Path Summary:

Slack 0.262
Data Arrival Time 1.546
Data Required Time 1.285
From dacfifo_writedata_10_s0
To i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.083 0.502 tNET RR 1 R26C46[3][A] dacfifo_writedata_10_s0/CLK
1.227 0.144 tC2Q RR 1 R26C46[3][A] dacfifo_writedata_10_s0/Q
1.546 0.319 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[10]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.070 0.489 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA
1.285 0.215 tHld 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Path Statistics:

Clock Skew -0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 53.620%; route: 0.502, 46.380%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.319, 68.898%; tC2Q: 0.144, 31.102%
Required Clock Path Delay cell: 0.581, 54.296%; route: 0.489, 45.704%

Path12

Path Summary:

Slack 0.262
Data Arrival Time 1.546
Data Required Time 1.285
From dacfifo_writedata_9_s0
To i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.083 0.502 tNET RR 1 R26C46[2][A] dacfifo_writedata_9_s0/CLK
1.227 0.144 tC2Q RR 1 R26C46[2][A] dacfifo_writedata_9_s0/Q
1.546 0.319 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.070 0.489 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA
1.285 0.215 tHld 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Path Statistics:

Clock Skew -0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 53.620%; route: 0.502, 46.380%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.319, 68.898%; tC2Q: 0.144, 31.102%
Required Clock Path Delay cell: 0.581, 54.296%; route: 0.489, 45.704%

Path13

Path Summary:

Slack 0.269
Data Arrival Time 1.553
Data Required Time 1.285
From dacfifo_writedata_17_s0
To i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.078 0.498 tNET RR 1 R27C46[0][A] dacfifo_writedata_17_s0/CLK
1.222 0.144 tC2Q RR 1 R27C46[0][A] dacfifo_writedata_17_s0/Q
1.553 0.331 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[17]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.070 0.489 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA
1.285 0.215 tHld 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Path Statistics:

Clock Skew -0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 53.868%; route: 0.498, 46.132%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.331, 69.684%; tC2Q: 0.144, 30.316%
Required Clock Path Delay cell: 0.581, 54.296%; route: 0.489, 45.704%

Path14

Path Summary:

Slack 0.274
Data Arrival Time 1.550
Data Required Time 1.277
From i2s_rx/adcfifo_writedata_1_s0
To i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.581 0.581 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.065 0.484 tNET RR 1 R16C48[1][A] i2s_rx/adcfifo_writedata_1_s0/CLK
1.209 0.144 tC2Q RR 1 R16C48[1][A] i2s_rx/adcfifo_writedata_1_s0/Q
1.550 0.341 tNET RR 1 BSRAM_R28[14] i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.581 0.581 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.062 0.481 tNET RR 1 BSRAM_R28[14] i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA
1.277 0.215 tHld 1 BSRAM_R28[14] i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Path Statistics:

Clock Skew -0.003
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 54.538%; route: 0.484, 45.462%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.341, 70.309%; tC2Q: 0.144, 29.691%
Required Clock Path Delay cell: 0.581, 54.705%; route: 0.481, 45.295%

Path15

Path Summary:

Slack 0.275
Data Arrival Time 1.356
Data Required Time 1.081
From WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/state.GEN_STO_s0
To WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/state.GEN_STO_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.056 0.475 tNET RR 1 R14C43[0][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/state.GEN_STO_s0/CLK
1.197 0.141 tC2Q RF 12 R14C43[0][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/state.GEN_STO_s0/Q
1.203 0.006 tNET FF 1 R14C43[0][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/n494_s13/I2
1.356 0.153 tINS FF 1 R14C43[0][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/n494_s13/F
1.356 0.000 tNET FF 1 R14C43[0][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/state.GEN_STO_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.056 0.475 tNET RR 1 R14C43[0][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/state.GEN_STO_s0/CLK
1.081 0.025 tHld 1 R14C43[0][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/state.GEN_STO_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.581, 55.016%; route: 0.475, 44.984%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.581, 55.016%; route: 0.475, 44.984%

Path16

Path Summary:

Slack 0.275
Data Arrival Time 1.390
Data Required Time 1.115
From WM8960_Init/I2C_Init_Dev/i2c_control/Cmd_0_s1
To WM8960_Init/I2C_Init_Dev/i2c_control/Cmd_0_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.090 0.509 tNET RR 1 R20C40[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/Cmd_0_s1/CLK
1.231 0.141 tC2Q RF 6 R20C40[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/Cmd_0_s1/Q
1.237 0.006 tNET FF 1 R20C40[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/n274_s7/I1
1.390 0.153 tINS FF 1 R20C40[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/n274_s7/F
1.390 0.000 tNET FF 1 R20C40[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/Cmd_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.090 0.509 tNET RR 1 R20C40[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/Cmd_0_s1/CLK
1.115 0.025 tHld 1 R20C40[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/Cmd_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.581, 53.312%; route: 0.509, 46.688%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.581, 53.312%; route: 0.509, 46.688%

Path17

Path Summary:

Slack 0.275
Data Arrival Time 1.365
Data Required Time 1.090
From WM8960_Init/I2C_Init_Dev/wrreg_req_s5
To WM8960_Init/I2C_Init_Dev/wrreg_req_s5
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.065 0.484 tNET RR 1 R16C44[0][A] WM8960_Init/I2C_Init_Dev/wrreg_req_s5/CLK
1.206 0.141 tC2Q RF 3 R16C44[0][A] WM8960_Init/I2C_Init_Dev/wrreg_req_s5/Q
1.212 0.006 tNET FF 1 R16C44[0][A] WM8960_Init/I2C_Init_Dev/n75_s7/I0
1.365 0.153 tINS FF 1 R16C44[0][A] WM8960_Init/I2C_Init_Dev/n75_s7/F
1.365 0.000 tNET FF 1 R16C44[0][A] WM8960_Init/I2C_Init_Dev/wrreg_req_s5/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.065 0.484 tNET RR 1 R16C44[0][A] WM8960_Init/I2C_Init_Dev/wrreg_req_s5/CLK
1.090 0.025 tHld 1 R16C44[0][A] WM8960_Init/I2C_Init_Dev/wrreg_req_s5

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.581, 54.538%; route: 0.484, 45.462%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.581, 54.538%; route: 0.484, 45.462%

Path18

Path Summary:

Slack 0.275
Data Arrival Time 1.560
Data Required Time 1.285
From dacfifo_writedata_25_s0
To i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.085 0.504 tNET RR 1 R25C45[1][A] dacfifo_writedata_25_s0/CLK
1.229 0.144 tC2Q RR 1 R25C45[1][A] dacfifo_writedata_25_s0/Q
1.560 0.331 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[25]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.070 0.489 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA
1.285 0.215 tHld 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Path Statistics:

Clock Skew -0.015
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 53.545%; route: 0.504, 46.455%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.331, 69.684%; tC2Q: 0.144, 30.316%
Required Clock Path Delay cell: 0.581, 54.296%; route: 0.489, 45.704%

Path19

Path Summary:

Slack 0.278
Data Arrival Time 1.369
Data Required Time 1.091
From i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_8_s0
To i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_8_s0
Launch Clk I2S_BCLK:[R]
Latch Clk I2S_BCLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.581 0.581 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.066 0.485 tNET RR 1 R17C48[0][A] i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_8_s0/CLK
1.207 0.141 tC2Q RF 4 R17C48[0][A] i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_8_s0/Q
1.216 0.009 tNET FF 1 R17C48[0][A] i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_next_8_s2/I1
1.369 0.153 tINS FF 1 R17C48[0][A] i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_next_8_s2/F
1.369 0.000 tNET FF 1 R17C48[0][A] i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR 1 IOT3[B] I2S_BCLK_ibuf/I
0.581 0.581 tINS RR 204 IOT3[B] I2S_BCLK_ibuf/O
1.066 0.485 tNET RR 1 R17C48[0][A] i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_8_s0/CLK
1.091 0.025 tHld 1 R17C48[0][A] i2s_rx/adc_fifo/async_fifo_ctrl_inst/wr_pntr_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.581, 54.474%; route: 0.485, 45.526%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.581, 54.474%; route: 0.485, 45.526%

Path20

Path Summary:

Slack 0.278
Data Arrival Time 1.359
Data Required Time 1.081
From WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_2_s3
To WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_2_s3
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.056 0.475 tNET RR 1 R14C43[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_2_s3/CLK
1.197 0.141 tC2Q RF 9 R14C43[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_2_s3/Q
1.206 0.009 tNET FF 1 R14C43[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/n497_s21/I1
1.359 0.153 tINS FF 1 R14C43[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/n497_s21/F
1.359 0.000 tNET FF 1 R14C43[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_2_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.056 0.475 tNET RR 1 R14C43[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_2_s3/CLK
1.081 0.025 tHld 1 R14C43[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_2_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.581, 55.016%; route: 0.475, 44.984%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.581, 55.016%; route: 0.475, 44.984%

Path21

Path Summary:

Slack 0.278
Data Arrival Time 1.364
Data Required Time 1.086
From WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_4_s4
To WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_4_s4
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.061 0.480 tNET RR 1 R16C43[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_4_s4/CLK
1.202 0.141 tC2Q RF 5 R16C43[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_4_s4/Q
1.211 0.009 tNET FF 1 R16C43[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/n495_s23/I0
1.364 0.153 tINS FF 1 R16C43[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/n495_s23/F
1.364 0.000 tNET FF 1 R16C43[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_4_s4/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.061 0.480 tNET RR 1 R16C43[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_4_s4/CLK
1.086 0.025 tHld 1 R16C43[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/i2c_bit_shift/cnt_4_s4

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.581, 54.744%; route: 0.480, 45.256%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.581, 54.744%; route: 0.480, 45.256%

Path22

Path Summary:

Slack 0.278
Data Arrival Time 1.397
Data Required Time 1.119
From WM8960_Init/I2C_Init_Dev/i2c_control/cnt_0_s0
To WM8960_Init/I2C_Init_Dev/i2c_control/cnt_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.094 0.513 tNET RR 1 R20C41[0][A] WM8960_Init/I2C_Init_Dev/i2c_control/cnt_0_s0/CLK
1.235 0.141 tC2Q RF 11 R20C41[0][A] WM8960_Init/I2C_Init_Dev/i2c_control/cnt_0_s0/Q
1.244 0.009 tNET FF 1 R20C41[0][A] WM8960_Init/I2C_Init_Dev/i2c_control/n240_s11/I0
1.397 0.153 tINS FF 1 R20C41[0][A] WM8960_Init/I2C_Init_Dev/i2c_control/n240_s11/F
1.397 0.000 tNET FF 1 R20C41[0][A] WM8960_Init/I2C_Init_Dev/i2c_control/cnt_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.094 0.513 tNET RR 1 R20C41[0][A] WM8960_Init/I2C_Init_Dev/i2c_control/cnt_0_s0/CLK
1.119 0.025 tHld 1 R20C41[0][A] WM8960_Init/I2C_Init_Dev/i2c_control/cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.581, 53.117%; route: 0.513, 46.883%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.581, 53.117%; route: 0.513, 46.883%

Path23

Path Summary:

Slack 0.278
Data Arrival Time 1.397
Data Required Time 1.119
From WM8960_Init/I2C_Init_Dev/i2c_control/cnt_1_s0
To WM8960_Init/I2C_Init_Dev/i2c_control/cnt_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.094 0.513 tNET RR 1 R20C41[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/cnt_1_s0/CLK
1.235 0.141 tC2Q RF 10 R20C41[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/cnt_1_s0/Q
1.244 0.009 tNET FF 1 R20C41[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/n238_s10/I2
1.397 0.153 tINS FF 1 R20C41[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/n238_s10/F
1.397 0.000 tNET FF 1 R20C41[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/cnt_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.094 0.513 tNET RR 1 R20C41[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/cnt_1_s0/CLK
1.119 0.025 tHld 1 R20C41[1][A] WM8960_Init/I2C_Init_Dev/i2c_control/cnt_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.581, 53.117%; route: 0.513, 46.883%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.581, 53.117%; route: 0.513, 46.883%

Path24

Path Summary:

Slack 0.278
Data Arrival Time 1.363
Data Required Time 1.085
From WM8960_Init/I2C_Init_Dev/cnt_4_s1
To WM8960_Init/I2C_Init_Dev/cnt_4_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.060 0.479 tNET RR 1 R14C44[0][A] WM8960_Init/I2C_Init_Dev/cnt_4_s1/CLK
1.201 0.141 tC2Q RF 4 R14C44[0][A] WM8960_Init/I2C_Init_Dev/cnt_4_s1/Q
1.210 0.009 tNET FF 1 R14C44[0][A] WM8960_Init/I2C_Init_Dev/n22_s3/I1
1.363 0.153 tINS FF 1 R14C44[0][A] WM8960_Init/I2C_Init_Dev/n22_s3/F
1.363 0.000 tNET FF 1 R14C44[0][A] WM8960_Init/I2C_Init_Dev/cnt_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.060 0.479 tNET RR 1 R14C44[0][A] WM8960_Init/I2C_Init_Dev/cnt_4_s1/CLK
1.085 0.025 tHld 1 R14C44[0][A] WM8960_Init/I2C_Init_Dev/cnt_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.581, 54.808%; route: 0.479, 45.192%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.581, 54.808%; route: 0.479, 45.192%

Path25

Path Summary:

Slack 0.287
Data Arrival Time 1.571
Data Required Time 1.285
From dacfifo_writedata_6_s0
To i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.083 0.502 tNET RR 1 R26C46[1][B] dacfifo_writedata_6_s0/CLK
1.227 0.144 tC2Q RR 1 R26C46[1][B] dacfifo_writedata_6_s0/Q
1.571 0.344 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.581 0.581 tINS RR 219 IOB29[A] clk_ibuf/O
1.070 0.489 tNET RR 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA
1.285 0.215 tHld 1 BSRAM_R28[12] i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Path Statistics:

Clock Skew -0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 53.620%; route: 0.502, 46.380%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.344, 70.492%; tC2Q: 0.144, 29.508%
Required Clock Path Delay cell: 0.581, 54.296%; route: 0.489, 45.704%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 3.563
Actual Width: 4.425
Required Width: 0.862
Type: Low Pulse Width
Clock: I2S_BCLK
Objects: i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF I2S_BCLK_ibuf/I
5.591 0.591 tINS FF I2S_BCLK_ibuf/O
6.641 1.049 tNET FF i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 I2S_BCLK
10.000 0.000 tCL RR I2S_BCLK_ibuf/I
10.581 0.581 tINS RR I2S_BCLK_ibuf/O
11.066 0.485 tNET RR i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKB

MPW2

MPW Summary:

Slack: 3.567
Actual Width: 4.429
Required Width: 0.862
Type: Low Pulse Width
Clock: I2S_BCLK
Objects: i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF I2S_BCLK_ibuf/I
5.591 0.591 tINS FF I2S_BCLK_ibuf/O
6.633 1.042 tNET FF i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 I2S_BCLK
10.000 0.000 tCL RR I2S_BCLK_ibuf/I
10.581 0.581 tINS RR I2S_BCLK_ibuf/O
11.062 0.481 tNET RR i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA

MPW3

MPW Summary:

Slack: 3.573
Actual Width: 4.435
Required Width: 0.862
Type: High Pulse Width
Clock: I2S_BCLK
Objects: i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR I2S_BCLK_ibuf/I
0.587 0.587 tINS RR I2S_BCLK_ibuf/O
1.637 1.050 tNET RR i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF I2S_BCLK_ibuf/I
5.583 0.583 tINS FF I2S_BCLK_ibuf/O
6.072 0.490 tNET FF i2s_tx/dac_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKB

MPW4

MPW Summary:

Slack: 3.577
Actual Width: 4.439
Required Width: 0.862
Type: High Pulse Width
Clock: I2S_BCLK
Objects: i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 I2S_BCLK
0.000 0.000 tCL RR I2S_BCLK_ibuf/I
0.587 0.587 tINS RR I2S_BCLK_ibuf/O
1.630 1.043 tNET RR i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 I2S_BCLK
5.000 0.000 tCL FF I2S_BCLK_ibuf/I
5.583 0.583 tINS FF I2S_BCLK_ibuf/O
6.068 0.486 tNET FF i2s_rx/adc_fifo/dpram_inst/use_bram.ram_use_bram.ram_0_0_s/CLKA

MPW5

MPW Summary:

Slack: 3.832
Actual Width: 4.032
Required Width: 0.200
Type: Low Pulse Width
Clock: I2S_DACLRC
Objects: i2s_tx/dacfifo_rddata_r0_23_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 I2S_DACLRC
5.000 0.000 tCL FF I2S_DACLRC_ibuf/I
5.591 0.591 tINS FF I2S_DACLRC_ibuf/O
7.763 2.172 tNET FF i2s_tx/dacfifo_rddata_r0_23_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 I2S_DACLRC
10.000 0.000 tCL RR I2S_DACLRC_ibuf/I
10.581 0.581 tINS RR I2S_DACLRC_ibuf/O
11.795 1.214 tNET RR i2s_tx/dacfifo_rddata_r0_23_s0/CLK

MPW6

MPW Summary:

Slack: 3.832
Actual Width: 4.032
Required Width: 0.200
Type: Low Pulse Width
Clock: I2S_DACLRC
Objects: i2s_tx/dacfifo_rddata_r0_14_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 I2S_DACLRC
5.000 0.000 tCL FF I2S_DACLRC_ibuf/I
5.591 0.591 tINS FF I2S_DACLRC_ibuf/O
7.763 2.172 tNET FF i2s_tx/dacfifo_rddata_r0_14_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 I2S_DACLRC
10.000 0.000 tCL RR I2S_DACLRC_ibuf/I
10.581 0.581 tINS RR I2S_DACLRC_ibuf/O
11.795 1.214 tNET RR i2s_tx/dacfifo_rddata_r0_14_s0/CLK

MPW7

MPW Summary:

Slack: 3.832
Actual Width: 4.032
Required Width: 0.200
Type: Low Pulse Width
Clock: I2S_DACLRC
Objects: i2s_tx/dacfifo_rddata_r0_25_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 I2S_DACLRC
5.000 0.000 tCL FF I2S_DACLRC_ibuf/I
5.591 0.591 tINS FF I2S_DACLRC_ibuf/O
7.757 2.166 tNET FF i2s_tx/dacfifo_rddata_r0_25_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 I2S_DACLRC
10.000 0.000 tCL RR I2S_DACLRC_ibuf/I
10.581 0.581 tINS RR I2S_DACLRC_ibuf/O
11.790 1.209 tNET RR i2s_tx/dacfifo_rddata_r0_25_s0/CLK

MPW8

MPW Summary:

Slack: 3.832
Actual Width: 4.032
Required Width: 0.200
Type: Low Pulse Width
Clock: I2S_DACLRC
Objects: i2s_tx/dacfifo_rddata_r0_24_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 I2S_DACLRC
5.000 0.000 tCL FF I2S_DACLRC_ibuf/I
5.591 0.591 tINS FF I2S_DACLRC_ibuf/O
7.757 2.166 tNET FF i2s_tx/dacfifo_rddata_r0_24_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 I2S_DACLRC
10.000 0.000 tCL RR I2S_DACLRC_ibuf/I
10.581 0.581 tINS RR I2S_DACLRC_ibuf/O
11.790 1.209 tNET RR i2s_tx/dacfifo_rddata_r0_24_s0/CLK

MPW9

MPW Summary:

Slack: 3.834
Actual Width: 4.034
Required Width: 0.200
Type: Low Pulse Width
Clock: I2S_DACLRC
Objects: i2s_tx/dacfifo_rddata_r0_30_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 I2S_DACLRC
5.000 0.000 tCL FF I2S_DACLRC_ibuf/I
5.591 0.591 tINS FF I2S_DACLRC_ibuf/O
7.762 2.171 tNET FF i2s_tx/dacfifo_rddata_r0_30_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 I2S_DACLRC
10.000 0.000 tCL RR I2S_DACLRC_ibuf/I
10.581 0.581 tINS RR I2S_DACLRC_ibuf/O
11.796 1.215 tNET RR i2s_tx/dacfifo_rddata_r0_30_s0/CLK

MPW10

MPW Summary:

Slack: 3.834
Actual Width: 4.034
Required Width: 0.200
Type: Low Pulse Width
Clock: I2S_DACLRC
Objects: i2s_tx/dacfifo_rddata_r0_29_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 I2S_DACLRC
5.000 0.000 tCL FF I2S_DACLRC_ibuf/I
5.591 0.591 tINS FF I2S_DACLRC_ibuf/O
7.762 2.171 tNET FF i2s_tx/dacfifo_rddata_r0_29_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 I2S_DACLRC
10.000 0.000 tCL RR I2S_DACLRC_ibuf/I
10.581 0.581 tINS RR I2S_DACLRC_ibuf/O
11.796 1.215 tNET RR i2s_tx/dacfifo_rddata_r0_29_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
219 clk_d 8.866 1.093
204 I2S_BCLK_d 1.133 1.087
35 I2S_DACLRC_d 3.277 2.305
34 adcfifo_read 15.300 1.494
32 n335_8 7.050 1.092
32 dacfifo_rden 7.637 1.042
32 n200_6 15.630 2.527
32 adcdat_r1 6.064 3.549
31 bit_cnt_7_10 5.722 0.864
30 bit_cnt[3] 5.923 0.994

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R20C42 45.83%
R18C42 38.89%
R18C47 37.50%
R14C48 34.72%
R28C48 34.72%
R13C48 33.33%
R23C45 33.33%
R20C41 33.33%
R16C40 33.33%
R28C47 33.33%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command