#include "COMMON.h"
#include "xi2srx.h"
#include "xi2stx.h"

#define FS_KHZ 			96000		//Ƶ96KHz
#define MCLK_KHZ		12288000	//ʱƵ128*fs KHz12.288MHz
#define WM8960_ADDR		0x10		//WM8960ַ
#define IIC_SCLK_RATE	100000		//I2Cͨ

//WM8960дĴ
//#define	WM8960_Write_Reg(REG,DATA)	PS_IIC_Write_Reg(&IIC0,WM8960_ADDR,REG8,(REG<<1)|(DATA>>8), DATA&0xFF)
#define	ES8388_Write_Reg(REG,DATA)	PS_IIC_Write_Reg(&IIC0,WM8960_ADDR,REG8,REG, DATA&0xFF)

//ʵ
XI2s_Rx I2s_Rx;
XI2s_Tx I2s_Tx;

int main()
{
	//ö
	XI2srx_Config *I2s_Rx_Config;
	XI2stx_Config *I2s_Tx_Config;

    //ʼ I2S Receiver
    I2s_Rx_Config = XI2s_Rx_LookupConfig(XPAR_XI2SRX_0_DEVICE_ID);
    XI2s_Rx_CfgInitialize(&I2s_Rx, I2s_Rx_Config, I2s_Rx_Config->BaseAddress);
    // I2S Receiver ģλʱBCLK
    XI2s_Rx_SetSclkOutDiv(&I2s_Rx, MCLK_KHZ, FS_KHZ);
    //ʹ I2S Receiver ģ
    XI2s_Rx_Enable(&I2s_Rx, TRUE);

    //ʼ I2S Transmitter
    I2s_Tx_Config = XI2s_Tx_LookupConfig(XPAR_XI2STX_0_DEVICE_ID);
    XI2s_Tx_CfgInitialize(&I2s_Tx, I2s_Tx_Config, I2s_Tx_Config->BaseAddress);
    // I2S Transmitter ģλʱBCLK
    XI2s_Tx_SetSclkOutDiv(&I2s_Tx, MCLK_KHZ, FS_KHZ);
    //ʹ I2S Transmitter ģ
    XI2s_Tx_Enable(&I2s_Tx,TRUE);

    //IICʼ
    PS_IIC_Init(&IIC0,XPAR_XIICPS_0_DEVICE_ID,100000);

    ES8388_Write_Reg(0x00, 0x80);       /* λES8388 */
    ES8388_Write_Reg(0x00, 0x16);
    usleep(500);                            /* ȴλ */

    ES8388_Write_Reg(0x01,0x58);
    ES8388_Write_Reg(0x01,0x50);
    ES8388_Write_Reg(0x01,0x50);
    ES8388_Write_Reg(0x02,0xF3);
    ES8388_Write_Reg(0x02,0xF0);
    ES8388_Write_Reg(0x2B,0x80); //ADCDACʹͬLRCK bit[7] Ϊ1
    ES8388_Write_Reg(0x00,0x36);
    ES8388_Write_Reg(0x08,0x00); //ģʽƼĴbit[7]1ģʽ,MCLK/SCLKıbit40 SCLKΪ2.0148M
    ES8388_Write_Reg(0x03,0x09);
    ES8388_Write_Reg(0x04,0x00);
    ES8388_Write_Reg(0x0f,0x60);//<-
    ES8388_Write_Reg(0x0D,0x20); //MCLKƵʵı      ADCLRCK=MCLK/ӦüĴ[40]512 16K
    ES8388_Write_Reg(0x18,0x20);
    ES8388_Write_Reg(0x05,0x00);
    ES8388_Write_Reg(0x06,0xc3);//c3<-
    ES8388_Write_Reg(0x0A,0x00); //Select Analog input channel for ADC (Lin1/Rin1)    LIN1:0X00                LIN20x52
    ES8388_Write_Reg(0x0B,0x02); //(Select LIN1and RIN1 as differential input pairs)  LIN1:0X02    LIN2:0x82
    ES8388_Write_Reg(0x0C,0x0c); //ADC Control: [1:0]=00(I2Sģʽ); [4:2]: 011: 16bit(0x0c); 000:24(0x00); 001:20(0x04); 010:18(0x08); 100:32(0x10)
//    ES8388_Write_Reg(0x0e,0x00);//<-
    ES8388_Write_Reg(0x17,0x18); //DAC Control: [2:1]=00(I2S);     [5:3]: 011: 16bit(0x18); 000:24(0x00); 001:20(0x08); 010:18(0x10); 100:32(0x20)
    ES8388_Write_Reg(0x10,0x00);//ADC
    ES8388_Write_Reg(0x11,0x00);
    ES8388_Write_Reg(0x1A,0x00);//DAC
    ES8388_Write_Reg(0x1B,0x00);
    ES8388_Write_Reg(0x1C,0xc8);//<-
    ES8388_Write_Reg(0x09,0x00);//棬3dbbit[7:4]ͨbit[3:0]ͨ
    ES8388_Write_Reg(0x12,0x11);//C0<-
    ES8388_Write_Reg(0x13,0x0a);
    ES8388_Write_Reg(0x14,0xaa);
    ES8388_Write_Reg(0x15,0x06);
    ES8388_Write_Reg(0x16,0xfb);//01
//    ES8388_Write_Reg(0x26,0x37);//<-
    ES8388_Write_Reg(0x27,0xb8);
    ES8388_Write_Reg(0x2A,0xb8);
    ES8388_Write_Reg(0x2D,0xFF);
    ES8388_Write_Reg(0x02,0x00);        //Ҫʱ500ms
    usleep(500);
//    ES8388_Write_Reg(0x2E,0x0F);
//    ES8388_Write_Reg(0x2F,0x0F);
//    ES8388_Write_Reg(0x30,0x0F);
//    ES8388_Write_Reg(0x31,0x0F);
    ES8388_Write_Reg(0x04,0x30);    //0x30:ʹOUT1 [4]:ROUT1 enable; [5]:LOUT1 enable; 0x06:ʹOUT2 [2]:ROUT2 enable;[3]:LOUT2 enable
    ES8388_Write_Reg(0x26,0x00);
    ES8388_Write_Reg(0x03,0x08);
    ES8388_Write_Reg(0x2E,0x1E);//LOUT1 volume
    ES8388_Write_Reg(0x2F,0x1E);//ROUT1 volume
    ES8388_Write_Reg(0x30,0x1E);//LOUT2 volume
    ES8388_Write_Reg(0x31,0x1E);//ROUT2 volume



    return 0;
}
