# Reading F:/app/xinquartus/modelsim_ase/tcl/vsim/pref.tcl 
# do adc_run_msim_rtl_verilog.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying F:\app\xinquartus\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied F:\app\xinquartus\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
# 
# vlog -vlog01compat -work work +incdir+C:/Users/27954/Desktop/class/adc/rtl {C:/Users/27954/Desktop/class/adc/rtl/adc.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module adc
# 
# Top level modules:
# 	adc
# 
# vlog -vlog01compat -work work +incdir+C:/Users/27954/Desktop/class/adc/prj/../testbench {C:/Users/27954/Desktop/class/adc/prj/../testbench/adc_tb.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module adc_tb
# 
# Top level modules:
# 	adc_tb
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  adc_tb
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps adc_tb 
# Loading work.adc_tb
# Loading work.adc
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
# ** Warning: (vsim-PLI-3410) Illegal character '-' in data on line 1 of file "./sine.txt".    : C:/Users/27954/Desktop/class/adc/prj/../testbench/adc_tb.v(41)
#    Time: 0 ps  Iteration: 0  Instance: /adc_tb
# ** Warning: (vsim-PLI-3410) Illegal character '-' in data on line 1 of file "./sine.txt".    : C:/Users/27954/Desktop/class/adc/prj/../testbench/adc_tb.v(41)
#    Time: 0 ps  Iteration: 0  Instance: /adc_tb
# Break key hit 
# Simulation stop requested.
